decode_impl.hh revision 8503:479b186a4652
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "arch/types.hh" 32#include "base/trace.hh" 33#include "config/full_system.hh" 34#include "config/the_isa.hh" 35#include "cpu/o3/decode.hh" 36#include "cpu/inst_seq.hh" 37#include "debug/Activity.hh" 38#include "debug/Decode.hh" 39#include "params/DerivO3CPU.hh" 40 41using namespace std; 42 43template<class Impl> 44DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 45 : cpu(_cpu), 46 renameToDecodeDelay(params->renameToDecodeDelay), 47 iewToDecodeDelay(params->iewToDecodeDelay), 48 commitToDecodeDelay(params->commitToDecodeDelay), 49 fetchToDecodeDelay(params->fetchToDecodeDelay), 50 decodeWidth(params->decodeWidth), 51 numThreads(params->numThreads) 52{ 53 _status = Inactive; 54 55 // Setup status, make sure stall signals are clear. 56 for (ThreadID tid = 0; tid < numThreads; ++tid) { 57 decodeStatus[tid] = Idle; 58 59 stalls[tid].rename = false; 60 stalls[tid].iew = false; 61 stalls[tid].commit = false; 62 } 63 64 // @todo: Make into a parameter 65 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 66} 67 68template <class Impl> 69std::string 70DefaultDecode<Impl>::name() const 71{ 72 return cpu->name() + ".decode"; 73} 74 75template <class Impl> 76void 77DefaultDecode<Impl>::regStats() 78{ 79 decodeIdleCycles 80 .name(name() + ".IdleCycles") 81 .desc("Number of cycles decode is idle") 82 .prereq(decodeIdleCycles); 83 decodeBlockedCycles 84 .name(name() + ".BlockedCycles") 85 .desc("Number of cycles decode is blocked") 86 .prereq(decodeBlockedCycles); 87 decodeRunCycles 88 .name(name() + ".RunCycles") 89 .desc("Number of cycles decode is running") 90 .prereq(decodeRunCycles); 91 decodeUnblockCycles 92 .name(name() + ".UnblockCycles") 93 .desc("Number of cycles decode is unblocking") 94 .prereq(decodeUnblockCycles); 95 decodeSquashCycles 96 .name(name() + ".SquashCycles") 97 .desc("Number of cycles decode is squashing") 98 .prereq(decodeSquashCycles); 99 decodeBranchResolved 100 .name(name() + ".BranchResolved") 101 .desc("Number of times decode resolved a branch") 102 .prereq(decodeBranchResolved); 103 decodeBranchMispred 104 .name(name() + ".BranchMispred") 105 .desc("Number of times decode detected a branch misprediction") 106 .prereq(decodeBranchMispred); 107 decodeControlMispred 108 .name(name() + ".ControlMispred") 109 .desc("Number of times decode detected an instruction incorrectly" 110 " predicted as a control") 111 .prereq(decodeControlMispred); 112 decodeDecodedInsts 113 .name(name() + ".DecodedInsts") 114 .desc("Number of instructions handled by decode") 115 .prereq(decodeDecodedInsts); 116 decodeSquashedInsts 117 .name(name() + ".SquashedInsts") 118 .desc("Number of squashed instructions handled by decode") 119 .prereq(decodeSquashedInsts); 120} 121 122template<class Impl> 123void 124DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 125{ 126 timeBuffer = tb_ptr; 127 128 // Setup wire to write information back to fetch. 129 toFetch = timeBuffer->getWire(0); 130 131 // Create wires to get information from proper places in time buffer. 132 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 135} 136 137template<class Impl> 138void 139DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 140{ 141 decodeQueue = dq_ptr; 142 143 // Setup wire to write information to proper place in decode queue. 144 toRename = decodeQueue->getWire(0); 145} 146 147template<class Impl> 148void 149DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 150{ 151 fetchQueue = fq_ptr; 152 153 // Setup wire to read information from fetch queue. 154 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 155} 156 157template<class Impl> 158void 159DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 160{ 161 activeThreads = at_ptr; 162} 163 164template <class Impl> 165bool 166DefaultDecode<Impl>::drain() 167{ 168 // Decode is done draining at any time. 169 cpu->signalDrained(); 170 return true; 171} 172 173template <class Impl> 174void 175DefaultDecode<Impl>::takeOverFrom() 176{ 177 _status = Inactive; 178 179 // Be sure to reset state and clear out any old instructions. 180 for (ThreadID tid = 0; tid < numThreads; ++tid) { 181 decodeStatus[tid] = Idle; 182 183 stalls[tid].rename = false; 184 stalls[tid].iew = false; 185 stalls[tid].commit = false; 186 while (!insts[tid].empty()) 187 insts[tid].pop(); 188 while (!skidBuffer[tid].empty()) 189 skidBuffer[tid].pop(); 190 branchCount[tid] = 0; 191 } 192 wroteToTimeBuffer = false; 193} 194 195template<class Impl> 196bool 197DefaultDecode<Impl>::checkStall(ThreadID tid) const 198{ 199 bool ret_val = false; 200 201 if (stalls[tid].rename) { 202 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 203 ret_val = true; 204 } else if (stalls[tid].iew) { 205 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 206 ret_val = true; 207 } else if (stalls[tid].commit) { 208 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 209 ret_val = true; 210 } 211 212 return ret_val; 213} 214 215template<class Impl> 216inline bool 217DefaultDecode<Impl>::fetchInstsValid() 218{ 219 return fromFetch->size > 0; 220} 221 222template<class Impl> 223bool 224DefaultDecode<Impl>::block(ThreadID tid) 225{ 226 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 227 228 // Add the current inputs to the skid buffer so they can be 229 // reprocessed when this stage unblocks. 230 skidInsert(tid); 231 232 // If the decode status is blocked or unblocking then decode has not yet 233 // signalled fetch to unblock. In that case, there is no need to tell 234 // fetch to block. 235 if (decodeStatus[tid] != Blocked) { 236 // Set the status to Blocked. 237 decodeStatus[tid] = Blocked; 238 239 if (decodeStatus[tid] != Unblocking) { 240 toFetch->decodeBlock[tid] = true; 241 wroteToTimeBuffer = true; 242 } 243 244 return true; 245 } 246 247 return false; 248} 249 250template<class Impl> 251bool 252DefaultDecode<Impl>::unblock(ThreadID tid) 253{ 254 // Decode is done unblocking only if the skid buffer is empty. 255 if (skidBuffer[tid].empty()) { 256 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 257 toFetch->decodeUnblock[tid] = true; 258 wroteToTimeBuffer = true; 259 260 decodeStatus[tid] = Running; 261 return true; 262 } 263 264 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 265 266 return false; 267} 268 269template<class Impl> 270void 271DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 272{ 273 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 274 "prediction detected at decode.\n", tid, inst->seqNum); 275 276 // Send back mispredict information. 277 toFetch->decodeInfo[tid].branchMispredict = true; 278 toFetch->decodeInfo[tid].predIncorrect = true; 279 toFetch->decodeInfo[tid].squash = true; 280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 281 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 282 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 283 toFetch->decodeInfo[tid].squashInst = inst; 284 285 InstSeqNum squash_seq_num = inst->seqNum; 286 287 // Might have to tell fetch to unblock. 288 if (decodeStatus[tid] == Blocked || 289 decodeStatus[tid] == Unblocking) { 290 toFetch->decodeUnblock[tid] = 1; 291 } 292 293 // Set status to squashing. 294 decodeStatus[tid] = Squashing; 295 296 for (int i=0; i<fromFetch->size; i++) { 297 if (fromFetch->insts[i]->threadNumber == tid && 298 fromFetch->insts[i]->seqNum > squash_seq_num) { 299 fromFetch->insts[i]->setSquashed(); 300 } 301 } 302 303 // Clear the instruction list and skid buffer in case they have any 304 // insts in them. 305 while (!insts[tid].empty()) { 306 insts[tid].pop(); 307 } 308 309 while (!skidBuffer[tid].empty()) { 310 skidBuffer[tid].pop(); 311 } 312 313 // Squash instructions up until this one 314 cpu->removeInstsUntil(squash_seq_num, tid); 315} 316 317template<class Impl> 318unsigned 319DefaultDecode<Impl>::squash(ThreadID tid) 320{ 321 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 322 323 if (decodeStatus[tid] == Blocked || 324 decodeStatus[tid] == Unblocking) { 325#if !FULL_SYSTEM 326 // In syscall emulation, we can have both a block and a squash due 327 // to a syscall in the same cycle. This would cause both signals to 328 // be high. This shouldn't happen in full system. 329 // @todo: Determine if this still happens. 330 if (toFetch->decodeBlock[tid]) { 331 toFetch->decodeBlock[tid] = 0; 332 } else { 333 toFetch->decodeUnblock[tid] = 1; 334 } 335#else 336 toFetch->decodeUnblock[tid] = 1; 337#endif 338 } 339 340 // Set status to squashing. 341 decodeStatus[tid] = Squashing; 342 343 // Go through incoming instructions from fetch and squash them. 344 unsigned squash_count = 0; 345 346 for (int i=0; i<fromFetch->size; i++) { 347 if (fromFetch->insts[i]->threadNumber == tid) { 348 fromFetch->insts[i]->setSquashed(); 349 squash_count++; 350 } 351 } 352 353 // Clear the instruction list and skid buffer in case they have any 354 // insts in them. 355 while (!insts[tid].empty()) { 356 insts[tid].pop(); 357 } 358 359 while (!skidBuffer[tid].empty()) { 360 skidBuffer[tid].pop(); 361 } 362 363 return squash_count; 364} 365 366template<class Impl> 367void 368DefaultDecode<Impl>::skidInsert(ThreadID tid) 369{ 370 DynInstPtr inst = NULL; 371 372 while (!insts[tid].empty()) { 373 inst = insts[tid].front(); 374 375 insts[tid].pop(); 376 377 assert(tid == inst->threadNumber); 378 379 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 380 inst->seqNum, inst->pcState(), inst->threadNumber); 381 382 skidBuffer[tid].push(inst); 383 } 384 385 // @todo: Eventually need to enforce this by not letting a thread 386 // fetch past its skidbuffer 387 assert(skidBuffer[tid].size() <= skidBufferMax); 388} 389 390template<class Impl> 391bool 392DefaultDecode<Impl>::skidsEmpty() 393{ 394 list<ThreadID>::iterator threads = activeThreads->begin(); 395 list<ThreadID>::iterator end = activeThreads->end(); 396 397 while (threads != end) { 398 ThreadID tid = *threads++; 399 if (!skidBuffer[tid].empty()) 400 return false; 401 } 402 403 return true; 404} 405 406template<class Impl> 407void 408DefaultDecode<Impl>::updateStatus() 409{ 410 bool any_unblocking = false; 411 412 list<ThreadID>::iterator threads = activeThreads->begin(); 413 list<ThreadID>::iterator end = activeThreads->end(); 414 415 while (threads != end) { 416 ThreadID tid = *threads++; 417 418 if (decodeStatus[tid] == Unblocking) { 419 any_unblocking = true; 420 break; 421 } 422 } 423 424 // Decode will have activity if it's unblocking. 425 if (any_unblocking) { 426 if (_status == Inactive) { 427 _status = Active; 428 429 DPRINTF(Activity, "Activating stage.\n"); 430 431 cpu->activateStage(O3CPU::DecodeIdx); 432 } 433 } else { 434 // If it's not unblocking, then decode will not have any internal 435 // activity. Switch it to inactive. 436 if (_status == Active) { 437 _status = Inactive; 438 DPRINTF(Activity, "Deactivating stage.\n"); 439 440 cpu->deactivateStage(O3CPU::DecodeIdx); 441 } 442 } 443} 444 445template <class Impl> 446void 447DefaultDecode<Impl>::sortInsts() 448{ 449 int insts_from_fetch = fromFetch->size; 450#ifdef DEBUG 451 for (ThreadID tid = 0; tid < numThreads; tid++) 452 assert(insts[tid].empty()); 453#endif 454 for (int i = 0; i < insts_from_fetch; ++i) { 455 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 456 } 457} 458 459template<class Impl> 460void 461DefaultDecode<Impl>::readStallSignals(ThreadID tid) 462{ 463 if (fromRename->renameBlock[tid]) { 464 stalls[tid].rename = true; 465 } 466 467 if (fromRename->renameUnblock[tid]) { 468 assert(stalls[tid].rename); 469 stalls[tid].rename = false; 470 } 471 472 if (fromIEW->iewBlock[tid]) { 473 stalls[tid].iew = true; 474 } 475 476 if (fromIEW->iewUnblock[tid]) { 477 assert(stalls[tid].iew); 478 stalls[tid].iew = false; 479 } 480 481 if (fromCommit->commitBlock[tid]) { 482 stalls[tid].commit = true; 483 } 484 485 if (fromCommit->commitUnblock[tid]) { 486 assert(stalls[tid].commit); 487 stalls[tid].commit = false; 488 } 489} 490 491template <class Impl> 492bool 493DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 494{ 495 // Check if there's a squash signal, squash if there is. 496 // Check stall signals, block if necessary. 497 // If status was blocked 498 // Check if stall conditions have passed 499 // if so then go to unblocking 500 // If status was Squashing 501 // check if squashing is not high. Switch to running this cycle. 502 503 // Update the per thread stall statuses. 504 readStallSignals(tid); 505 506 // Check squash signals from commit. 507 if (fromCommit->commitInfo[tid].squash) { 508 509 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 510 "from commit.\n", tid); 511 512 squash(tid); 513 514 return true; 515 } 516 517 // Check ROB squash signals from commit. 518 if (fromCommit->commitInfo[tid].robSquashing) { 519 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 520 521 // Continue to squash. 522 decodeStatus[tid] = Squashing; 523 524 return true; 525 } 526 527 if (checkStall(tid)) { 528 return block(tid); 529 } 530 531 if (decodeStatus[tid] == Blocked) { 532 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 533 tid); 534 535 decodeStatus[tid] = Unblocking; 536 537 unblock(tid); 538 539 return true; 540 } 541 542 if (decodeStatus[tid] == Squashing) { 543 // Switch status to running if decode isn't being told to block or 544 // squash this cycle. 545 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 546 tid); 547 548 decodeStatus[tid] = Running; 549 550 return false; 551 } 552 553 // If we've reached this point, we have not gotten any signals that 554 // cause decode to change its status. Decode remains the same as before. 555 return false; 556} 557 558template<class Impl> 559void 560DefaultDecode<Impl>::tick() 561{ 562 wroteToTimeBuffer = false; 563 564 bool status_change = false; 565 566 toRenameIndex = 0; 567 568 list<ThreadID>::iterator threads = activeThreads->begin(); 569 list<ThreadID>::iterator end = activeThreads->end(); 570 571 sortInsts(); 572 573 //Check stall and squash signals. 574 while (threads != end) { 575 ThreadID tid = *threads++; 576 577 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 578 status_change = checkSignalsAndUpdate(tid) || status_change; 579 580 decode(status_change, tid); 581 } 582 583 if (status_change) { 584 updateStatus(); 585 } 586 587 if (wroteToTimeBuffer) { 588 DPRINTF(Activity, "Activity this cycle.\n"); 589 590 cpu->activityThisCycle(); 591 } 592} 593 594template<class Impl> 595void 596DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 597{ 598 // If status is Running or idle, 599 // call decodeInsts() 600 // If status is Unblocking, 601 // buffer any instructions coming from fetch 602 // continue trying to empty skid buffer 603 // check if stall conditions have passed 604 605 if (decodeStatus[tid] == Blocked) { 606 ++decodeBlockedCycles; 607 } else if (decodeStatus[tid] == Squashing) { 608 ++decodeSquashCycles; 609 } 610 611 // Decode should try to decode as many instructions as its bandwidth 612 // will allow, as long as it is not currently blocked. 613 if (decodeStatus[tid] == Running || 614 decodeStatus[tid] == Idle) { 615 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 616 "stage.\n",tid); 617 618 decodeInsts(tid); 619 } else if (decodeStatus[tid] == Unblocking) { 620 // Make sure that the skid buffer has something in it if the 621 // status is unblocking. 622 assert(!skidsEmpty()); 623 624 // If the status was unblocking, then instructions from the skid 625 // buffer were used. Remove those instructions and handle 626 // the rest of unblocking. 627 decodeInsts(tid); 628 629 if (fetchInstsValid()) { 630 // Add the current inputs to the skid buffer so they can be 631 // reprocessed when this stage unblocks. 632 skidInsert(tid); 633 } 634 635 status_change = unblock(tid) || status_change; 636 } 637} 638 639template <class Impl> 640void 641DefaultDecode<Impl>::decodeInsts(ThreadID tid) 642{ 643 // Instructions can come either from the skid buffer or the list of 644 // instructions coming from fetch, depending on decode's status. 645 int insts_available = decodeStatus[tid] == Unblocking ? 646 skidBuffer[tid].size() : insts[tid].size(); 647 648 if (insts_available == 0) { 649 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 650 " early.\n",tid); 651 // Should I change the status to idle? 652 ++decodeIdleCycles; 653 return; 654 } else if (decodeStatus[tid] == Unblocking) { 655 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 656 "buffer.\n",tid); 657 ++decodeUnblockCycles; 658 } else if (decodeStatus[tid] == Running) { 659 ++decodeRunCycles; 660 } 661 662 DynInstPtr inst; 663 664 std::queue<DynInstPtr> 665 &insts_to_decode = decodeStatus[tid] == Unblocking ? 666 skidBuffer[tid] : insts[tid]; 667 668 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 669 670 while (insts_available > 0 && toRenameIndex < decodeWidth) { 671 assert(!insts_to_decode.empty()); 672 673 inst = insts_to_decode.front(); 674 675 insts_to_decode.pop(); 676 677 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 678 "PC %s\n", tid, inst->seqNum, inst->pcState()); 679 680 if (inst->isSquashed()) { 681 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 682 "squashed, skipping.\n", 683 tid, inst->seqNum, inst->pcState()); 684 685 ++decodeSquashedInsts; 686 687 --insts_available; 688 689 continue; 690 } 691 692 // Also check if instructions have no source registers. Mark 693 // them as ready to issue at any time. Not sure if this check 694 // should exist here or at a later stage; however it doesn't matter 695 // too much for function correctness. 696 if (inst->numSrcRegs() == 0) { 697 inst->setCanIssue(); 698 } 699 700 // This current instruction is valid, so add it into the decode 701 // queue. The next instruction may not be valid, so check to 702 // see if branches were predicted correctly. 703 toRename->insts[toRenameIndex] = inst; 704 705 ++(toRename->size); 706 ++toRenameIndex; 707 ++decodeDecodedInsts; 708 --insts_available; 709 710#if TRACING_ON 711 inst->decodeTick = curTick(); 712#endif 713 714 // Ensure that if it was predicted as a branch, it really is a 715 // branch. 716 if (inst->readPredTaken() && !inst->isControl()) { 717 panic("Instruction predicted as a branch!"); 718 719 ++decodeControlMispred; 720 721 // Might want to set some sort of boolean and just do 722 // a check at the end 723 squash(inst, inst->threadNumber); 724 725 break; 726 } 727 728 // Go ahead and compute any PC-relative branches. 729 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 730 ++decodeBranchResolved; 731 732 if (!(inst->branchTarget() == inst->readPredTarg())) { 733 ++decodeBranchMispred; 734 735 // Might want to set some sort of boolean and just do 736 // a check at the end 737 squash(inst, inst->threadNumber); 738 TheISA::PCState target = inst->branchTarget(); 739 740 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 741 inst->seqNum, target); 742 //The micro pc after an instruction level branch should be 0 743 inst->setPredTarg(target); 744 break; 745 } 746 } 747 } 748 749 // If we didn't process all instructions, then we will need to block 750 // and put all those instructions into the skid buffer. 751 if (!insts_to_decode.empty()) { 752 block(tid); 753 } 754 755 // Record that decode has written to the time buffer for activity 756 // tracking. 757 if (toRenameIndex) { 758 wroteToTimeBuffer = true; 759 } 760} 761