decode_impl.hh revision 4632:be5b8f67b8fb
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params) 35 : cpu(_cpu), 36 renameToDecodeDelay(params->renameToDecodeDelay), 37 iewToDecodeDelay(params->iewToDecodeDelay), 38 commitToDecodeDelay(params->commitToDecodeDelay), 39 fetchToDecodeDelay(params->fetchToDecodeDelay), 40 decodeWidth(params->decodeWidth), 41 numThreads(params->numberOfThreads) 42{ 43 _status = Inactive; 44 45 // Setup status, make sure stall signals are clear. 46 for (int i = 0; i < numThreads; ++i) { 47 decodeStatus[i] = Idle; 48 49 stalls[i].rename = false; 50 stalls[i].iew = false; 51 stalls[i].commit = false; 52 } 53 54 // @todo: Make into a parameter 55 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 56} 57 58template <class Impl> 59std::string 60DefaultDecode<Impl>::name() const 61{ 62 return cpu->name() + ".decode"; 63} 64 65template <class Impl> 66void 67DefaultDecode<Impl>::regStats() 68{ 69 decodeIdleCycles 70 .name(name() + ".DECODE:IdleCycles") 71 .desc("Number of cycles decode is idle") 72 .prereq(decodeIdleCycles); 73 decodeBlockedCycles 74 .name(name() + ".DECODE:BlockedCycles") 75 .desc("Number of cycles decode is blocked") 76 .prereq(decodeBlockedCycles); 77 decodeRunCycles 78 .name(name() + ".DECODE:RunCycles") 79 .desc("Number of cycles decode is running") 80 .prereq(decodeRunCycles); 81 decodeUnblockCycles 82 .name(name() + ".DECODE:UnblockCycles") 83 .desc("Number of cycles decode is unblocking") 84 .prereq(decodeUnblockCycles); 85 decodeSquashCycles 86 .name(name() + ".DECODE:SquashCycles") 87 .desc("Number of cycles decode is squashing") 88 .prereq(decodeSquashCycles); 89 decodeBranchResolved 90 .name(name() + ".DECODE:BranchResolved") 91 .desc("Number of times decode resolved a branch") 92 .prereq(decodeBranchResolved); 93 decodeBranchMispred 94 .name(name() + ".DECODE:BranchMispred") 95 .desc("Number of times decode detected a branch misprediction") 96 .prereq(decodeBranchMispred); 97 decodeControlMispred 98 .name(name() + ".DECODE:ControlMispred") 99 .desc("Number of times decode detected an instruction incorrectly" 100 " predicted as a control") 101 .prereq(decodeControlMispred); 102 decodeDecodedInsts 103 .name(name() + ".DECODE:DecodedInsts") 104 .desc("Number of instructions handled by decode") 105 .prereq(decodeDecodedInsts); 106 decodeSquashedInsts 107 .name(name() + ".DECODE:SquashedInsts") 108 .desc("Number of squashed instructions handled by decode") 109 .prereq(decodeSquashedInsts); 110} 111 112template<class Impl> 113void 114DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 115{ 116 timeBuffer = tb_ptr; 117 118 // Setup wire to write information back to fetch. 119 toFetch = timeBuffer->getWire(0); 120 121 // Create wires to get information from proper places in time buffer. 122 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 123 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 124 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 125} 126 127template<class Impl> 128void 129DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 130{ 131 decodeQueue = dq_ptr; 132 133 // Setup wire to write information to proper place in decode queue. 134 toRename = decodeQueue->getWire(0); 135} 136 137template<class Impl> 138void 139DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 140{ 141 fetchQueue = fq_ptr; 142 143 // Setup wire to read information from fetch queue. 144 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 145} 146 147template<class Impl> 148void 149DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 150{ 151 activeThreads = at_ptr; 152} 153 154template <class Impl> 155bool 156DefaultDecode<Impl>::drain() 157{ 158 // Decode is done draining at any time. 159 cpu->signalDrained(); 160 return true; 161} 162 163template <class Impl> 164void 165DefaultDecode<Impl>::takeOverFrom() 166{ 167 _status = Inactive; 168 169 // Be sure to reset state and clear out any old instructions. 170 for (int i = 0; i < numThreads; ++i) { 171 decodeStatus[i] = Idle; 172 173 stalls[i].rename = false; 174 stalls[i].iew = false; 175 stalls[i].commit = false; 176 while (!insts[i].empty()) 177 insts[i].pop(); 178 while (!skidBuffer[i].empty()) 179 skidBuffer[i].pop(); 180 branchCount[i] = 0; 181 } 182 wroteToTimeBuffer = false; 183} 184 185template<class Impl> 186bool 187DefaultDecode<Impl>::checkStall(unsigned tid) const 188{ 189 bool ret_val = false; 190 191 if (stalls[tid].rename) { 192 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 193 ret_val = true; 194 } else if (stalls[tid].iew) { 195 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 196 ret_val = true; 197 } else if (stalls[tid].commit) { 198 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 199 ret_val = true; 200 } 201 202 return ret_val; 203} 204 205template<class Impl> 206inline bool 207DefaultDecode<Impl>::fetchInstsValid() 208{ 209 return fromFetch->size > 0; 210} 211 212template<class Impl> 213bool 214DefaultDecode<Impl>::block(unsigned tid) 215{ 216 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 217 218 // Add the current inputs to the skid buffer so they can be 219 // reprocessed when this stage unblocks. 220 skidInsert(tid); 221 222 // If the decode status is blocked or unblocking then decode has not yet 223 // signalled fetch to unblock. In that case, there is no need to tell 224 // fetch to block. 225 if (decodeStatus[tid] != Blocked) { 226 // Set the status to Blocked. 227 decodeStatus[tid] = Blocked; 228 229 if (decodeStatus[tid] != Unblocking) { 230 toFetch->decodeBlock[tid] = true; 231 wroteToTimeBuffer = true; 232 } 233 234 return true; 235 } 236 237 return false; 238} 239 240template<class Impl> 241bool 242DefaultDecode<Impl>::unblock(unsigned tid) 243{ 244 // Decode is done unblocking only if the skid buffer is empty. 245 if (skidBuffer[tid].empty()) { 246 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 247 toFetch->decodeUnblock[tid] = true; 248 wroteToTimeBuffer = true; 249 250 decodeStatus[tid] = Running; 251 return true; 252 } 253 254 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 255 256 return false; 257} 258 259template<class Impl> 260void 261DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 262{ 263 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 264 "detected at decode.\n", tid); 265 266 // Send back mispredict information. 267 toFetch->decodeInfo[tid].branchMispredict = true; 268 toFetch->decodeInfo[tid].predIncorrect = true; 269 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 270 toFetch->decodeInfo[tid].squash = true; 271 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 272 ///FIXME There needs to be a way to set the nextPC and nextNPC 273 ///explicitly for ISAs with delay slots. 274 toFetch->decodeInfo[tid].nextNPC = 275 inst->branchTarget() + sizeof(TheISA::MachInst); 276#if ISA_HAS_DELAY_SLOT 277 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 278 (inst->readNextPC() + sizeof(TheISA::MachInst)); 279#else 280 toFetch->decodeInfo[tid].branchTaken = 281 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 282#endif 283 284 InstSeqNum squash_seq_num = inst->seqNum; 285 286 // Might have to tell fetch to unblock. 287 if (decodeStatus[tid] == Blocked || 288 decodeStatus[tid] == Unblocking) { 289 toFetch->decodeUnblock[tid] = 1; 290 } 291 292 // Set status to squashing. 293 decodeStatus[tid] = Squashing; 294 295 for (int i=0; i<fromFetch->size; i++) { 296 if (fromFetch->insts[i]->threadNumber == tid && 297 fromFetch->insts[i]->seqNum > squash_seq_num) { 298 fromFetch->insts[i]->setSquashed(); 299 } 300 } 301 302 // Clear the instruction list and skid buffer in case they have any 303 // insts in them. 304 while (!insts[tid].empty()) { 305 insts[tid].pop(); 306 } 307 308 while (!skidBuffer[tid].empty()) { 309 skidBuffer[tid].pop(); 310 } 311 312 // Squash instructions up until this one 313 cpu->removeInstsUntil(squash_seq_num, tid); 314} 315 316template<class Impl> 317unsigned 318DefaultDecode<Impl>::squash(unsigned tid) 319{ 320 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 321 322 if (decodeStatus[tid] == Blocked || 323 decodeStatus[tid] == Unblocking) { 324#if !FULL_SYSTEM 325 // In syscall emulation, we can have both a block and a squash due 326 // to a syscall in the same cycle. This would cause both signals to 327 // be high. This shouldn't happen in full system. 328 // @todo: Determine if this still happens. 329 if (toFetch->decodeBlock[tid]) { 330 toFetch->decodeBlock[tid] = 0; 331 } else { 332 toFetch->decodeUnblock[tid] = 1; 333 } 334#else 335 toFetch->decodeUnblock[tid] = 1; 336#endif 337 } 338 339 // Set status to squashing. 340 decodeStatus[tid] = Squashing; 341 342 // Go through incoming instructions from fetch and squash them. 343 unsigned squash_count = 0; 344 345 for (int i=0; i<fromFetch->size; i++) { 346 if (fromFetch->insts[i]->threadNumber == tid) { 347 fromFetch->insts[i]->setSquashed(); 348 squash_count++; 349 } 350 } 351 352 // Clear the instruction list and skid buffer in case they have any 353 // insts in them. 354 while (!insts[tid].empty()) { 355 insts[tid].pop(); 356 } 357 358 while (!skidBuffer[tid].empty()) { 359 skidBuffer[tid].pop(); 360 } 361 362 return squash_count; 363} 364 365template<class Impl> 366void 367DefaultDecode<Impl>::skidInsert(unsigned tid) 368{ 369 DynInstPtr inst = NULL; 370 371 while (!insts[tid].empty()) { 372 inst = insts[tid].front(); 373 374 insts[tid].pop(); 375 376 assert(tid == inst->threadNumber); 377 378 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 379 inst->seqNum, inst->readPC(), inst->threadNumber); 380 381 skidBuffer[tid].push(inst); 382 } 383 384 // @todo: Eventually need to enforce this by not letting a thread 385 // fetch past its skidbuffer 386 assert(skidBuffer[tid].size() <= skidBufferMax); 387} 388 389template<class Impl> 390bool 391DefaultDecode<Impl>::skidsEmpty() 392{ 393 std::list<unsigned>::iterator threads = activeThreads->begin(); 394 std::list<unsigned>::iterator end = activeThreads->end(); 395 396 while (threads != end) { 397 unsigned tid = *threads++; 398 if (!skidBuffer[tid].empty()) 399 return false; 400 } 401 402 return true; 403} 404 405template<class Impl> 406void 407DefaultDecode<Impl>::updateStatus() 408{ 409 bool any_unblocking = false; 410 411 std::list<unsigned>::iterator threads = activeThreads->begin(); 412 std::list<unsigned>::iterator end = activeThreads->end(); 413 414 while (threads != end) { 415 unsigned tid = *threads++; 416 417 if (decodeStatus[tid] == Unblocking) { 418 any_unblocking = true; 419 break; 420 } 421 } 422 423 // Decode will have activity if it's unblocking. 424 if (any_unblocking) { 425 if (_status == Inactive) { 426 _status = Active; 427 428 DPRINTF(Activity, "Activating stage.\n"); 429 430 cpu->activateStage(O3CPU::DecodeIdx); 431 } 432 } else { 433 // If it's not unblocking, then decode will not have any internal 434 // activity. Switch it to inactive. 435 if (_status == Active) { 436 _status = Inactive; 437 DPRINTF(Activity, "Deactivating stage.\n"); 438 439 cpu->deactivateStage(O3CPU::DecodeIdx); 440 } 441 } 442} 443 444template <class Impl> 445void 446DefaultDecode<Impl>::sortInsts() 447{ 448 int insts_from_fetch = fromFetch->size; 449#ifdef DEBUG 450 for (int i=0; i < numThreads; i++) 451 assert(insts[i].empty()); 452#endif 453 for (int i = 0; i < insts_from_fetch; ++i) { 454 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 455 } 456} 457 458template<class Impl> 459void 460DefaultDecode<Impl>::readStallSignals(unsigned tid) 461{ 462 if (fromRename->renameBlock[tid]) { 463 stalls[tid].rename = true; 464 } 465 466 if (fromRename->renameUnblock[tid]) { 467 assert(stalls[tid].rename); 468 stalls[tid].rename = false; 469 } 470 471 if (fromIEW->iewBlock[tid]) { 472 stalls[tid].iew = true; 473 } 474 475 if (fromIEW->iewUnblock[tid]) { 476 assert(stalls[tid].iew); 477 stalls[tid].iew = false; 478 } 479 480 if (fromCommit->commitBlock[tid]) { 481 stalls[tid].commit = true; 482 } 483 484 if (fromCommit->commitUnblock[tid]) { 485 assert(stalls[tid].commit); 486 stalls[tid].commit = false; 487 } 488} 489 490template <class Impl> 491bool 492DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 493{ 494 // Check if there's a squash signal, squash if there is. 495 // Check stall signals, block if necessary. 496 // If status was blocked 497 // Check if stall conditions have passed 498 // if so then go to unblocking 499 // If status was Squashing 500 // check if squashing is not high. Switch to running this cycle. 501 502 // Update the per thread stall statuses. 503 readStallSignals(tid); 504 505 // Check squash signals from commit. 506 if (fromCommit->commitInfo[tid].squash) { 507 508 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 509 "from commit.\n", tid); 510 511 squash(tid); 512 513 return true; 514 } 515 516 // Check ROB squash signals from commit. 517 if (fromCommit->commitInfo[tid].robSquashing) { 518 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 519 520 // Continue to squash. 521 decodeStatus[tid] = Squashing; 522 523 return true; 524 } 525 526 if (checkStall(tid)) { 527 return block(tid); 528 } 529 530 if (decodeStatus[tid] == Blocked) { 531 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 532 tid); 533 534 decodeStatus[tid] = Unblocking; 535 536 unblock(tid); 537 538 return true; 539 } 540 541 if (decodeStatus[tid] == Squashing) { 542 // Switch status to running if decode isn't being told to block or 543 // squash this cycle. 544 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 545 tid); 546 547 decodeStatus[tid] = Running; 548 549 return false; 550 } 551 552 // If we've reached this point, we have not gotten any signals that 553 // cause decode to change its status. Decode remains the same as before. 554 return false; 555} 556 557template<class Impl> 558void 559DefaultDecode<Impl>::tick() 560{ 561 wroteToTimeBuffer = false; 562 563 bool status_change = false; 564 565 toRenameIndex = 0; 566 567 std::list<unsigned>::iterator threads = activeThreads->begin(); 568 std::list<unsigned>::iterator end = activeThreads->end(); 569 570 sortInsts(); 571 572 //Check stall and squash signals. 573 while (threads != end) { 574 unsigned tid = *threads++; 575 576 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 577 status_change = checkSignalsAndUpdate(tid) || status_change; 578 579 decode(status_change, tid); 580 } 581 582 if (status_change) { 583 updateStatus(); 584 } 585 586 if (wroteToTimeBuffer) { 587 DPRINTF(Activity, "Activity this cycle.\n"); 588 589 cpu->activityThisCycle(); 590 } 591} 592 593template<class Impl> 594void 595DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 596{ 597 // If status is Running or idle, 598 // call decodeInsts() 599 // If status is Unblocking, 600 // buffer any instructions coming from fetch 601 // continue trying to empty skid buffer 602 // check if stall conditions have passed 603 604 if (decodeStatus[tid] == Blocked) { 605 ++decodeBlockedCycles; 606 } else if (decodeStatus[tid] == Squashing) { 607 ++decodeSquashCycles; 608 } 609 610 // Decode should try to decode as many instructions as its bandwidth 611 // will allow, as long as it is not currently blocked. 612 if (decodeStatus[tid] == Running || 613 decodeStatus[tid] == Idle) { 614 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 615 "stage.\n",tid); 616 617 decodeInsts(tid); 618 } else if (decodeStatus[tid] == Unblocking) { 619 // Make sure that the skid buffer has something in it if the 620 // status is unblocking. 621 assert(!skidsEmpty()); 622 623 // If the status was unblocking, then instructions from the skid 624 // buffer were used. Remove those instructions and handle 625 // the rest of unblocking. 626 decodeInsts(tid); 627 628 if (fetchInstsValid()) { 629 // Add the current inputs to the skid buffer so they can be 630 // reprocessed when this stage unblocks. 631 skidInsert(tid); 632 } 633 634 status_change = unblock(tid) || status_change; 635 } 636} 637 638template <class Impl> 639void 640DefaultDecode<Impl>::decodeInsts(unsigned tid) 641{ 642 // Instructions can come either from the skid buffer or the list of 643 // instructions coming from fetch, depending on decode's status. 644 int insts_available = decodeStatus[tid] == Unblocking ? 645 skidBuffer[tid].size() : insts[tid].size(); 646 647 if (insts_available == 0) { 648 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 649 " early.\n",tid); 650 // Should I change the status to idle? 651 ++decodeIdleCycles; 652 return; 653 } else if (decodeStatus[tid] == Unblocking) { 654 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 655 "buffer.\n",tid); 656 ++decodeUnblockCycles; 657 } else if (decodeStatus[tid] == Running) { 658 ++decodeRunCycles; 659 } 660 661 DynInstPtr inst; 662 663 std::queue<DynInstPtr> 664 &insts_to_decode = decodeStatus[tid] == Unblocking ? 665 skidBuffer[tid] : insts[tid]; 666 667 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 668 669 while (insts_available > 0 && toRenameIndex < decodeWidth) { 670 assert(!insts_to_decode.empty()); 671 672 inst = insts_to_decode.front(); 673 674 insts_to_decode.pop(); 675 676 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 677 "PC %#x\n", 678 tid, inst->seqNum, inst->readPC()); 679 680 if (inst->isSquashed()) { 681 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 682 "squashed, skipping.\n", 683 tid, inst->seqNum, inst->readPC()); 684 685 ++decodeSquashedInsts; 686 687 --insts_available; 688 689 continue; 690 } 691 692 // Also check if instructions have no source registers. Mark 693 // them as ready to issue at any time. Not sure if this check 694 // should exist here or at a later stage; however it doesn't matter 695 // too much for function correctness. 696 if (inst->numSrcRegs() == 0) { 697 inst->setCanIssue(); 698 } 699 700 // This current instruction is valid, so add it into the decode 701 // queue. The next instruction may not be valid, so check to 702 // see if branches were predicted correctly. 703 toRename->insts[toRenameIndex] = inst; 704 705 ++(toRename->size); 706 ++toRenameIndex; 707 ++decodeDecodedInsts; 708 --insts_available; 709 710 // Ensure that if it was predicted as a branch, it really is a 711 // branch. 712 if (inst->readPredTaken() && !inst->isControl()) { 713 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 714 inst->readPredPC(), inst->readNextPC() + 4); 715 716 panic("Instruction predicted as a branch!"); 717 718 ++decodeControlMispred; 719 720 // Might want to set some sort of boolean and just do 721 // a check at the end 722 squash(inst, inst->threadNumber); 723 724 break; 725 } 726 727 // Go ahead and compute any PC-relative branches. 728 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 729 ++decodeBranchResolved; 730 731 if (inst->branchTarget() != inst->readPredPC()) { 732 ++decodeBranchMispred; 733 734 // Might want to set some sort of boolean and just do 735 // a check at the end 736 squash(inst, inst->threadNumber); 737 Addr target = inst->branchTarget(); 738 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 739 break; 740 } 741 } 742 } 743 744 // If we didn't process all instructions, then we will need to block 745 // and put all those instructions into the skid buffer. 746 if (!insts_to_decode.empty()) { 747 block(tid); 748 } 749 750 // Record that decode has written to the time buffer for activity 751 // tracking. 752 if (toRenameIndex) { 753 wroteToTimeBuffer = true; 754 } 755} 756