decode_impl.hh revision 4329:52057dbec096
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params) 35 : cpu(_cpu), 36 renameToDecodeDelay(params->renameToDecodeDelay), 37 iewToDecodeDelay(params->iewToDecodeDelay), 38 commitToDecodeDelay(params->commitToDecodeDelay), 39 fetchToDecodeDelay(params->fetchToDecodeDelay), 40 decodeWidth(params->decodeWidth), 41 numThreads(params->numberOfThreads) 42{ 43 _status = Inactive; 44 45 // Setup status, make sure stall signals are clear. 46 for (int i = 0; i < numThreads; ++i) { 47 decodeStatus[i] = Idle; 48 49 stalls[i].rename = false; 50 stalls[i].iew = false; 51 stalls[i].commit = false; 52 53 squashAfterDelaySlot[i] = false; 54 } 55 56 // @todo: Make into a parameter 57 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 58} 59 60template <class Impl> 61std::string 62DefaultDecode<Impl>::name() const 63{ 64 return cpu->name() + ".decode"; 65} 66 67template <class Impl> 68void 69DefaultDecode<Impl>::regStats() 70{ 71 decodeIdleCycles 72 .name(name() + ".DECODE:IdleCycles") 73 .desc("Number of cycles decode is idle") 74 .prereq(decodeIdleCycles); 75 decodeBlockedCycles 76 .name(name() + ".DECODE:BlockedCycles") 77 .desc("Number of cycles decode is blocked") 78 .prereq(decodeBlockedCycles); 79 decodeRunCycles 80 .name(name() + ".DECODE:RunCycles") 81 .desc("Number of cycles decode is running") 82 .prereq(decodeRunCycles); 83 decodeUnblockCycles 84 .name(name() + ".DECODE:UnblockCycles") 85 .desc("Number of cycles decode is unblocking") 86 .prereq(decodeUnblockCycles); 87 decodeSquashCycles 88 .name(name() + ".DECODE:SquashCycles") 89 .desc("Number of cycles decode is squashing") 90 .prereq(decodeSquashCycles); 91 decodeBranchResolved 92 .name(name() + ".DECODE:BranchResolved") 93 .desc("Number of times decode resolved a branch") 94 .prereq(decodeBranchResolved); 95 decodeBranchMispred 96 .name(name() + ".DECODE:BranchMispred") 97 .desc("Number of times decode detected a branch misprediction") 98 .prereq(decodeBranchMispred); 99 decodeControlMispred 100 .name(name() + ".DECODE:ControlMispred") 101 .desc("Number of times decode detected an instruction incorrectly" 102 " predicted as a control") 103 .prereq(decodeControlMispred); 104 decodeDecodedInsts 105 .name(name() + ".DECODE:DecodedInsts") 106 .desc("Number of instructions handled by decode") 107 .prereq(decodeDecodedInsts); 108 decodeSquashedInsts 109 .name(name() + ".DECODE:SquashedInsts") 110 .desc("Number of squashed instructions handled by decode") 111 .prereq(decodeSquashedInsts); 112} 113 114template<class Impl> 115void 116DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 117{ 118 timeBuffer = tb_ptr; 119 120 // Setup wire to write information back to fetch. 121 toFetch = timeBuffer->getWire(0); 122 123 // Create wires to get information from proper places in time buffer. 124 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 125 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 126 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 127} 128 129template<class Impl> 130void 131DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 132{ 133 decodeQueue = dq_ptr; 134 135 // Setup wire to write information to proper place in decode queue. 136 toRename = decodeQueue->getWire(0); 137} 138 139template<class Impl> 140void 141DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 142{ 143 fetchQueue = fq_ptr; 144 145 // Setup wire to read information from fetch queue. 146 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 147} 148 149template<class Impl> 150void 151DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 152{ 153 activeThreads = at_ptr; 154} 155 156template <class Impl> 157bool 158DefaultDecode<Impl>::drain() 159{ 160 // Decode is done draining at any time. 161 cpu->signalDrained(); 162 return true; 163} 164 165template <class Impl> 166void 167DefaultDecode<Impl>::takeOverFrom() 168{ 169 _status = Inactive; 170 171 // Be sure to reset state and clear out any old instructions. 172 for (int i = 0; i < numThreads; ++i) { 173 decodeStatus[i] = Idle; 174 175 stalls[i].rename = false; 176 stalls[i].iew = false; 177 stalls[i].commit = false; 178 while (!insts[i].empty()) 179 insts[i].pop(); 180 while (!skidBuffer[i].empty()) 181 skidBuffer[i].pop(); 182 branchCount[i] = 0; 183 } 184 wroteToTimeBuffer = false; 185} 186 187template<class Impl> 188bool 189DefaultDecode<Impl>::checkStall(unsigned tid) const 190{ 191 bool ret_val = false; 192 193 if (stalls[tid].rename) { 194 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 195 ret_val = true; 196 } else if (stalls[tid].iew) { 197 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 198 ret_val = true; 199 } else if (stalls[tid].commit) { 200 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 201 ret_val = true; 202 } 203 204 return ret_val; 205} 206 207template<class Impl> 208inline bool 209DefaultDecode<Impl>::fetchInstsValid() 210{ 211 return fromFetch->size > 0; 212} 213 214template<class Impl> 215bool 216DefaultDecode<Impl>::block(unsigned tid) 217{ 218 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 219 220 // Add the current inputs to the skid buffer so they can be 221 // reprocessed when this stage unblocks. 222 skidInsert(tid); 223 224 // If the decode status is blocked or unblocking then decode has not yet 225 // signalled fetch to unblock. In that case, there is no need to tell 226 // fetch to block. 227 if (decodeStatus[tid] != Blocked) { 228 // Set the status to Blocked. 229 decodeStatus[tid] = Blocked; 230 231 if (decodeStatus[tid] != Unblocking) { 232 toFetch->decodeBlock[tid] = true; 233 wroteToTimeBuffer = true; 234 } 235 236 return true; 237 } 238 239 return false; 240} 241 242template<class Impl> 243bool 244DefaultDecode<Impl>::unblock(unsigned tid) 245{ 246 // Decode is done unblocking only if the skid buffer is empty. 247 if (skidBuffer[tid].empty()) { 248 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 249 toFetch->decodeUnblock[tid] = true; 250 wroteToTimeBuffer = true; 251 252 decodeStatus[tid] = Running; 253 return true; 254 } 255 256 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 257 258 return false; 259} 260 261template<class Impl> 262void 263DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 264{ 265 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 266 "detected at decode.\n", tid); 267 268 // Send back mispredict information. 269 toFetch->decodeInfo[tid].branchMispredict = true; 270 toFetch->decodeInfo[tid].predIncorrect = true; 271 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 272 toFetch->decodeInfo[tid].squash = true; 273 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 274 ///FIXME There needs to be a way to set the nextPC and nextNPC 275 ///explicitly for ISAs with delay slots. 276 toFetch->decodeInfo[tid].nextNPC = 277 inst->branchTarget() + sizeof(TheISA::MachInst); 278#if ISA_HAS_DELAY_SLOT 279 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 280 (inst->readNextPC() + sizeof(TheISA::MachInst)); 281 282 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 283 squashAfterDelaySlot[tid] = false; 284 285 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 286#else 287 toFetch->decodeInfo[tid].branchTaken = 288 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 289 290 InstSeqNum squash_seq_num = inst->seqNum; 291#endif 292 293 // Might have to tell fetch to unblock. 294 if (decodeStatus[tid] == Blocked || 295 decodeStatus[tid] == Unblocking) { 296 toFetch->decodeUnblock[tid] = 1; 297 } 298 299 // Set status to squashing. 300 decodeStatus[tid] = Squashing; 301 302 for (int i=0; i<fromFetch->size; i++) { 303 if (fromFetch->insts[i]->threadNumber == tid && 304 fromFetch->insts[i]->seqNum > squash_seq_num) { 305 fromFetch->insts[i]->setSquashed(); 306 } 307 } 308 309 // Clear the instruction list and skid buffer in case they have any 310 // insts in them. 311 while (!insts[tid].empty()) { 312 313#if ISA_HAS_DELAY_SLOT 314 if (insts[tid].front()->seqNum <= squash_seq_num) { 315 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 316 "instructions before delay slot [sn:%i]. %i insts" 317 "left in decode.\n", tid, squash_seq_num, 318 insts[tid].size()); 319 break; 320 } 321#endif 322 insts[tid].pop(); 323 } 324 325 while (!skidBuffer[tid].empty()) { 326 327#if ISA_HAS_DELAY_SLOT 328 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 329 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 330 "instructions before delay slot [sn:%i]. %i insts" 331 "left in decode.\n", tid, squash_seq_num, 332 insts[tid].size()); 333 break; 334 } 335#endif 336 skidBuffer[tid].pop(); 337 } 338 339 // Squash instructions up until this one 340 cpu->removeInstsUntil(squash_seq_num, tid); 341} 342 343template<class Impl> 344unsigned 345DefaultDecode<Impl>::squash(unsigned tid) 346{ 347 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 348 349 if (decodeStatus[tid] == Blocked || 350 decodeStatus[tid] == Unblocking) { 351#if !FULL_SYSTEM 352 // In syscall emulation, we can have both a block and a squash due 353 // to a syscall in the same cycle. This would cause both signals to 354 // be high. This shouldn't happen in full system. 355 // @todo: Determine if this still happens. 356 if (toFetch->decodeBlock[tid]) { 357 toFetch->decodeBlock[tid] = 0; 358 } else { 359 toFetch->decodeUnblock[tid] = 1; 360 } 361#else 362 toFetch->decodeUnblock[tid] = 1; 363#endif 364 } 365 366 // Set status to squashing. 367 decodeStatus[tid] = Squashing; 368 369 // Go through incoming instructions from fetch and squash them. 370 unsigned squash_count = 0; 371 372 for (int i=0; i<fromFetch->size; i++) { 373 if (fromFetch->insts[i]->threadNumber == tid) { 374 fromFetch->insts[i]->setSquashed(); 375 squash_count++; 376 } 377 } 378 379 // Clear the instruction list and skid buffer in case they have any 380 // insts in them. 381 while (!insts[tid].empty()) { 382 insts[tid].pop(); 383 } 384 385 while (!skidBuffer[tid].empty()) { 386 skidBuffer[tid].pop(); 387 } 388 389 return squash_count; 390} 391 392template<class Impl> 393void 394DefaultDecode<Impl>::skidInsert(unsigned tid) 395{ 396 DynInstPtr inst = NULL; 397 398 while (!insts[tid].empty()) { 399 inst = insts[tid].front(); 400 401 insts[tid].pop(); 402 403 assert(tid == inst->threadNumber); 404 405 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 406 inst->seqNum, inst->readPC(), inst->threadNumber); 407 408 skidBuffer[tid].push(inst); 409 } 410 411 // @todo: Eventually need to enforce this by not letting a thread 412 // fetch past its skidbuffer 413 assert(skidBuffer[tid].size() <= skidBufferMax); 414} 415 416template<class Impl> 417bool 418DefaultDecode<Impl>::skidsEmpty() 419{ 420 std::list<unsigned>::iterator threads = activeThreads->begin(); 421 std::list<unsigned>::iterator end = activeThreads->end(); 422 423 while (threads != end) { 424 unsigned tid = *threads++; 425 if (!skidBuffer[tid].empty()) 426 return false; 427 } 428 429 return true; 430} 431 432template<class Impl> 433void 434DefaultDecode<Impl>::updateStatus() 435{ 436 bool any_unblocking = false; 437 438 std::list<unsigned>::iterator threads = activeThreads->begin(); 439 std::list<unsigned>::iterator end = activeThreads->end(); 440 441 while (threads != end) { 442 unsigned tid = *threads++; 443 444 if (decodeStatus[tid] == Unblocking) { 445 any_unblocking = true; 446 break; 447 } 448 } 449 450 // Decode will have activity if it's unblocking. 451 if (any_unblocking) { 452 if (_status == Inactive) { 453 _status = Active; 454 455 DPRINTF(Activity, "Activating stage.\n"); 456 457 cpu->activateStage(O3CPU::DecodeIdx); 458 } 459 } else { 460 // If it's not unblocking, then decode will not have any internal 461 // activity. Switch it to inactive. 462 if (_status == Active) { 463 _status = Inactive; 464 DPRINTF(Activity, "Deactivating stage.\n"); 465 466 cpu->deactivateStage(O3CPU::DecodeIdx); 467 } 468 } 469} 470 471template <class Impl> 472void 473DefaultDecode<Impl>::sortInsts() 474{ 475 int insts_from_fetch = fromFetch->size; 476#ifdef DEBUG 477 for (int i=0; i < numThreads; i++) 478 assert(insts[i].empty()); 479#endif 480 for (int i = 0; i < insts_from_fetch; ++i) { 481 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 482 } 483} 484 485template<class Impl> 486void 487DefaultDecode<Impl>::readStallSignals(unsigned tid) 488{ 489 if (fromRename->renameBlock[tid]) { 490 stalls[tid].rename = true; 491 } 492 493 if (fromRename->renameUnblock[tid]) { 494 assert(stalls[tid].rename); 495 stalls[tid].rename = false; 496 } 497 498 if (fromIEW->iewBlock[tid]) { 499 stalls[tid].iew = true; 500 } 501 502 if (fromIEW->iewUnblock[tid]) { 503 assert(stalls[tid].iew); 504 stalls[tid].iew = false; 505 } 506 507 if (fromCommit->commitBlock[tid]) { 508 stalls[tid].commit = true; 509 } 510 511 if (fromCommit->commitUnblock[tid]) { 512 assert(stalls[tid].commit); 513 stalls[tid].commit = false; 514 } 515} 516 517template <class Impl> 518bool 519DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 520{ 521 // Check if there's a squash signal, squash if there is. 522 // Check stall signals, block if necessary. 523 // If status was blocked 524 // Check if stall conditions have passed 525 // if so then go to unblocking 526 // If status was Squashing 527 // check if squashing is not high. Switch to running this cycle. 528 529 // Update the per thread stall statuses. 530 readStallSignals(tid); 531 532 // Check squash signals from commit. 533 if (fromCommit->commitInfo[tid].squash) { 534 535 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 536 "from commit.\n", tid); 537 538 squash(tid); 539 540 return true; 541 } 542 543 // Check ROB squash signals from commit. 544 if (fromCommit->commitInfo[tid].robSquashing) { 545 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 546 547 // Continue to squash. 548 decodeStatus[tid] = Squashing; 549 550 return true; 551 } 552 553 if (checkStall(tid)) { 554 return block(tid); 555 } 556 557 if (decodeStatus[tid] == Blocked) { 558 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 559 tid); 560 561 decodeStatus[tid] = Unblocking; 562 563 unblock(tid); 564 565 return true; 566 } 567 568 if (decodeStatus[tid] == Squashing) { 569 // Switch status to running if decode isn't being told to block or 570 // squash this cycle. 571 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 572 tid); 573 574 decodeStatus[tid] = Running; 575 576 return false; 577 } 578 579 // If we've reached this point, we have not gotten any signals that 580 // cause decode to change its status. Decode remains the same as before. 581 return false; 582} 583 584template<class Impl> 585void 586DefaultDecode<Impl>::tick() 587{ 588 wroteToTimeBuffer = false; 589 590 bool status_change = false; 591 592 toRenameIndex = 0; 593 594 std::list<unsigned>::iterator threads = activeThreads->begin(); 595 std::list<unsigned>::iterator end = activeThreads->end(); 596 597 sortInsts(); 598 599 //Check stall and squash signals. 600 while (threads != end) { 601 unsigned tid = *threads++; 602 603 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 604 status_change = checkSignalsAndUpdate(tid) || status_change; 605 606 decode(status_change, tid); 607 } 608 609 if (status_change) { 610 updateStatus(); 611 } 612 613 if (wroteToTimeBuffer) { 614 DPRINTF(Activity, "Activity this cycle.\n"); 615 616 cpu->activityThisCycle(); 617 } 618} 619 620template<class Impl> 621void 622DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 623{ 624 // If status is Running or idle, 625 // call decodeInsts() 626 // If status is Unblocking, 627 // buffer any instructions coming from fetch 628 // continue trying to empty skid buffer 629 // check if stall conditions have passed 630 631 if (decodeStatus[tid] == Blocked) { 632 ++decodeBlockedCycles; 633 } else if (decodeStatus[tid] == Squashing) { 634 ++decodeSquashCycles; 635 } 636 637 // Decode should try to decode as many instructions as its bandwidth 638 // will allow, as long as it is not currently blocked. 639 if (decodeStatus[tid] == Running || 640 decodeStatus[tid] == Idle) { 641 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 642 "stage.\n",tid); 643 644 decodeInsts(tid); 645 } else if (decodeStatus[tid] == Unblocking) { 646 // Make sure that the skid buffer has something in it if the 647 // status is unblocking. 648 assert(!skidsEmpty()); 649 650 // If the status was unblocking, then instructions from the skid 651 // buffer were used. Remove those instructions and handle 652 // the rest of unblocking. 653 decodeInsts(tid); 654 655 if (fetchInstsValid()) { 656 // Add the current inputs to the skid buffer so they can be 657 // reprocessed when this stage unblocks. 658 skidInsert(tid); 659 } 660 661 status_change = unblock(tid) || status_change; 662 } 663} 664 665template <class Impl> 666void 667DefaultDecode<Impl>::decodeInsts(unsigned tid) 668{ 669 // Instructions can come either from the skid buffer or the list of 670 // instructions coming from fetch, depending on decode's status. 671 int insts_available = decodeStatus[tid] == Unblocking ? 672 skidBuffer[tid].size() : insts[tid].size(); 673 674 if (insts_available == 0) { 675 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 676 " early.\n",tid); 677 // Should I change the status to idle? 678 ++decodeIdleCycles; 679 return; 680 } else if (decodeStatus[tid] == Unblocking) { 681 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 682 "buffer.\n",tid); 683 ++decodeUnblockCycles; 684 } else if (decodeStatus[tid] == Running) { 685 ++decodeRunCycles; 686 } 687 688 DynInstPtr inst; 689 690 std::queue<DynInstPtr> 691 &insts_to_decode = decodeStatus[tid] == Unblocking ? 692 skidBuffer[tid] : insts[tid]; 693 694 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 695 696 while (insts_available > 0 && toRenameIndex < decodeWidth) { 697 assert(!insts_to_decode.empty()); 698 699 inst = insts_to_decode.front(); 700 701 insts_to_decode.pop(); 702 703 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 704 "PC %#x\n", 705 tid, inst->seqNum, inst->readPC()); 706 707 if (inst->isSquashed()) { 708 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 709 "squashed, skipping.\n", 710 tid, inst->seqNum, inst->readPC()); 711 712 ++decodeSquashedInsts; 713 714 --insts_available; 715 716 continue; 717 } 718 719 // Also check if instructions have no source registers. Mark 720 // them as ready to issue at any time. Not sure if this check 721 // should exist here or at a later stage; however it doesn't matter 722 // too much for function correctness. 723 if (inst->numSrcRegs() == 0) { 724 inst->setCanIssue(); 725 } 726 727 // This current instruction is valid, so add it into the decode 728 // queue. The next instruction may not be valid, so check to 729 // see if branches were predicted correctly. 730 toRename->insts[toRenameIndex] = inst; 731 732 ++(toRename->size); 733 ++toRenameIndex; 734 ++decodeDecodedInsts; 735 --insts_available; 736 737 // Ensure that if it was predicted as a branch, it really is a 738 // branch. 739 if (inst->readPredTaken() && !inst->isControl()) { 740 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 741 inst->readPredPC(), inst->readNextPC() + 4); 742 743 panic("Instruction predicted as a branch!"); 744 745 ++decodeControlMispred; 746 747 // Might want to set some sort of boolean and just do 748 // a check at the end 749 squash(inst, inst->threadNumber); 750 751 break; 752 } 753 754 // Go ahead and compute any PC-relative branches. 755 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 756 ++decodeBranchResolved; 757 758 if (inst->branchTarget() != inst->readPredPC()) { 759 ++decodeBranchMispred; 760 761 // Might want to set some sort of boolean and just do 762 // a check at the end 763#if !ISA_HAS_DELAY_SLOT 764 squash(inst, inst->threadNumber); 765 Addr target = inst->branchTarget(); 766 inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 767 break; 768#else 769 // If mispredicted as taken, then ignore delay slot 770 // instruction... else keep delay slot and squash 771 // after it is sent to rename 772 if (inst->readPredTaken() && inst->isCondDelaySlot()) { 773 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 774 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 775 inst->seqNum, inst->PC); 776 bdelayDoneSeqNum[tid] = inst->seqNum; 777 squash(inst, inst->threadNumber); 778 Addr target = inst->branchTarget(); 779 inst->setPredTarg(target, 780 target + sizeof(TheISA::MachInst)); 781 break; 782 } else { 783 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 784 "[sn:%i] PC %#x, will squash after delay slot " 785 "inst. is sent to Rename\n", 786 tid, inst->seqNum, inst->PC); 787 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 788 squashAfterDelaySlot[tid] = true; 789 squashInst[tid] = inst; 790 continue; 791 } 792#endif 793 } 794 } 795 796 if (squashAfterDelaySlot[tid]) { 797 assert(!inst->isSquashed()); 798 squash(squashInst[tid], squashInst[tid]->threadNumber); 799 Addr target = squashInst[tid]->branchTarget(); 800 squashInst[tid]->setPredTarg(target, 801 target + sizeof(TheISA::MachInst)); 802 assert(!inst->isSquashed()); 803 break; 804 } 805 } 806 807 // If we didn't process all instructions, then we will need to block 808 // and put all those instructions into the skid buffer. 809 if (!insts_to_decode.empty()) { 810 block(tid); 811 } 812 813 // Record that decode has written to the time buffer for activity 814 // tracking. 815 if (toRenameIndex) { 816 wroteToTimeBuffer = true; 817 } 818} 819