decode_impl.hh revision 2935:d1223a6c9156
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33using namespace std; 34 35template<class Impl> 36DefaultDecode<Impl>::DefaultDecode(Params *params) 37 : renameToDecodeDelay(params->renameToDecodeDelay), 38 iewToDecodeDelay(params->iewToDecodeDelay), 39 commitToDecodeDelay(params->commitToDecodeDelay), 40 fetchToDecodeDelay(params->fetchToDecodeDelay), 41 decodeWidth(params->decodeWidth), 42 numThreads(params->numberOfThreads) 43{ 44 _status = Inactive; 45 46 // Setup status, make sure stall signals are clear. 47 for (int i = 0; i < numThreads; ++i) { 48 decodeStatus[i] = Idle; 49 50 stalls[i].rename = false; 51 stalls[i].iew = false; 52 stalls[i].commit = false; 53 54 squashAfterDelaySlot[i] = false; 55 } 56 57 // @todo: Make into a parameter 58 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 59} 60 61template <class Impl> 62std::string 63DefaultDecode<Impl>::name() const 64{ 65 return cpu->name() + ".decode"; 66} 67 68template <class Impl> 69void 70DefaultDecode<Impl>::regStats() 71{ 72 decodeIdleCycles 73 .name(name() + ".DECODE:IdleCycles") 74 .desc("Number of cycles decode is idle") 75 .prereq(decodeIdleCycles); 76 decodeBlockedCycles 77 .name(name() + ".DECODE:BlockedCycles") 78 .desc("Number of cycles decode is blocked") 79 .prereq(decodeBlockedCycles); 80 decodeRunCycles 81 .name(name() + ".DECODE:RunCycles") 82 .desc("Number of cycles decode is running") 83 .prereq(decodeRunCycles); 84 decodeUnblockCycles 85 .name(name() + ".DECODE:UnblockCycles") 86 .desc("Number of cycles decode is unblocking") 87 .prereq(decodeUnblockCycles); 88 decodeSquashCycles 89 .name(name() + ".DECODE:SquashCycles") 90 .desc("Number of cycles decode is squashing") 91 .prereq(decodeSquashCycles); 92 decodeBranchResolved 93 .name(name() + ".DECODE:BranchResolved") 94 .desc("Number of times decode resolved a branch") 95 .prereq(decodeBranchResolved); 96 decodeBranchMispred 97 .name(name() + ".DECODE:BranchMispred") 98 .desc("Number of times decode detected a branch misprediction") 99 .prereq(decodeBranchMispred); 100 decodeControlMispred 101 .name(name() + ".DECODE:ControlMispred") 102 .desc("Number of times decode detected an instruction incorrectly" 103 " predicted as a control") 104 .prereq(decodeControlMispred); 105 decodeDecodedInsts 106 .name(name() + ".DECODE:DecodedInsts") 107 .desc("Number of instructions handled by decode") 108 .prereq(decodeDecodedInsts); 109 decodeSquashedInsts 110 .name(name() + ".DECODE:SquashedInsts") 111 .desc("Number of squashed instructions handled by decode") 112 .prereq(decodeSquashedInsts); 113} 114 115template<class Impl> 116void 117DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 118{ 119 DPRINTF(Decode, "Setting CPU pointer.\n"); 120 cpu = cpu_ptr; 121} 122 123template<class Impl> 124void 125DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 126{ 127 DPRINTF(Decode, "Setting time buffer pointer.\n"); 128 timeBuffer = tb_ptr; 129 130 // Setup wire to write information back to fetch. 131 toFetch = timeBuffer->getWire(0); 132 133 // Create wires to get information from proper places in time buffer. 134 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 135 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 136 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 137} 138 139template<class Impl> 140void 141DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 142{ 143 DPRINTF(Decode, "Setting decode queue pointer.\n"); 144 decodeQueue = dq_ptr; 145 146 // Setup wire to write information to proper place in decode queue. 147 toRename = decodeQueue->getWire(0); 148} 149 150template<class Impl> 151void 152DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 153{ 154 DPRINTF(Decode, "Setting fetch queue pointer.\n"); 155 fetchQueue = fq_ptr; 156 157 // Setup wire to read information from fetch queue. 158 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 159} 160 161template<class Impl> 162void 163DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) 164{ 165 DPRINTF(Decode, "Setting active threads list pointer.\n"); 166 activeThreads = at_ptr; 167} 168 169template <class Impl> 170bool 171DefaultDecode<Impl>::drain() 172{ 173 // Decode is done draining at any time. 174 cpu->signalDrained(); 175 return true; 176} 177 178template <class Impl> 179void 180DefaultDecode<Impl>::takeOverFrom() 181{ 182 _status = Inactive; 183 184 // Be sure to reset state and clear out any old instructions. 185 for (int i = 0; i < numThreads; ++i) { 186 decodeStatus[i] = Idle; 187 188 stalls[i].rename = false; 189 stalls[i].iew = false; 190 stalls[i].commit = false; 191 while (!insts[i].empty()) 192 insts[i].pop(); 193 while (!skidBuffer[i].empty()) 194 skidBuffer[i].pop(); 195 branchCount[i] = 0; 196 } 197 wroteToTimeBuffer = false; 198} 199 200template<class Impl> 201bool 202DefaultDecode<Impl>::checkStall(unsigned tid) const 203{ 204 bool ret_val = false; 205 206 if (stalls[tid].rename) { 207 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 208 ret_val = true; 209 } else if (stalls[tid].iew) { 210 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 211 ret_val = true; 212 } else if (stalls[tid].commit) { 213 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 214 ret_val = true; 215 } 216 217 return ret_val; 218} 219 220template<class Impl> 221inline bool 222DefaultDecode<Impl>::fetchInstsValid() 223{ 224 return fromFetch->size > 0; 225} 226 227template<class Impl> 228bool 229DefaultDecode<Impl>::block(unsigned tid) 230{ 231 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 232 233 // Add the current inputs to the skid buffer so they can be 234 // reprocessed when this stage unblocks. 235 skidInsert(tid); 236 237 // If the decode status is blocked or unblocking then decode has not yet 238 // signalled fetch to unblock. In that case, there is no need to tell 239 // fetch to block. 240 if (decodeStatus[tid] != Blocked) { 241 // Set the status to Blocked. 242 decodeStatus[tid] = Blocked; 243 244 if (decodeStatus[tid] != Unblocking) { 245 toFetch->decodeBlock[tid] = true; 246 wroteToTimeBuffer = true; 247 } 248 249 return true; 250 } 251 252 return false; 253} 254 255template<class Impl> 256bool 257DefaultDecode<Impl>::unblock(unsigned tid) 258{ 259 // Decode is done unblocking only if the skid buffer is empty. 260 if (skidBuffer[tid].empty()) { 261 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 262 toFetch->decodeUnblock[tid] = true; 263 wroteToTimeBuffer = true; 264 265 decodeStatus[tid] = Running; 266 return true; 267 } 268 269 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 270 271 return false; 272} 273 274template<class Impl> 275void 276DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 277{ 278 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 279 "detected at decode.\n", tid); 280 281 // Send back mispredict information. 282 toFetch->decodeInfo[tid].branchMispredict = true; 283 toFetch->decodeInfo[tid].predIncorrect = true; 284 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 285 toFetch->decodeInfo[tid].squash = true; 286 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 287#if THE_ISA == ALPHA_ISA 288 toFetch->decodeInfo[tid].branchTaken = 289 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 290 291 InstSeqNum squash_seq_num = inst->seqNum; 292#else 293 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 294 (inst->readNextPC() + sizeof(TheISA::MachInst)); 295 296 toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 297 squashAfterDelaySlot[tid] = false; 298 299 InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 300#endif 301 302 // Might have to tell fetch to unblock. 303 if (decodeStatus[tid] == Blocked || 304 decodeStatus[tid] == Unblocking) { 305 toFetch->decodeUnblock[tid] = 1; 306 } 307 308 // Set status to squashing. 309 decodeStatus[tid] = Squashing; 310 311 for (int i=0; i<fromFetch->size; i++) { 312 if (fromFetch->insts[i]->threadNumber == tid && 313 fromFetch->insts[i]->seqNum > squash_seq_num) { 314 fromFetch->insts[i]->setSquashed(); 315 } 316 } 317 318 // Clear the instruction list and skid buffer in case they have any 319 // insts in them. 320 while (!insts[tid].empty()) { 321 322#if THE_ISA != ALPHA_ISA 323 if (insts[tid].front()->seqNum <= squash_seq_num) { 324 DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 325 "instructions before delay slot [sn:%i]. %i insts" 326 "left in decode.\n", tid, squash_seq_num, 327 insts[tid].size()); 328 break; 329 } 330#endif 331 insts[tid].pop(); 332 } 333 334 while (!skidBuffer[tid].empty()) { 335 336#if THE_ISA != ALPHA_ISA 337 if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 338 DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 339 "instructions before delay slot [sn:%i]. %i insts" 340 "left in decode.\n", tid, squash_seq_num, 341 insts[tid].size()); 342 break; 343 } 344#endif 345 skidBuffer[tid].pop(); 346 } 347 348 // Squash instructions up until this one 349 cpu->removeInstsUntil(squash_seq_num, tid); 350} 351 352template<class Impl> 353unsigned 354DefaultDecode<Impl>::squash(unsigned tid) 355{ 356 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 357 358 if (decodeStatus[tid] == Blocked || 359 decodeStatus[tid] == Unblocking) { 360#if !FULL_SYSTEM 361 // In syscall emulation, we can have both a block and a squash due 362 // to a syscall in the same cycle. This would cause both signals to 363 // be high. This shouldn't happen in full system. 364 // @todo: Determine if this still happens. 365 if (toFetch->decodeBlock[tid]) { 366 toFetch->decodeBlock[tid] = 0; 367 } else { 368 toFetch->decodeUnblock[tid] = 1; 369 } 370#else 371 toFetch->decodeUnblock[tid] = 1; 372#endif 373 } 374 375 // Set status to squashing. 376 decodeStatus[tid] = Squashing; 377 378 // Go through incoming instructions from fetch and squash them. 379 unsigned squash_count = 0; 380 381 for (int i=0; i<fromFetch->size; i++) { 382 if (fromFetch->insts[i]->threadNumber == tid) { 383 fromFetch->insts[i]->setSquashed(); 384 squash_count++; 385 } 386 } 387 388 // Clear the instruction list and skid buffer in case they have any 389 // insts in them. 390 while (!insts[tid].empty()) { 391 insts[tid].pop(); 392 } 393 394 while (!skidBuffer[tid].empty()) { 395 skidBuffer[tid].pop(); 396 } 397 398 return squash_count; 399} 400 401template<class Impl> 402void 403DefaultDecode<Impl>::skidInsert(unsigned tid) 404{ 405 DynInstPtr inst = NULL; 406 407 while (!insts[tid].empty()) { 408 inst = insts[tid].front(); 409 410 insts[tid].pop(); 411 412 assert(tid == inst->threadNumber); 413 414 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 415 inst->seqNum, inst->readPC(), inst->threadNumber); 416 417 skidBuffer[tid].push(inst); 418 } 419 420 // @todo: Eventually need to enforce this by not letting a thread 421 // fetch past its skidbuffer 422 assert(skidBuffer[tid].size() <= skidBufferMax); 423} 424 425template<class Impl> 426bool 427DefaultDecode<Impl>::skidsEmpty() 428{ 429 list<unsigned>::iterator threads = (*activeThreads).begin(); 430 431 while (threads != (*activeThreads).end()) { 432 if (!skidBuffer[*threads++].empty()) 433 return false; 434 } 435 436 return true; 437} 438 439template<class Impl> 440void 441DefaultDecode<Impl>::updateStatus() 442{ 443 bool any_unblocking = false; 444 445 list<unsigned>::iterator threads = (*activeThreads).begin(); 446 447 threads = (*activeThreads).begin(); 448 449 while (threads != (*activeThreads).end()) { 450 unsigned tid = *threads++; 451 452 if (decodeStatus[tid] == Unblocking) { 453 any_unblocking = true; 454 break; 455 } 456 } 457 458 // Decode will have activity if it's unblocking. 459 if (any_unblocking) { 460 if (_status == Inactive) { 461 _status = Active; 462 463 DPRINTF(Activity, "Activating stage.\n"); 464 465 cpu->activateStage(O3CPU::DecodeIdx); 466 } 467 } else { 468 // If it's not unblocking, then decode will not have any internal 469 // activity. Switch it to inactive. 470 if (_status == Active) { 471 _status = Inactive; 472 DPRINTF(Activity, "Deactivating stage.\n"); 473 474 cpu->deactivateStage(O3CPU::DecodeIdx); 475 } 476 } 477} 478 479template <class Impl> 480void 481DefaultDecode<Impl>::sortInsts() 482{ 483 int insts_from_fetch = fromFetch->size; 484#ifdef DEBUG 485 for (int i=0; i < numThreads; i++) 486 assert(insts[i].empty()); 487#endif 488 for (int i = 0; i < insts_from_fetch; ++i) { 489 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 490 } 491} 492 493template<class Impl> 494void 495DefaultDecode<Impl>::readStallSignals(unsigned tid) 496{ 497 if (fromRename->renameBlock[tid]) { 498 stalls[tid].rename = true; 499 } 500 501 if (fromRename->renameUnblock[tid]) { 502 assert(stalls[tid].rename); 503 stalls[tid].rename = false; 504 } 505 506 if (fromIEW->iewBlock[tid]) { 507 stalls[tid].iew = true; 508 } 509 510 if (fromIEW->iewUnblock[tid]) { 511 assert(stalls[tid].iew); 512 stalls[tid].iew = false; 513 } 514 515 if (fromCommit->commitBlock[tid]) { 516 stalls[tid].commit = true; 517 } 518 519 if (fromCommit->commitUnblock[tid]) { 520 assert(stalls[tid].commit); 521 stalls[tid].commit = false; 522 } 523} 524 525template <class Impl> 526bool 527DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 528{ 529 // Check if there's a squash signal, squash if there is. 530 // Check stall signals, block if necessary. 531 // If status was blocked 532 // Check if stall conditions have passed 533 // if so then go to unblocking 534 // If status was Squashing 535 // check if squashing is not high. Switch to running this cycle. 536 537 // Update the per thread stall statuses. 538 readStallSignals(tid); 539 540 // Check squash signals from commit. 541 if (fromCommit->commitInfo[tid].squash) { 542 543 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 544 "from commit.\n", tid); 545 546 squash(tid); 547 548 return true; 549 } 550 551 // Check ROB squash signals from commit. 552 if (fromCommit->commitInfo[tid].robSquashing) { 553 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 554 555 // Continue to squash. 556 decodeStatus[tid] = Squashing; 557 558 return true; 559 } 560 561 if (checkStall(tid)) { 562 return block(tid); 563 } 564 565 if (decodeStatus[tid] == Blocked) { 566 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 567 tid); 568 569 decodeStatus[tid] = Unblocking; 570 571 unblock(tid); 572 573 return true; 574 } 575 576 if (decodeStatus[tid] == Squashing) { 577 // Switch status to running if decode isn't being told to block or 578 // squash this cycle. 579 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 580 tid); 581 582 decodeStatus[tid] = Running; 583 584 return false; 585 } 586 587 // If we've reached this point, we have not gotten any signals that 588 // cause decode to change its status. Decode remains the same as before. 589 return false; 590} 591 592template<class Impl> 593void 594DefaultDecode<Impl>::tick() 595{ 596 wroteToTimeBuffer = false; 597 598 bool status_change = false; 599 600 toRenameIndex = 0; 601 602 list<unsigned>::iterator threads = (*activeThreads).begin(); 603 604 sortInsts(); 605 606 //Check stall and squash signals. 607 while (threads != (*activeThreads).end()) { 608 unsigned tid = *threads++; 609 610 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 611 status_change = checkSignalsAndUpdate(tid) || status_change; 612 613 decode(status_change, tid); 614 } 615 616 if (status_change) { 617 updateStatus(); 618 } 619 620 if (wroteToTimeBuffer) { 621 DPRINTF(Activity, "Activity this cycle.\n"); 622 623 cpu->activityThisCycle(); 624 } 625} 626 627template<class Impl> 628void 629DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 630{ 631 // If status is Running or idle, 632 // call decodeInsts() 633 // If status is Unblocking, 634 // buffer any instructions coming from fetch 635 // continue trying to empty skid buffer 636 // check if stall conditions have passed 637 638 if (decodeStatus[tid] == Blocked) { 639 ++decodeBlockedCycles; 640 } else if (decodeStatus[tid] == Squashing) { 641 ++decodeSquashCycles; 642 } 643 644 // Decode should try to decode as many instructions as its bandwidth 645 // will allow, as long as it is not currently blocked. 646 if (decodeStatus[tid] == Running || 647 decodeStatus[tid] == Idle) { 648 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 649 "stage.\n",tid); 650 651 decodeInsts(tid); 652 } else if (decodeStatus[tid] == Unblocking) { 653 // Make sure that the skid buffer has something in it if the 654 // status is unblocking. 655 assert(!skidsEmpty()); 656 657 // If the status was unblocking, then instructions from the skid 658 // buffer were used. Remove those instructions and handle 659 // the rest of unblocking. 660 decodeInsts(tid); 661 662 if (fetchInstsValid()) { 663 // Add the current inputs to the skid buffer so they can be 664 // reprocessed when this stage unblocks. 665 skidInsert(tid); 666 } 667 668 status_change = unblock(tid) || status_change; 669 } 670} 671 672template <class Impl> 673void 674DefaultDecode<Impl>::decodeInsts(unsigned tid) 675{ 676 // Instructions can come either from the skid buffer or the list of 677 // instructions coming from fetch, depending on decode's status. 678 int insts_available = decodeStatus[tid] == Unblocking ? 679 skidBuffer[tid].size() : insts[tid].size(); 680 681 if (insts_available == 0) { 682 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 683 " early.\n",tid); 684 // Should I change the status to idle? 685 ++decodeIdleCycles; 686 return; 687 } else if (decodeStatus[tid] == Unblocking) { 688 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 689 "buffer.\n",tid); 690 ++decodeUnblockCycles; 691 } else if (decodeStatus[tid] == Running) { 692 ++decodeRunCycles; 693 } 694 695 DynInstPtr inst; 696 697 std::queue<DynInstPtr> 698 &insts_to_decode = decodeStatus[tid] == Unblocking ? 699 skidBuffer[tid] : insts[tid]; 700 701 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 702 703 while (insts_available > 0 && toRenameIndex < decodeWidth) { 704 assert(!insts_to_decode.empty()); 705 706 inst = insts_to_decode.front(); 707 708 insts_to_decode.pop(); 709 710 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 711 "PC %#x\n", 712 tid, inst->seqNum, inst->readPC()); 713 714 if (inst->isSquashed()) { 715 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 716 "squashed, skipping.\n", 717 tid, inst->seqNum, inst->readPC()); 718 719 ++decodeSquashedInsts; 720 721 --insts_available; 722 723 continue; 724 } 725 726 // Also check if instructions have no source registers. Mark 727 // them as ready to issue at any time. Not sure if this check 728 // should exist here or at a later stage; however it doesn't matter 729 // too much for function correctness. 730 if (inst->numSrcRegs() == 0) { 731 inst->setCanIssue(); 732 } 733 734 // This current instruction is valid, so add it into the decode 735 // queue. The next instruction may not be valid, so check to 736 // see if branches were predicted correctly. 737 toRename->insts[toRenameIndex] = inst; 738 739 ++(toRename->size); 740 ++toRenameIndex; 741 ++decodeDecodedInsts; 742 --insts_available; 743 744 // Ensure that if it was predicted as a branch, it really is a 745 // branch. 746 if (inst->predTaken() && !inst->isControl()) { 747 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC, 748 inst->nextPC + 4); 749 750 panic("Instruction predicted as a branch!"); 751 752 ++decodeControlMispred; 753 754 // Might want to set some sort of boolean and just do 755 // a check at the end 756 squash(inst, inst->threadNumber); 757 758 break; 759 } 760 761 // Go ahead and compute any PC-relative branches. 762 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 763 ++decodeBranchResolved; 764 765 if (inst->branchTarget() != inst->readPredTarg()) { 766 ++decodeBranchMispred; 767 768 // Might want to set some sort of boolean and just do 769 // a check at the end 770#if THE_ISA == ALPHA_ISA 771 squash(inst, inst->threadNumber); 772 inst->setPredTarg(inst->branchTarget()); 773 break; 774#else 775 // If mispredicted as taken, then ignore delay slot 776 // instruction... else keep delay slot and squash 777 // after it is sent to rename 778 if (inst->predTaken() && inst->isCondDelaySlot()) { 779 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 780 "[sn:%i] PC %#x mispredicted as taken.\n", tid, 781 inst->seqNum, inst->PC); 782 bdelayDoneSeqNum[tid] = inst->seqNum; 783 squash(inst, inst->threadNumber); 784 inst->setPredTarg(inst->branchTarget()); 785 break; 786 } else { 787 DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 788 "[sn:%i] PC %#x, will squash after delay slot " 789 "inst. is sent to Rename\n", 790 tid, inst->seqNum, inst->PC); 791 bdelayDoneSeqNum[tid] = inst->seqNum + 1; 792 squashAfterDelaySlot[tid] = true; 793 squashInst[tid] = inst; 794 continue; 795 } 796#endif 797 } 798 } 799 800 if (squashAfterDelaySlot[tid]) { 801 assert(!inst->isSquashed()); 802 squash(squashInst[tid], squashInst[tid]->threadNumber); 803 squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget()); 804 assert(!inst->isSquashed()); 805 break; 806 } 807 } 808 809 // If we didn't process all instructions, then we will need to block 810 // and put all those instructions into the skid buffer. 811 if (!insts_to_decode.empty()) { 812 block(tid); 813 } 814 815 // Record that decode has written to the time buffer for activity 816 // tracking. 817 if (toRenameIndex) { 818 wroteToTimeBuffer = true; 819 } 820} 821