decode_impl.hh revision 2863
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32 33using namespace std; 34 35template<class Impl> 36DefaultDecode<Impl>::DefaultDecode(Params *params) 37 : renameToDecodeDelay(params->renameToDecodeDelay), 38 iewToDecodeDelay(params->iewToDecodeDelay), 39 commitToDecodeDelay(params->commitToDecodeDelay), 40 fetchToDecodeDelay(params->fetchToDecodeDelay), 41 decodeWidth(params->decodeWidth), 42 numThreads(params->numberOfThreads) 43{ 44 _status = Inactive; 45 46 // Setup status, make sure stall signals are clear. 47 for (int i = 0; i < numThreads; ++i) { 48 decodeStatus[i] = Idle; 49 50 stalls[i].rename = false; 51 stalls[i].iew = false; 52 stalls[i].commit = false; 53 } 54 55 // @todo: Make into a parameter 56 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 57} 58 59template <class Impl> 60std::string 61DefaultDecode<Impl>::name() const 62{ 63 return cpu->name() + ".decode"; 64} 65 66template <class Impl> 67void 68DefaultDecode<Impl>::regStats() 69{ 70 decodeIdleCycles 71 .name(name() + ".DECODE:IdleCycles") 72 .desc("Number of cycles decode is idle") 73 .prereq(decodeIdleCycles); 74 decodeBlockedCycles 75 .name(name() + ".DECODE:BlockedCycles") 76 .desc("Number of cycles decode is blocked") 77 .prereq(decodeBlockedCycles); 78 decodeRunCycles 79 .name(name() + ".DECODE:RunCycles") 80 .desc("Number of cycles decode is running") 81 .prereq(decodeRunCycles); 82 decodeUnblockCycles 83 .name(name() + ".DECODE:UnblockCycles") 84 .desc("Number of cycles decode is unblocking") 85 .prereq(decodeUnblockCycles); 86 decodeSquashCycles 87 .name(name() + ".DECODE:SquashCycles") 88 .desc("Number of cycles decode is squashing") 89 .prereq(decodeSquashCycles); 90 decodeBranchResolved 91 .name(name() + ".DECODE:BranchResolved") 92 .desc("Number of times decode resolved a branch") 93 .prereq(decodeBranchResolved); 94 decodeBranchMispred 95 .name(name() + ".DECODE:BranchMispred") 96 .desc("Number of times decode detected a branch misprediction") 97 .prereq(decodeBranchMispred); 98 decodeControlMispred 99 .name(name() + ".DECODE:ControlMispred") 100 .desc("Number of times decode detected an instruction incorrectly" 101 " predicted as a control") 102 .prereq(decodeControlMispred); 103 decodeDecodedInsts 104 .name(name() + ".DECODE:DecodedInsts") 105 .desc("Number of instructions handled by decode") 106 .prereq(decodeDecodedInsts); 107 decodeSquashedInsts 108 .name(name() + ".DECODE:SquashedInsts") 109 .desc("Number of squashed instructions handled by decode") 110 .prereq(decodeSquashedInsts); 111} 112 113template<class Impl> 114void 115DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 116{ 117 DPRINTF(Decode, "Setting CPU pointer.\n"); 118 cpu = cpu_ptr; 119} 120 121template<class Impl> 122void 123DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 124{ 125 DPRINTF(Decode, "Setting time buffer pointer.\n"); 126 timeBuffer = tb_ptr; 127 128 // Setup wire to write information back to fetch. 129 toFetch = timeBuffer->getWire(0); 130 131 // Create wires to get information from proper places in time buffer. 132 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 135} 136 137template<class Impl> 138void 139DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 140{ 141 DPRINTF(Decode, "Setting decode queue pointer.\n"); 142 decodeQueue = dq_ptr; 143 144 // Setup wire to write information to proper place in decode queue. 145 toRename = decodeQueue->getWire(0); 146} 147 148template<class Impl> 149void 150DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 151{ 152 DPRINTF(Decode, "Setting fetch queue pointer.\n"); 153 fetchQueue = fq_ptr; 154 155 // Setup wire to read information from fetch queue. 156 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 157} 158 159template<class Impl> 160void 161DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) 162{ 163 DPRINTF(Decode, "Setting active threads list pointer.\n"); 164 activeThreads = at_ptr; 165} 166 167template <class Impl> 168bool 169DefaultDecode<Impl>::drain() 170{ 171 // Decode is done draining at any time. 172 cpu->signalDrained(); 173 return true; 174} 175 176template <class Impl> 177void 178DefaultDecode<Impl>::takeOverFrom() 179{ 180 _status = Inactive; 181 182 // Be sure to reset state and clear out any old instructions. 183 for (int i = 0; i < numThreads; ++i) { 184 decodeStatus[i] = Idle; 185 186 stalls[i].rename = false; 187 stalls[i].iew = false; 188 stalls[i].commit = false; 189 while (!insts[i].empty()) 190 insts[i].pop(); 191 while (!skidBuffer[i].empty()) 192 skidBuffer[i].pop(); 193 branchCount[i] = 0; 194 } 195 wroteToTimeBuffer = false; 196} 197 198template<class Impl> 199bool 200DefaultDecode<Impl>::checkStall(unsigned tid) const 201{ 202 bool ret_val = false; 203 204 if (stalls[tid].rename) { 205 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 206 ret_val = true; 207 } else if (stalls[tid].iew) { 208 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 209 ret_val = true; 210 } else if (stalls[tid].commit) { 211 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 212 ret_val = true; 213 } 214 215 return ret_val; 216} 217 218template<class Impl> 219inline bool 220DefaultDecode<Impl>::fetchInstsValid() 221{ 222 return fromFetch->size > 0; 223} 224 225template<class Impl> 226bool 227DefaultDecode<Impl>::block(unsigned tid) 228{ 229 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 230 231 // Add the current inputs to the skid buffer so they can be 232 // reprocessed when this stage unblocks. 233 skidInsert(tid); 234 235 // If the decode status is blocked or unblocking then decode has not yet 236 // signalled fetch to unblock. In that case, there is no need to tell 237 // fetch to block. 238 if (decodeStatus[tid] != Blocked) { 239 // Set the status to Blocked. 240 decodeStatus[tid] = Blocked; 241 242 if (decodeStatus[tid] != Unblocking) { 243 toFetch->decodeBlock[tid] = true; 244 wroteToTimeBuffer = true; 245 } 246 247 return true; 248 } 249 250 return false; 251} 252 253template<class Impl> 254bool 255DefaultDecode<Impl>::unblock(unsigned tid) 256{ 257 // Decode is done unblocking only if the skid buffer is empty. 258 if (skidBuffer[tid].empty()) { 259 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 260 toFetch->decodeUnblock[tid] = true; 261 wroteToTimeBuffer = true; 262 263 decodeStatus[tid] = Running; 264 return true; 265 } 266 267 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 268 269 return false; 270} 271 272template<class Impl> 273void 274DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 275{ 276 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 277 "detected at decode.\n", tid); 278 279 // Send back mispredict information. 280 toFetch->decodeInfo[tid].branchMispredict = true; 281 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 282 toFetch->decodeInfo[tid].predIncorrect = true; 283 toFetch->decodeInfo[tid].squash = true; 284 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 285 toFetch->decodeInfo[tid].branchTaken = 286 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 287 288 // Might have to tell fetch to unblock. 289 if (decodeStatus[tid] == Blocked || 290 decodeStatus[tid] == Unblocking) { 291 toFetch->decodeUnblock[tid] = 1; 292 } 293 294 // Set status to squashing. 295 decodeStatus[tid] = Squashing; 296 297 for (int i=0; i<fromFetch->size; i++) { 298 if (fromFetch->insts[i]->threadNumber == tid && 299 fromFetch->insts[i]->seqNum > inst->seqNum) { 300 fromFetch->insts[i]->setSquashed(); 301 } 302 } 303 304 // Clear the instruction list and skid buffer in case they have any 305 // insts in them. 306 while (!insts[tid].empty()) { 307 insts[tid].pop(); 308 } 309 310 while (!skidBuffer[tid].empty()) { 311 skidBuffer[tid].pop(); 312 } 313 314 // Squash instructions up until this one 315 cpu->removeInstsUntil(inst->seqNum, tid); 316} 317 318template<class Impl> 319unsigned 320DefaultDecode<Impl>::squash(unsigned tid) 321{ 322 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 323 324 if (decodeStatus[tid] == Blocked || 325 decodeStatus[tid] == Unblocking) { 326#if !FULL_SYSTEM 327 // In syscall emulation, we can have both a block and a squash due 328 // to a syscall in the same cycle. This would cause both signals to 329 // be high. This shouldn't happen in full system. 330 // @todo: Determine if this still happens. 331 if (toFetch->decodeBlock[tid]) { 332 toFetch->decodeBlock[tid] = 0; 333 } else { 334 toFetch->decodeUnblock[tid] = 1; 335 } 336#else 337 toFetch->decodeUnblock[tid] = 1; 338#endif 339 } 340 341 // Set status to squashing. 342 decodeStatus[tid] = Squashing; 343 344 // Go through incoming instructions from fetch and squash them. 345 unsigned squash_count = 0; 346 347 for (int i=0; i<fromFetch->size; i++) { 348 if (fromFetch->insts[i]->threadNumber == tid) { 349 fromFetch->insts[i]->setSquashed(); 350 squash_count++; 351 } 352 } 353 354 // Clear the instruction list and skid buffer in case they have any 355 // insts in them. 356 while (!insts[tid].empty()) { 357 insts[tid].pop(); 358 } 359 360 while (!skidBuffer[tid].empty()) { 361 skidBuffer[tid].pop(); 362 } 363 364 return squash_count; 365} 366 367template<class Impl> 368void 369DefaultDecode<Impl>::skidInsert(unsigned tid) 370{ 371 DynInstPtr inst = NULL; 372 373 while (!insts[tid].empty()) { 374 inst = insts[tid].front(); 375 376 insts[tid].pop(); 377 378 assert(tid == inst->threadNumber); 379 380 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 381 inst->seqNum, inst->readPC(), inst->threadNumber); 382 383 skidBuffer[tid].push(inst); 384 } 385 386 // @todo: Eventually need to enforce this by not letting a thread 387 // fetch past its skidbuffer 388 assert(skidBuffer[tid].size() <= skidBufferMax); 389} 390 391template<class Impl> 392bool 393DefaultDecode<Impl>::skidsEmpty() 394{ 395 list<unsigned>::iterator threads = (*activeThreads).begin(); 396 397 while (threads != (*activeThreads).end()) { 398 if (!skidBuffer[*threads++].empty()) 399 return false; 400 } 401 402 return true; 403} 404 405template<class Impl> 406void 407DefaultDecode<Impl>::updateStatus() 408{ 409 bool any_unblocking = false; 410 411 list<unsigned>::iterator threads = (*activeThreads).begin(); 412 413 threads = (*activeThreads).begin(); 414 415 while (threads != (*activeThreads).end()) { 416 unsigned tid = *threads++; 417 418 if (decodeStatus[tid] == Unblocking) { 419 any_unblocking = true; 420 break; 421 } 422 } 423 424 // Decode will have activity if it's unblocking. 425 if (any_unblocking) { 426 if (_status == Inactive) { 427 _status = Active; 428 429 DPRINTF(Activity, "Activating stage.\n"); 430 431 cpu->activateStage(O3CPU::DecodeIdx); 432 } 433 } else { 434 // If it's not unblocking, then decode will not have any internal 435 // activity. Switch it to inactive. 436 if (_status == Active) { 437 _status = Inactive; 438 DPRINTF(Activity, "Deactivating stage.\n"); 439 440 cpu->deactivateStage(O3CPU::DecodeIdx); 441 } 442 } 443} 444 445template <class Impl> 446void 447DefaultDecode<Impl>::sortInsts() 448{ 449 int insts_from_fetch = fromFetch->size; 450#ifdef DEBUG 451 for (int i=0; i < numThreads; i++) 452 assert(insts[i].empty()); 453#endif 454 for (int i = 0; i < insts_from_fetch; ++i) { 455 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 456 } 457} 458 459template<class Impl> 460void 461DefaultDecode<Impl>::readStallSignals(unsigned tid) 462{ 463 if (fromRename->renameBlock[tid]) { 464 stalls[tid].rename = true; 465 } 466 467 if (fromRename->renameUnblock[tid]) { 468 assert(stalls[tid].rename); 469 stalls[tid].rename = false; 470 } 471 472 if (fromIEW->iewBlock[tid]) { 473 stalls[tid].iew = true; 474 } 475 476 if (fromIEW->iewUnblock[tid]) { 477 assert(stalls[tid].iew); 478 stalls[tid].iew = false; 479 } 480 481 if (fromCommit->commitBlock[tid]) { 482 stalls[tid].commit = true; 483 } 484 485 if (fromCommit->commitUnblock[tid]) { 486 assert(stalls[tid].commit); 487 stalls[tid].commit = false; 488 } 489} 490 491template <class Impl> 492bool 493DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 494{ 495 // Check if there's a squash signal, squash if there is. 496 // Check stall signals, block if necessary. 497 // If status was blocked 498 // Check if stall conditions have passed 499 // if so then go to unblocking 500 // If status was Squashing 501 // check if squashing is not high. Switch to running this cycle. 502 503 // Update the per thread stall statuses. 504 readStallSignals(tid); 505 506 // Check squash signals from commit. 507 if (fromCommit->commitInfo[tid].squash) { 508 509 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 510 "from commit.\n", tid); 511 512 squash(tid); 513 514 return true; 515 } 516 517 // Check ROB squash signals from commit. 518 if (fromCommit->commitInfo[tid].robSquashing) { 519 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 520 521 // Continue to squash. 522 decodeStatus[tid] = Squashing; 523 524 return true; 525 } 526 527 if (checkStall(tid)) { 528 return block(tid); 529 } 530 531 if (decodeStatus[tid] == Blocked) { 532 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 533 tid); 534 535 decodeStatus[tid] = Unblocking; 536 537 unblock(tid); 538 539 return true; 540 } 541 542 if (decodeStatus[tid] == Squashing) { 543 // Switch status to running if decode isn't being told to block or 544 // squash this cycle. 545 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 546 tid); 547 548 decodeStatus[tid] = Running; 549 550 return false; 551 } 552 553 // If we've reached this point, we have not gotten any signals that 554 // cause decode to change its status. Decode remains the same as before. 555 return false; 556} 557 558template<class Impl> 559void 560DefaultDecode<Impl>::tick() 561{ 562 wroteToTimeBuffer = false; 563 564 bool status_change = false; 565 566 toRenameIndex = 0; 567 568 list<unsigned>::iterator threads = (*activeThreads).begin(); 569 570 sortInsts(); 571 572 //Check stall and squash signals. 573 while (threads != (*activeThreads).end()) { 574 unsigned tid = *threads++; 575 576 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 577 status_change = checkSignalsAndUpdate(tid) || status_change; 578 579 decode(status_change, tid); 580 } 581 582 if (status_change) { 583 updateStatus(); 584 } 585 586 if (wroteToTimeBuffer) { 587 DPRINTF(Activity, "Activity this cycle.\n"); 588 589 cpu->activityThisCycle(); 590 } 591} 592 593template<class Impl> 594void 595DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 596{ 597 // If status is Running or idle, 598 // call decodeInsts() 599 // If status is Unblocking, 600 // buffer any instructions coming from fetch 601 // continue trying to empty skid buffer 602 // check if stall conditions have passed 603 604 if (decodeStatus[tid] == Blocked) { 605 ++decodeBlockedCycles; 606 } else if (decodeStatus[tid] == Squashing) { 607 ++decodeSquashCycles; 608 } 609 610 // Decode should try to decode as many instructions as its bandwidth 611 // will allow, as long as it is not currently blocked. 612 if (decodeStatus[tid] == Running || 613 decodeStatus[tid] == Idle) { 614 DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run " 615 "stage.\n",tid); 616 617 decodeInsts(tid); 618 } else if (decodeStatus[tid] == Unblocking) { 619 // Make sure that the skid buffer has something in it if the 620 // status is unblocking. 621 assert(!skidsEmpty()); 622 623 // If the status was unblocking, then instructions from the skid 624 // buffer were used. Remove those instructions and handle 625 // the rest of unblocking. 626 decodeInsts(tid); 627 628 if (fetchInstsValid()) { 629 // Add the current inputs to the skid buffer so they can be 630 // reprocessed when this stage unblocks. 631 skidInsert(tid); 632 } 633 634 status_change = unblock(tid) || status_change; 635 } 636} 637 638template <class Impl> 639void 640DefaultDecode<Impl>::decodeInsts(unsigned tid) 641{ 642 // Instructions can come either from the skid buffer or the list of 643 // instructions coming from fetch, depending on decode's status. 644 int insts_available = decodeStatus[tid] == Unblocking ? 645 skidBuffer[tid].size() : insts[tid].size(); 646 647 if (insts_available == 0) { 648 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 649 " early.\n",tid); 650 // Should I change the status to idle? 651 ++decodeIdleCycles; 652 return; 653 } else if (decodeStatus[tid] == Unblocking) { 654 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 655 "buffer.\n",tid); 656 ++decodeUnblockCycles; 657 } else if (decodeStatus[tid] == Running) { 658 ++decodeRunCycles; 659 } 660 661 DynInstPtr inst; 662 663 std::queue<DynInstPtr> 664 &insts_to_decode = decodeStatus[tid] == Unblocking ? 665 skidBuffer[tid] : insts[tid]; 666 667 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 668 669 while (insts_available > 0 && toRenameIndex < decodeWidth) { 670 assert(!insts_to_decode.empty()); 671 672 inst = insts_to_decode.front(); 673 674 insts_to_decode.pop(); 675 676 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 677 "PC %#x\n", 678 tid, inst->seqNum, inst->readPC()); 679 680 if (inst->isSquashed()) { 681 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 682 "squashed, skipping.\n", 683 tid, inst->seqNum, inst->readPC()); 684 685 ++decodeSquashedInsts; 686 687 --insts_available; 688 689 continue; 690 } 691 692 // Also check if instructions have no source registers. Mark 693 // them as ready to issue at any time. Not sure if this check 694 // should exist here or at a later stage; however it doesn't matter 695 // too much for function correctness. 696 if (inst->numSrcRegs() == 0) { 697 inst->setCanIssue(); 698 } 699 700 // This current instruction is valid, so add it into the decode 701 // queue. The next instruction may not be valid, so check to 702 // see if branches were predicted correctly. 703 toRename->insts[toRenameIndex] = inst; 704 705 ++(toRename->size); 706 ++toRenameIndex; 707 ++decodeDecodedInsts; 708 --insts_available; 709 710 // Ensure that if it was predicted as a branch, it really is a 711 // branch. 712 if (inst->predTaken() && !inst->isControl()) { 713 panic("Instruction predicted as a branch!"); 714 715 ++decodeControlMispred; 716 717 // Might want to set some sort of boolean and just do 718 // a check at the end 719 squash(inst, inst->threadNumber); 720 721 break; 722 } 723 724 // Go ahead and compute any PC-relative branches. 725 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 726 ++decodeBranchResolved; 727 728 if (inst->branchTarget() != inst->readPredTarg()) { 729 ++decodeBranchMispred; 730 731 // Might want to set some sort of boolean and just do 732 // a check at the end 733 squash(inst, inst->threadNumber); 734 inst->setPredTarg(inst->branchTarget()); 735 736 break; 737 } 738 } 739 } 740 741 // If we didn't process all instructions, then we will need to block 742 // and put all those instructions into the skid buffer. 743 if (!insts_to_decode.empty()) { 744 block(tid); 745 } 746 747 // Record that decode has written to the time buffer for activity 748 // tracking. 749 if (toRenameIndex) { 750 wroteToTimeBuffer = true; 751 } 752} 753