decode_impl.hh revision 2307
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "cpu/o3/decode.hh" 30 31using namespace std; 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(Params *params) 35 : renameToDecodeDelay(params->renameToDecodeDelay), 36 iewToDecodeDelay(params->iewToDecodeDelay), 37 commitToDecodeDelay(params->commitToDecodeDelay), 38 fetchToDecodeDelay(params->fetchToDecodeDelay), 39 decodeWidth(params->decodeWidth), 40 numThreads(params->numberOfThreads) 41{ 42 DPRINTF(Decode, "decodeWidth=%i.\n", decodeWidth); 43 _status = Inactive; 44 45 for (int i = 0; i < numThreads; ++i) { 46 decodeStatus[i] = Idle; 47 48 stalls[i].rename = false; 49 stalls[i].iew = false; 50 stalls[i].commit = false; 51 } 52 53 // @todo: Make into a parameter 54 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 55} 56 57template <class Impl> 58std::string 59DefaultDecode<Impl>::name() const 60{ 61 return cpu->name() + ".decode"; 62} 63 64template <class Impl> 65void 66DefaultDecode<Impl>::regStats() 67{ 68 decodeIdleCycles 69 .name(name() + ".DECODE:IdleCycles") 70 .desc("Number of cycles decode is idle") 71 .prereq(decodeIdleCycles); 72 decodeBlockedCycles 73 .name(name() + ".DECODE:BlockedCycles") 74 .desc("Number of cycles decode is blocked") 75 .prereq(decodeBlockedCycles); 76 decodeRunCycles 77 .name(name() + ".DECODE:RunCycles") 78 .desc("Number of cycles decode is running") 79 .prereq(decodeRunCycles); 80 decodeUnblockCycles 81 .name(name() + ".DECODE:UnblockCycles") 82 .desc("Number of cycles decode is unblocking") 83 .prereq(decodeUnblockCycles); 84 decodeSquashCycles 85 .name(name() + ".DECODE:SquashCycles") 86 .desc("Number of cycles decode is squashing") 87 .prereq(decodeSquashCycles); 88 decodeBranchResolved 89 .name(name() + ".DECODE:BranchResolved") 90 .desc("Number of times decode resolved a branch") 91 .prereq(decodeBranchResolved); 92 decodeBranchMispred 93 .name(name() + ".DECODE:BranchMispred") 94 .desc("Number of times decode detected a branch misprediction") 95 .prereq(decodeBranchMispred); 96 decodeControlMispred 97 .name(name() + ".DECODE:ControlMispred") 98 .desc("Number of times decode detected an instruction incorrectly" 99 " predicted as a control") 100 .prereq(decodeControlMispred); 101 decodeDecodedInsts 102 .name(name() + ".DECODE:DecodedInsts") 103 .desc("Number of instructions handled by decode") 104 .prereq(decodeDecodedInsts); 105 decodeSquashedInsts 106 .name(name() + ".DECODE:SquashedInsts") 107 .desc("Number of squashed instructions handled by decode") 108 .prereq(decodeSquashedInsts); 109} 110 111template<class Impl> 112void 113DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr) 114{ 115 DPRINTF(Decode, "Setting CPU pointer.\n"); 116 cpu = cpu_ptr; 117} 118 119template<class Impl> 120void 121DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 122{ 123 DPRINTF(Decode, "Setting time buffer pointer.\n"); 124 timeBuffer = tb_ptr; 125 126 // Setup wire to write information back to fetch. 127 toFetch = timeBuffer->getWire(0); 128 129 // Create wires to get information from proper places in time buffer. 130 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 131 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 132 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 133} 134 135template<class Impl> 136void 137DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 138{ 139 DPRINTF(Decode, "Setting decode queue pointer.\n"); 140 decodeQueue = dq_ptr; 141 142 // Setup wire to write information to proper place in decode queue. 143 toRename = decodeQueue->getWire(0); 144} 145 146template<class Impl> 147void 148DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 149{ 150 DPRINTF(Decode, "Setting fetch queue pointer.\n"); 151 fetchQueue = fq_ptr; 152 153 // Setup wire to read information from fetch queue. 154 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 155} 156 157template<class Impl> 158void 159DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) 160{ 161 DPRINTF(Decode, "Setting active threads list pointer.\n"); 162 activeThreads = at_ptr; 163} 164 165template <class Impl> 166void 167DefaultDecode<Impl>::switchOut() 168{ 169} 170 171template <class Impl> 172void 173DefaultDecode<Impl>::takeOverFrom() 174{ 175 _status = Inactive; 176 177 for (int i = 0; i < numThreads; ++i) { 178 decodeStatus[i] = Idle; 179 180 stalls[i].rename = false; 181 stalls[i].iew = false; 182 stalls[i].commit = false; 183 while (!insts[i].empty()) 184 insts[i].pop(); 185 while (!skidBuffer[i].empty()) 186 skidBuffer[i].pop(); 187 branchCount[i] = 0; 188 } 189 wroteToTimeBuffer = false; 190} 191 192template<class Impl> 193bool 194DefaultDecode<Impl>::checkStall(unsigned tid) const 195{ 196 bool ret_val = false; 197 198 if (stalls[tid].rename) { 199 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 200 ret_val = true; 201 } else if (stalls[tid].iew) { 202 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 203 ret_val = true; 204 } else if (stalls[tid].commit) { 205 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 206 ret_val = true; 207 } 208 209 return ret_val; 210} 211 212template<class Impl> 213inline bool 214DefaultDecode<Impl>::fetchInstsValid() 215{ 216 return fromFetch->size > 0; 217} 218 219template<class Impl> 220bool 221DefaultDecode<Impl>::block(unsigned tid) 222{ 223 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 224 225 // If the decode status is blocked or unblocking then decode has not yet 226 // signalled fetch to unblock. In that case, there is no need to tell 227 // fetch to block. 228 if (decodeStatus[tid] != Blocked && 229 decodeStatus[tid] != Unblocking) { 230 toFetch->decodeBlock[tid] = true; 231 wroteToTimeBuffer = true; 232 } 233 234 // Add the current inputs to the skid buffer so they can be 235 // reprocessed when this stage unblocks. 236 skidInsert(tid); 237 238 if (decodeStatus[tid] != Blocked) { 239 // Set the status to Blocked. 240 decodeStatus[tid] = Blocked; 241 return true; 242 } 243 244 return false; 245} 246 247template<class Impl> 248bool 249DefaultDecode<Impl>::unblock(unsigned tid) 250{ 251 DPRINTF(Decode, "[tid:%u]: Trying to unblock.\n", tid); 252 253 // Decode is done unblocking only if the skid buffer is empty. 254 if (skidBuffer[tid].empty()) { 255 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 256 toFetch->decodeUnblock[tid] = true; 257 wroteToTimeBuffer = true; 258 259 decodeStatus[tid] = Running; 260 return true; 261 } 262 263 return false; 264} 265 266template<class Impl> 267void 268DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 269{ 270 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 271 "detected at decode.\n", tid); 272 273 toFetch->decodeInfo[tid].branchMispredict = true; 274 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 275 toFetch->decodeInfo[tid].predIncorrect = true; 276 toFetch->decodeInfo[tid].squash = true; 277 toFetch->decodeInfo[tid].nextPC = inst->readNextPC(); 278 toFetch->decodeInfo[tid].branchTaken = true; 279 280 if (decodeStatus[tid] == Blocked || 281 decodeStatus[tid] == Unblocking) { 282 toFetch->decodeUnblock[tid] = 1; 283 } 284 285 // Set status to squashing. 286 decodeStatus[tid] = Squashing; 287 288 for (int i=0; i<fromFetch->size; i++) { 289 if (fromFetch->insts[i]->threadNumber == tid && 290 fromFetch->insts[i]->seqNum > inst->seqNum) { 291 fromFetch->insts[i]->squashed = true; 292 } 293 } 294 295 while (!insts[tid].empty()) { 296 insts[tid].pop(); 297 } 298 299 // Clear the skid buffer in case it has any data in it. 300 while (!skidBuffer[tid].empty()) { 301 skidBuffer[tid].pop(); 302 } 303 304 // Squash instructions up until this one 305 cpu->removeInstsUntil(inst->seqNum, tid); 306} 307 308template<class Impl> 309unsigned 310DefaultDecode<Impl>::squash(unsigned tid) 311{ 312 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 313 314 if (decodeStatus[tid] == Blocked || 315 decodeStatus[tid] == Unblocking) { 316#if !FULL_SYSTEM 317 // In syscall emulation, we can have both a block and a squash due 318 // to a syscall in the same cycle. This would cause both signals to 319 // be high. This shouldn't happen in full system. 320 if (toFetch->decodeBlock[tid]) { 321 toFetch->decodeBlock[tid] = 0; 322 } else { 323 toFetch->decodeUnblock[tid] = 1; 324 } 325#else 326 toFetch->decodeUnblock[tid] = 1; 327#endif 328 } 329 330 // Set status to squashing. 331 decodeStatus[tid] = Squashing; 332 333 // Go through incoming instructions from fetch and squash them. 334 unsigned squash_count = 0; 335 336 for (int i=0; i<fromFetch->size; i++) { 337 if (fromFetch->insts[i]->threadNumber == tid) { 338 fromFetch->insts[i]->squashed = true; 339 squash_count++; 340 } 341 } 342 343 while (!insts[tid].empty()) { 344 insts[tid].pop(); 345 } 346 347 // Clear the skid buffer in case it has any data in it. 348 while (!skidBuffer[tid].empty()) { 349 skidBuffer[tid].pop(); 350 } 351 352 return squash_count; 353} 354 355template<class Impl> 356void 357DefaultDecode<Impl>::skidInsert(unsigned tid) 358{ 359 DynInstPtr inst = NULL; 360 361 while (!insts[tid].empty()) { 362 inst = insts[tid].front(); 363 364 insts[tid].pop(); 365 366 assert(tid == inst->threadNumber); 367 368 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 369 inst->seqNum, inst->readPC(), inst->threadNumber); 370 371 skidBuffer[tid].push(inst); 372 } 373 374 // Eventually need to enforce this by not letting a thread 375 // fetch past its skidbuffer 376 assert(skidBuffer[tid].size() <= skidBufferMax); 377} 378 379template<class Impl> 380bool 381DefaultDecode<Impl>::skidsEmpty() 382{ 383 list<unsigned>::iterator threads = (*activeThreads).begin(); 384 385 while (threads != (*activeThreads).end()) { 386 if (!skidBuffer[*threads++].empty()) 387 return false; 388 } 389 390 return true; 391} 392 393template<class Impl> 394void 395DefaultDecode<Impl>::updateStatus() 396{ 397 bool any_unblocking = false; 398 399 list<unsigned>::iterator threads = (*activeThreads).begin(); 400 401 threads = (*activeThreads).begin(); 402 403 while (threads != (*activeThreads).end()) { 404 unsigned tid = *threads++; 405 406 if (decodeStatus[tid] == Unblocking) { 407 any_unblocking = true; 408 break; 409 } 410 } 411 412 // Decode will have activity if it's unblocking. 413 if (any_unblocking) { 414 if (_status == Inactive) { 415 _status = Active; 416 417 DPRINTF(Activity, "Activating stage.\n"); 418 419 cpu->activateStage(FullCPU::DecodeIdx); 420 } 421 } else { 422 // If it's not unblocking, then decode will not have any internal 423 // activity. Switch it to inactive. 424 if (_status == Active) { 425 _status = Inactive; 426 DPRINTF(Activity, "Deactivating stage.\n"); 427 428 cpu->deactivateStage(FullCPU::DecodeIdx); 429 } 430 } 431} 432 433template <class Impl> 434void 435DefaultDecode<Impl>::sortInsts() 436{ 437 int insts_from_fetch = fromFetch->size; 438 439 for (int i=0; i < numThreads; i++) 440 assert(insts[i].empty()); 441 442 for (int i = 0; i < insts_from_fetch; ++i) { 443 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 444 } 445} 446 447template<class Impl> 448void 449DefaultDecode<Impl>::readStallSignals(unsigned tid) 450{ 451 if (fromRename->renameBlock[tid]) { 452 stalls[tid].rename = true; 453 } 454 455 if (fromRename->renameUnblock[tid]) { 456 assert(stalls[tid].rename); 457 stalls[tid].rename = false; 458 } 459 460 if (fromIEW->iewBlock[tid]) { 461 stalls[tid].iew = true; 462 } 463 464 if (fromIEW->iewUnblock[tid]) { 465 assert(stalls[tid].iew); 466 stalls[tid].iew = false; 467 } 468 469 if (fromCommit->commitBlock[tid]) { 470 stalls[tid].commit = true; 471 } 472 473 if (fromCommit->commitUnblock[tid]) { 474 assert(stalls[tid].commit); 475 stalls[tid].commit = false; 476 } 477} 478 479template <class Impl> 480bool 481DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 482{ 483 // Check if there's a squash signal, squash if there is. 484 // Check stall signals, block if necessary. 485 // If status was blocked 486 // Check if stall conditions have passed 487 // if so then go to unblocking 488 // If status was Squashing 489 // check if squashing is not high. Switch to running this cycle. 490 491 // Update the per thread stall statuses. 492 readStallSignals(tid); 493 494 // Check squash signals from commit. 495 if (fromCommit->commitInfo[tid].squash) { 496 497 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 498 "from commit.\n", tid); 499 500 squash(tid); 501 502 return true; 503 } 504 505 // Check ROB squash signals from commit. 506 if (fromCommit->commitInfo[tid].robSquashing) { 507 DPRINTF(Decode, "[tid:%]: ROB is still squashing.\n",tid); 508 509 // Continue to squash. 510 decodeStatus[tid] = Squashing; 511 512 return true; 513 } 514 515 if (checkStall(tid)) { 516 return block(tid); 517 } 518 519 if (decodeStatus[tid] == Blocked) { 520 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 521 tid); 522 523 decodeStatus[tid] = Unblocking; 524 525 unblock(tid); 526 527 return true; 528 } 529 530 if (decodeStatus[tid] == Squashing) { 531 // Switch status to running if decode isn't being told to block or 532 // squash this cycle. 533 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 534 tid); 535 536 decodeStatus[tid] = Running; 537 538 return false; 539 } 540 541 // If we've reached this point, we have not gotten any signals that 542 // cause decode to change its status. Decode remains the same as before. 543 return false; 544} 545 546template<class Impl> 547void 548DefaultDecode<Impl>::tick() 549{ 550 wroteToTimeBuffer = false; 551 552 bool status_change = false; 553 554 toRenameIndex = 0; 555 556 list<unsigned>::iterator threads = (*activeThreads).begin(); 557 558 sortInsts(); 559 560 //Check stall and squash signals. 561 while (threads != (*activeThreads).end()) { 562 unsigned tid = *threads++; 563 564 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 565 status_change = checkSignalsAndUpdate(tid) || status_change; 566 567 decode(status_change, tid); 568 } 569 570 if (status_change) { 571 updateStatus(); 572 } 573 574 if (wroteToTimeBuffer) { 575 DPRINTF(Activity, "Activity this cycle.\n"); 576 577 cpu->activityThisCycle(); 578 } 579} 580 581template<class Impl> 582void 583DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 584{ 585 // If status is Running or idle, 586 // call decodeInsts() 587 // If status is Unblocking, 588 // buffer any instructions coming from fetch 589 // continue trying to empty skid buffer 590 // check if stall conditions have passed 591 592 if (decodeStatus[tid] == Blocked) { 593 ++decodeBlockedCycles; 594 } else if (decodeStatus[tid] == Squashing) { 595 ++decodeSquashCycles; 596 } 597 598 // Decode should try to decode as many instructions as its bandwidth 599 // will allow, as long as it is not currently blocked. 600 if (decodeStatus[tid] == Running || 601 decodeStatus[tid] == Idle) { 602 DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run " 603 "stage.\n",tid); 604 605 decodeInsts(tid); 606 } else if (decodeStatus[tid] == Unblocking) { 607 // Make sure that the skid buffer has something in it if the 608 // status is unblocking. 609 assert(!skidsEmpty()); 610 611 // If the status was unblocking, then instructions from the skid 612 // buffer were used. Remove those instructions and handle 613 // the rest of unblocking. 614 decodeInsts(tid); 615 616 if (fetchInstsValid()) { 617 // Add the current inputs to the skid buffer so they can be 618 // reprocessed when this stage unblocks. 619 skidInsert(tid); 620 } 621 622 status_change = unblock(tid) || status_change; 623 } 624} 625 626template <class Impl> 627void 628DefaultDecode<Impl>::decodeInsts(unsigned tid) 629{ 630 // Instructions can come either from the skid buffer or the list of 631 // instructions coming from fetch, depending on decode's status. 632 int insts_available = decodeStatus[tid] == Unblocking ? 633 skidBuffer[tid].size() : insts[tid].size(); 634 635 if (insts_available == 0) { 636 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 637 " early.\n",tid); 638 // Should I change the status to idle? 639 ++decodeIdleCycles; 640 return; 641 } else if (decodeStatus[tid] == Unblocking) { 642 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 643 "buffer.\n",tid); 644 ++decodeUnblockCycles; 645 } else if (decodeStatus[tid] == Running) { 646 ++decodeRunCycles; 647 } 648 649 DynInstPtr inst; 650 651 std::queue<DynInstPtr> 652 &insts_to_decode = decodeStatus[tid] == Unblocking ? 653 skidBuffer[tid] : insts[tid]; 654 655 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 656 657 while (insts_available > 0 && toRenameIndex < decodeWidth) { 658 assert(!insts_to_decode.empty()); 659 660 inst = insts_to_decode.front(); 661 662 insts_to_decode.pop(); 663 664 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 665 "PC %#x\n", 666 tid, inst->seqNum, inst->readPC()); 667 668 if (inst->isSquashed()) { 669 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 670 "squashed, skipping.\n", 671 tid, inst->seqNum, inst->readPC()); 672 673 ++decodeSquashedInsts; 674 675 --insts_available; 676 677 continue; 678 } 679 680 // Also check if instructions have no source registers. Mark 681 // them as ready to issue at any time. Not sure if this check 682 // should exist here or at a later stage; however it doesn't matter 683 // too much for function correctness. 684 if (inst->numSrcRegs() == 0) { 685 inst->setCanIssue(); 686 } 687 688 // This current instruction is valid, so add it into the decode 689 // queue. The next instruction may not be valid, so check to 690 // see if branches were predicted correctly. 691 toRename->insts[toRenameIndex] = inst; 692 693 ++(toRename->size); 694 ++toRenameIndex; 695 ++decodeDecodedInsts; 696 --insts_available; 697 698 // Ensure that if it was predicted as a branch, it really is a 699 // branch. 700 if (inst->predTaken() && !inst->isControl()) { 701 panic("Instruction predicted as a branch!"); 702 703 ++decodeControlMispred; 704 705 // Might want to set some sort of boolean and just do 706 // a check at the end 707 squash(inst, inst->threadNumber); 708 709 break; 710 } 711 712 // Go ahead and compute any PC-relative branches. 713 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 714 ++decodeBranchResolved; 715 inst->setNextPC(inst->branchTarget()); 716 717 if (inst->mispredicted()) { 718 ++decodeBranchMispred; 719 720 // Might want to set some sort of boolean and just do 721 // a check at the end 722 squash(inst, inst->threadNumber); 723 724 break; 725 } 726 } 727 } 728 729 // If we didn't process all instructions, then we will need to block 730 // and put all those instructions into the skid buffer. 731 if (!insts_to_decode.empty()) { 732 block(tid); 733 } 734 735 // Record that decode has written to the time buffer for activity 736 // tracking. 737 if (toRenameIndex) { 738 wroteToTimeBuffer = true; 739 } 740} 741