decode_impl.hh revision 10328
1/*
2 * Copyright (c) 2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_IMPL_HH__
44#define __CPU_O3_DECODE_IMPL_HH__
45
46#include "arch/types.hh"
47#include "base/trace.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/decode.hh"
50#include "cpu/inst_seq.hh"
51#include "debug/Activity.hh"
52#include "debug/Decode.hh"
53#include "debug/O3PipeView.hh"
54#include "params/DerivO3CPU.hh"
55#include "sim/full_system.hh"
56
57// clang complains about std::set being overloaded with Packet::set if
58// we open up the entire namespace std
59using std::list;
60
61template<class Impl>
62DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
63    : cpu(_cpu),
64      renameToDecodeDelay(params->renameToDecodeDelay),
65      iewToDecodeDelay(params->iewToDecodeDelay),
66      commitToDecodeDelay(params->commitToDecodeDelay),
67      fetchToDecodeDelay(params->fetchToDecodeDelay),
68      decodeWidth(params->decodeWidth),
69      numThreads(params->numThreads)
70{
71    if (decodeWidth > Impl::MaxWidth)
72        fatal("decodeWidth (%d) is larger than compiled limit (%d),\n"
73             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
74             decodeWidth, static_cast<int>(Impl::MaxWidth));
75
76    // @todo: Make into a parameter
77    skidBufferMax = (fetchToDecodeDelay + 1) *  params->fetchWidth;
78}
79
80template<class Impl>
81void
82DefaultDecode<Impl>::startupStage()
83{
84    resetStage();
85}
86
87template<class Impl>
88void
89DefaultDecode<Impl>::resetStage()
90{
91    _status = Inactive;
92
93    // Setup status, make sure stall signals are clear.
94    for (ThreadID tid = 0; tid < numThreads; ++tid) {
95        decodeStatus[tid] = Idle;
96
97        stalls[tid].rename = false;
98    }
99}
100
101template <class Impl>
102std::string
103DefaultDecode<Impl>::name() const
104{
105    return cpu->name() + ".decode";
106}
107
108template <class Impl>
109void
110DefaultDecode<Impl>::regStats()
111{
112    decodeIdleCycles
113        .name(name() + ".IdleCycles")
114        .desc("Number of cycles decode is idle")
115        .prereq(decodeIdleCycles);
116    decodeBlockedCycles
117        .name(name() + ".BlockedCycles")
118        .desc("Number of cycles decode is blocked")
119        .prereq(decodeBlockedCycles);
120    decodeRunCycles
121        .name(name() + ".RunCycles")
122        .desc("Number of cycles decode is running")
123        .prereq(decodeRunCycles);
124    decodeUnblockCycles
125        .name(name() + ".UnblockCycles")
126        .desc("Number of cycles decode is unblocking")
127        .prereq(decodeUnblockCycles);
128    decodeSquashCycles
129        .name(name() + ".SquashCycles")
130        .desc("Number of cycles decode is squashing")
131        .prereq(decodeSquashCycles);
132    decodeBranchResolved
133        .name(name() + ".BranchResolved")
134        .desc("Number of times decode resolved a branch")
135        .prereq(decodeBranchResolved);
136    decodeBranchMispred
137        .name(name() + ".BranchMispred")
138        .desc("Number of times decode detected a branch misprediction")
139        .prereq(decodeBranchMispred);
140    decodeControlMispred
141        .name(name() + ".ControlMispred")
142        .desc("Number of times decode detected an instruction incorrectly"
143              " predicted as a control")
144        .prereq(decodeControlMispred);
145    decodeDecodedInsts
146        .name(name() + ".DecodedInsts")
147        .desc("Number of instructions handled by decode")
148        .prereq(decodeDecodedInsts);
149    decodeSquashedInsts
150        .name(name() + ".SquashedInsts")
151        .desc("Number of squashed instructions handled by decode")
152        .prereq(decodeSquashedInsts);
153}
154
155template<class Impl>
156void
157DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
158{
159    timeBuffer = tb_ptr;
160
161    // Setup wire to write information back to fetch.
162    toFetch = timeBuffer->getWire(0);
163
164    // Create wires to get information from proper places in time buffer.
165    fromRename = timeBuffer->getWire(-renameToDecodeDelay);
166    fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
167    fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
168}
169
170template<class Impl>
171void
172DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
173{
174    decodeQueue = dq_ptr;
175
176    // Setup wire to write information to proper place in decode queue.
177    toRename = decodeQueue->getWire(0);
178}
179
180template<class Impl>
181void
182DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
183{
184    fetchQueue = fq_ptr;
185
186    // Setup wire to read information from fetch queue.
187    fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
188}
189
190template<class Impl>
191void
192DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
193{
194    activeThreads = at_ptr;
195}
196
197template <class Impl>
198void
199DefaultDecode<Impl>::drainSanityCheck() const
200{
201    for (ThreadID tid = 0; tid < numThreads; ++tid) {
202        assert(insts[tid].empty());
203        assert(skidBuffer[tid].empty());
204    }
205}
206
207template <class Impl>
208bool
209DefaultDecode<Impl>::isDrained() const
210{
211    for (ThreadID tid = 0; tid < numThreads; ++tid) {
212        if (!insts[tid].empty() || !skidBuffer[tid].empty())
213            return false;
214    }
215    return true;
216}
217
218template<class Impl>
219bool
220DefaultDecode<Impl>::checkStall(ThreadID tid) const
221{
222    bool ret_val = false;
223
224    if (stalls[tid].rename) {
225        DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
226        ret_val = true;
227    }
228
229    return ret_val;
230}
231
232template<class Impl>
233inline bool
234DefaultDecode<Impl>::fetchInstsValid()
235{
236    return fromFetch->size > 0;
237}
238
239template<class Impl>
240bool
241DefaultDecode<Impl>::block(ThreadID tid)
242{
243    DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
244
245    // Add the current inputs to the skid buffer so they can be
246    // reprocessed when this stage unblocks.
247    skidInsert(tid);
248
249    // If the decode status is blocked or unblocking then decode has not yet
250    // signalled fetch to unblock. In that case, there is no need to tell
251    // fetch to block.
252    if (decodeStatus[tid] != Blocked) {
253        // Set the status to Blocked.
254        decodeStatus[tid] = Blocked;
255
256        if (toFetch->decodeUnblock[tid]) {
257            toFetch->decodeUnblock[tid] = false;
258        } else {
259            toFetch->decodeBlock[tid] = true;
260            wroteToTimeBuffer = true;
261        }
262
263        return true;
264    }
265
266    return false;
267}
268
269template<class Impl>
270bool
271DefaultDecode<Impl>::unblock(ThreadID tid)
272{
273    // Decode is done unblocking only if the skid buffer is empty.
274    if (skidBuffer[tid].empty()) {
275        DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
276        toFetch->decodeUnblock[tid] = true;
277        wroteToTimeBuffer = true;
278
279        decodeStatus[tid] = Running;
280        return true;
281    }
282
283    DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
284
285    return false;
286}
287
288template<class Impl>
289void
290DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
291{
292    DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
293            "prediction detected at decode.\n", tid, inst->seqNum);
294
295    // Send back mispredict information.
296    toFetch->decodeInfo[tid].branchMispredict = true;
297    toFetch->decodeInfo[tid].predIncorrect = true;
298    toFetch->decodeInfo[tid].mispredictInst = inst;
299    toFetch->decodeInfo[tid].squash = true;
300    toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
301    toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
302    toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
303    toFetch->decodeInfo[tid].squashInst = inst;
304    if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
305            toFetch->decodeInfo[tid].branchTaken = true;
306    }
307
308    InstSeqNum squash_seq_num = inst->seqNum;
309
310    // Might have to tell fetch to unblock.
311    if (decodeStatus[tid] == Blocked ||
312        decodeStatus[tid] == Unblocking) {
313        toFetch->decodeUnblock[tid] = 1;
314    }
315
316    // Set status to squashing.
317    decodeStatus[tid] = Squashing;
318
319    for (int i=0; i<fromFetch->size; i++) {
320        if (fromFetch->insts[i]->threadNumber == tid &&
321            fromFetch->insts[i]->seqNum > squash_seq_num) {
322            fromFetch->insts[i]->setSquashed();
323        }
324    }
325
326    // Clear the instruction list and skid buffer in case they have any
327    // insts in them.
328    while (!insts[tid].empty()) {
329        insts[tid].pop();
330    }
331
332    while (!skidBuffer[tid].empty()) {
333        skidBuffer[tid].pop();
334    }
335
336    // Squash instructions up until this one
337    cpu->removeInstsUntil(squash_seq_num, tid);
338}
339
340template<class Impl>
341unsigned
342DefaultDecode<Impl>::squash(ThreadID tid)
343{
344    DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
345
346    if (decodeStatus[tid] == Blocked ||
347        decodeStatus[tid] == Unblocking) {
348        if (FullSystem) {
349            toFetch->decodeUnblock[tid] = 1;
350        } else {
351            // In syscall emulation, we can have both a block and a squash due
352            // to a syscall in the same cycle.  This would cause both signals
353            // to be high.  This shouldn't happen in full system.
354            // @todo: Determine if this still happens.
355            if (toFetch->decodeBlock[tid])
356                toFetch->decodeBlock[tid] = 0;
357            else
358                toFetch->decodeUnblock[tid] = 1;
359        }
360    }
361
362    // Set status to squashing.
363    decodeStatus[tid] = Squashing;
364
365    // Go through incoming instructions from fetch and squash them.
366    unsigned squash_count = 0;
367
368    for (int i=0; i<fromFetch->size; i++) {
369        if (fromFetch->insts[i]->threadNumber == tid) {
370            fromFetch->insts[i]->setSquashed();
371            squash_count++;
372        }
373    }
374
375    // Clear the instruction list and skid buffer in case they have any
376    // insts in them.
377    while (!insts[tid].empty()) {
378        insts[tid].pop();
379    }
380
381    while (!skidBuffer[tid].empty()) {
382        skidBuffer[tid].pop();
383    }
384
385    return squash_count;
386}
387
388template<class Impl>
389void
390DefaultDecode<Impl>::skidInsert(ThreadID tid)
391{
392    DynInstPtr inst = NULL;
393
394    while (!insts[tid].empty()) {
395        inst = insts[tid].front();
396
397        insts[tid].pop();
398
399        assert(tid == inst->threadNumber);
400
401        skidBuffer[tid].push(inst);
402
403        DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n",
404                inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size());
405    }
406
407    // @todo: Eventually need to enforce this by not letting a thread
408    // fetch past its skidbuffer
409    assert(skidBuffer[tid].size() <= skidBufferMax);
410}
411
412template<class Impl>
413bool
414DefaultDecode<Impl>::skidsEmpty()
415{
416    list<ThreadID>::iterator threads = activeThreads->begin();
417    list<ThreadID>::iterator end = activeThreads->end();
418
419    while (threads != end) {
420        ThreadID tid = *threads++;
421        if (!skidBuffer[tid].empty())
422            return false;
423    }
424
425    return true;
426}
427
428template<class Impl>
429void
430DefaultDecode<Impl>::updateStatus()
431{
432    bool any_unblocking = false;
433
434    list<ThreadID>::iterator threads = activeThreads->begin();
435    list<ThreadID>::iterator end = activeThreads->end();
436
437    while (threads != end) {
438        ThreadID tid = *threads++;
439
440        if (decodeStatus[tid] == Unblocking) {
441            any_unblocking = true;
442            break;
443        }
444    }
445
446    // Decode will have activity if it's unblocking.
447    if (any_unblocking) {
448        if (_status == Inactive) {
449            _status = Active;
450
451            DPRINTF(Activity, "Activating stage.\n");
452
453            cpu->activateStage(O3CPU::DecodeIdx);
454        }
455    } else {
456        // If it's not unblocking, then decode will not have any internal
457        // activity.  Switch it to inactive.
458        if (_status == Active) {
459            _status = Inactive;
460            DPRINTF(Activity, "Deactivating stage.\n");
461
462            cpu->deactivateStage(O3CPU::DecodeIdx);
463        }
464    }
465}
466
467template <class Impl>
468void
469DefaultDecode<Impl>::sortInsts()
470{
471    int insts_from_fetch = fromFetch->size;
472    for (int i = 0; i < insts_from_fetch; ++i) {
473        insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
474    }
475}
476
477template<class Impl>
478void
479DefaultDecode<Impl>::readStallSignals(ThreadID tid)
480{
481    if (fromRename->renameBlock[tid]) {
482        stalls[tid].rename = true;
483    }
484
485    if (fromRename->renameUnblock[tid]) {
486        assert(stalls[tid].rename);
487        stalls[tid].rename = false;
488    }
489}
490
491template <class Impl>
492bool
493DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
494{
495    // Check if there's a squash signal, squash if there is.
496    // Check stall signals, block if necessary.
497    // If status was blocked
498    //     Check if stall conditions have passed
499    //         if so then go to unblocking
500    // If status was Squashing
501    //     check if squashing is not high.  Switch to running this cycle.
502
503    // Update the per thread stall statuses.
504    readStallSignals(tid);
505
506    // Check squash signals from commit.
507    if (fromCommit->commitInfo[tid].squash) {
508
509        DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
510                "from commit.\n", tid);
511
512        squash(tid);
513
514        return true;
515    }
516
517    if (checkStall(tid)) {
518        return block(tid);
519    }
520
521    if (decodeStatus[tid] == Blocked) {
522        DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
523                tid);
524
525        decodeStatus[tid] = Unblocking;
526
527        unblock(tid);
528
529        return true;
530    }
531
532    if (decodeStatus[tid] == Squashing) {
533        // Switch status to running if decode isn't being told to block or
534        // squash this cycle.
535        DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
536                tid);
537
538        decodeStatus[tid] = Running;
539
540        return false;
541    }
542
543    // If we've reached this point, we have not gotten any signals that
544    // cause decode to change its status.  Decode remains the same as before.
545    return false;
546}
547
548template<class Impl>
549void
550DefaultDecode<Impl>::tick()
551{
552    wroteToTimeBuffer = false;
553
554    bool status_change = false;
555
556    toRenameIndex = 0;
557
558    list<ThreadID>::iterator threads = activeThreads->begin();
559    list<ThreadID>::iterator end = activeThreads->end();
560
561    sortInsts();
562
563    //Check stall and squash signals.
564    while (threads != end) {
565        ThreadID tid = *threads++;
566
567        DPRINTF(Decode,"Processing [tid:%i]\n",tid);
568        status_change =  checkSignalsAndUpdate(tid) || status_change;
569
570        decode(status_change, tid);
571    }
572
573    if (status_change) {
574        updateStatus();
575    }
576
577    if (wroteToTimeBuffer) {
578        DPRINTF(Activity, "Activity this cycle.\n");
579
580        cpu->activityThisCycle();
581    }
582}
583
584template<class Impl>
585void
586DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
587{
588    // If status is Running or idle,
589    //     call decodeInsts()
590    // If status is Unblocking,
591    //     buffer any instructions coming from fetch
592    //     continue trying to empty skid buffer
593    //     check if stall conditions have passed
594
595    if (decodeStatus[tid] == Blocked) {
596        ++decodeBlockedCycles;
597    } else if (decodeStatus[tid] == Squashing) {
598        ++decodeSquashCycles;
599    }
600
601    // Decode should try to decode as many instructions as its bandwidth
602    // will allow, as long as it is not currently blocked.
603    if (decodeStatus[tid] == Running ||
604        decodeStatus[tid] == Idle) {
605        DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
606                "stage.\n",tid);
607
608        decodeInsts(tid);
609    } else if (decodeStatus[tid] == Unblocking) {
610        // Make sure that the skid buffer has something in it if the
611        // status is unblocking.
612        assert(!skidsEmpty());
613
614        // If the status was unblocking, then instructions from the skid
615        // buffer were used.  Remove those instructions and handle
616        // the rest of unblocking.
617        decodeInsts(tid);
618
619        if (fetchInstsValid()) {
620            // Add the current inputs to the skid buffer so they can be
621            // reprocessed when this stage unblocks.
622            skidInsert(tid);
623        }
624
625        status_change = unblock(tid) || status_change;
626    }
627}
628
629template <class Impl>
630void
631DefaultDecode<Impl>::decodeInsts(ThreadID tid)
632{
633    // Instructions can come either from the skid buffer or the list of
634    // instructions coming from fetch, depending on decode's status.
635    int insts_available = decodeStatus[tid] == Unblocking ?
636        skidBuffer[tid].size() : insts[tid].size();
637
638    if (insts_available == 0) {
639        DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
640                " early.\n",tid);
641        // Should I change the status to idle?
642        ++decodeIdleCycles;
643        return;
644    } else if (decodeStatus[tid] == Unblocking) {
645        DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
646                "buffer.\n",tid);
647        ++decodeUnblockCycles;
648    } else if (decodeStatus[tid] == Running) {
649        ++decodeRunCycles;
650    }
651
652    DynInstPtr inst;
653
654    std::queue<DynInstPtr>
655        &insts_to_decode = decodeStatus[tid] == Unblocking ?
656        skidBuffer[tid] : insts[tid];
657
658    DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
659
660    while (insts_available > 0 && toRenameIndex < decodeWidth) {
661        assert(!insts_to_decode.empty());
662
663        inst = insts_to_decode.front();
664
665        insts_to_decode.pop();
666
667        DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
668                "PC %s\n", tid, inst->seqNum, inst->pcState());
669
670        if (inst->isSquashed()) {
671            DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
672                    "squashed, skipping.\n",
673                    tid, inst->seqNum, inst->pcState());
674
675            ++decodeSquashedInsts;
676
677            --insts_available;
678
679            continue;
680        }
681
682        // Also check if instructions have no source registers.  Mark
683        // them as ready to issue at any time.  Not sure if this check
684        // should exist here or at a later stage; however it doesn't matter
685        // too much for function correctness.
686        if (inst->numSrcRegs() == 0) {
687            inst->setCanIssue();
688        }
689
690        // This current instruction is valid, so add it into the decode
691        // queue.  The next instruction may not be valid, so check to
692        // see if branches were predicted correctly.
693        toRename->insts[toRenameIndex] = inst;
694
695        ++(toRename->size);
696        ++toRenameIndex;
697        ++decodeDecodedInsts;
698        --insts_available;
699
700#if TRACING_ON
701        if (DTRACE(O3PipeView)) {
702            inst->decodeTick = curTick() - inst->fetchTick;
703        }
704#endif
705
706        // Ensure that if it was predicted as a branch, it really is a
707        // branch.
708        if (inst->readPredTaken() && !inst->isControl()) {
709            panic("Instruction predicted as a branch!");
710
711            ++decodeControlMispred;
712
713            // Might want to set some sort of boolean and just do
714            // a check at the end
715            squash(inst, inst->threadNumber);
716
717            break;
718        }
719
720        // Go ahead and compute any PC-relative branches.
721        if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
722            ++decodeBranchResolved;
723
724            if (!(inst->branchTarget() == inst->readPredTarg())) {
725                ++decodeBranchMispred;
726
727                // Might want to set some sort of boolean and just do
728                // a check at the end
729                squash(inst, inst->threadNumber);
730                TheISA::PCState target = inst->branchTarget();
731
732                DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
733                        inst->seqNum, target);
734                //The micro pc after an instruction level branch should be 0
735                inst->setPredTarg(target);
736                break;
737            }
738        }
739    }
740
741    // If we didn't process all instructions, then we will need to block
742    // and put all those instructions into the skid buffer.
743    if (!insts_to_decode.empty()) {
744        block(tid);
745    }
746
747    // Record that decode has written to the time buffer for activity
748    // tracking.
749    if (toRenameIndex) {
750        wroteToTimeBuffer = true;
751    }
752}
753
754#endif//__CPU_O3_DECODE_IMPL_HH__
755