decode_impl.hh revision 9944
19444SAndreas.Sandberg@ARM.com/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_DECODE_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_DECODE_IMPL_HH__ 459944Smatt.horsnell@ARM.com 468230Snate@binkert.org#include "arch/types.hh" 478230Snate@binkert.org#include "base/trace.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 491717SN/A#include "cpu/o3/decode.hh" 508230Snate@binkert.org#include "cpu/inst_seq.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/Decode.hh" 539527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 546221Snate@binkert.org#include "params/DerivO3CPU.hh" 558793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 561060SN/A 578737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 588737Skoansin.tan@gmail.com// we open up the entire namespace std 598737Skoansin.tan@gmail.comusing std::list; 605529Snate@binkert.org 611060SN/Atemplate<class Impl> 625529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 634329Sktlim@umich.edu : cpu(_cpu), 644329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 652292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 662292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 672292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 682292SN/A decodeWidth(params->decodeWidth), 695529Snate@binkert.org numThreads(params->numThreads) 701060SN/A{ 719444SAndreas.Sandberg@ARM.com // @todo: Make into a parameter 729444SAndreas.Sandberg@ARM.com skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 739444SAndreas.Sandberg@ARM.com} 749444SAndreas.Sandberg@ARM.com 759444SAndreas.Sandberg@ARM.comtemplate<class Impl> 769444SAndreas.Sandberg@ARM.comvoid 779444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::startupStage() 789444SAndreas.Sandberg@ARM.com{ 799444SAndreas.Sandberg@ARM.com resetStage(); 809444SAndreas.Sandberg@ARM.com} 819444SAndreas.Sandberg@ARM.com 829444SAndreas.Sandberg@ARM.comtemplate<class Impl> 839444SAndreas.Sandberg@ARM.comvoid 849444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::resetStage() 859444SAndreas.Sandberg@ARM.com{ 862292SN/A _status = Inactive; 872292SN/A 882348SN/A // Setup status, make sure stall signals are clear. 896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 906221Snate@binkert.org decodeStatus[tid] = Idle; 912292SN/A 926221Snate@binkert.org stalls[tid].rename = false; 936221Snate@binkert.org stalls[tid].iew = false; 946221Snate@binkert.org stalls[tid].commit = false; 952292SN/A } 962292SN/A} 972292SN/A 982292SN/Atemplate <class Impl> 992292SN/Astd::string 1002292SN/ADefaultDecode<Impl>::name() const 1012292SN/A{ 1022292SN/A return cpu->name() + ".decode"; 1031060SN/A} 1041060SN/A 1051062SN/Atemplate <class Impl> 1061062SN/Avoid 1072292SN/ADefaultDecode<Impl>::regStats() 1081062SN/A{ 1091062SN/A decodeIdleCycles 1108240Snate@binkert.org .name(name() + ".IdleCycles") 1111062SN/A .desc("Number of cycles decode is idle") 1121062SN/A .prereq(decodeIdleCycles); 1131062SN/A decodeBlockedCycles 1148240Snate@binkert.org .name(name() + ".BlockedCycles") 1151062SN/A .desc("Number of cycles decode is blocked") 1161062SN/A .prereq(decodeBlockedCycles); 1172292SN/A decodeRunCycles 1188240Snate@binkert.org .name(name() + ".RunCycles") 1192292SN/A .desc("Number of cycles decode is running") 1202292SN/A .prereq(decodeRunCycles); 1211062SN/A decodeUnblockCycles 1228240Snate@binkert.org .name(name() + ".UnblockCycles") 1231062SN/A .desc("Number of cycles decode is unblocking") 1241062SN/A .prereq(decodeUnblockCycles); 1251062SN/A decodeSquashCycles 1268240Snate@binkert.org .name(name() + ".SquashCycles") 1271062SN/A .desc("Number of cycles decode is squashing") 1281062SN/A .prereq(decodeSquashCycles); 1292307SN/A decodeBranchResolved 1308240Snate@binkert.org .name(name() + ".BranchResolved") 1312307SN/A .desc("Number of times decode resolved a branch") 1322307SN/A .prereq(decodeBranchResolved); 1331062SN/A decodeBranchMispred 1348240Snate@binkert.org .name(name() + ".BranchMispred") 1351062SN/A .desc("Number of times decode detected a branch misprediction") 1361062SN/A .prereq(decodeBranchMispred); 1371062SN/A decodeControlMispred 1388240Snate@binkert.org .name(name() + ".ControlMispred") 1391062SN/A .desc("Number of times decode detected an instruction incorrectly" 1401062SN/A " predicted as a control") 1411062SN/A .prereq(decodeControlMispred); 1421062SN/A decodeDecodedInsts 1438240Snate@binkert.org .name(name() + ".DecodedInsts") 1441062SN/A .desc("Number of instructions handled by decode") 1451062SN/A .prereq(decodeDecodedInsts); 1461062SN/A decodeSquashedInsts 1478240Snate@binkert.org .name(name() + ".SquashedInsts") 1481062SN/A .desc("Number of squashed instructions handled by decode") 1491062SN/A .prereq(decodeSquashedInsts); 1501062SN/A} 1511062SN/A 1521060SN/Atemplate<class Impl> 1531060SN/Avoid 1542292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1551060SN/A{ 1561060SN/A timeBuffer = tb_ptr; 1571060SN/A 1581060SN/A // Setup wire to write information back to fetch. 1591060SN/A toFetch = timeBuffer->getWire(0); 1601060SN/A 1611060SN/A // Create wires to get information from proper places in time buffer. 1621060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1631060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1641060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1651060SN/A} 1661060SN/A 1671060SN/Atemplate<class Impl> 1681060SN/Avoid 1692292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1701060SN/A{ 1711060SN/A decodeQueue = dq_ptr; 1721060SN/A 1731060SN/A // Setup wire to write information to proper place in decode queue. 1741060SN/A toRename = decodeQueue->getWire(0); 1751060SN/A} 1761060SN/A 1771060SN/Atemplate<class Impl> 1781060SN/Avoid 1792292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1801060SN/A{ 1811060SN/A fetchQueue = fq_ptr; 1821060SN/A 1831060SN/A // Setup wire to read information from fetch queue. 1841060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1851060SN/A} 1861060SN/A 1871060SN/Atemplate<class Impl> 1882292SN/Avoid 1896221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1902292SN/A{ 1912292SN/A activeThreads = at_ptr; 1922292SN/A} 1932292SN/A 1942307SN/Atemplate <class Impl> 1959444SAndreas.Sandberg@ARM.comvoid 1969444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::drainSanityCheck() const 1972307SN/A{ 1986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1999444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 2009444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 2012307SN/A } 2022307SN/A} 2032307SN/A 2042292SN/Atemplate<class Impl> 2052292SN/Abool 2066221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 2072292SN/A{ 2082292SN/A bool ret_val = false; 2092292SN/A 2102292SN/A if (stalls[tid].rename) { 2112292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2122292SN/A ret_val = true; 2132292SN/A } else if (stalls[tid].iew) { 2142292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2152292SN/A ret_val = true; 2162292SN/A } else if (stalls[tid].commit) { 2172292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2182292SN/A ret_val = true; 2192292SN/A } 2202292SN/A 2212292SN/A return ret_val; 2222292SN/A} 2232292SN/A 2242292SN/Atemplate<class Impl> 2251681SN/Ainline bool 2262292SN/ADefaultDecode<Impl>::fetchInstsValid() 2271681SN/A{ 2281681SN/A return fromFetch->size > 0; 2291681SN/A} 2301681SN/A 2311681SN/Atemplate<class Impl> 2322292SN/Abool 2336221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2341060SN/A{ 2352292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2361060SN/A 2371060SN/A // Add the current inputs to the skid buffer so they can be 2381060SN/A // reprocessed when this stage unblocks. 2392292SN/A skidInsert(tid); 2401060SN/A 2412348SN/A // If the decode status is blocked or unblocking then decode has not yet 2422348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2432348SN/A // fetch to block. 2442292SN/A if (decodeStatus[tid] != Blocked) { 2452292SN/A // Set the status to Blocked. 2462292SN/A decodeStatus[tid] = Blocked; 2472348SN/A 2489514SAli.Saidi@ARM.com if (toFetch->decodeUnblock[tid]) { 2499514SAli.Saidi@ARM.com toFetch->decodeUnblock[tid] = false; 2509514SAli.Saidi@ARM.com } else { 2512348SN/A toFetch->decodeBlock[tid] = true; 2522348SN/A wroteToTimeBuffer = true; 2532348SN/A } 2542348SN/A 2552292SN/A return true; 2562292SN/A } 2572292SN/A 2582292SN/A return false; 2591060SN/A} 2601060SN/A 2611060SN/Atemplate<class Impl> 2622292SN/Abool 2636221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2641060SN/A{ 2652292SN/A // Decode is done unblocking only if the skid buffer is empty. 2662292SN/A if (skidBuffer[tid].empty()) { 2672292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2682292SN/A toFetch->decodeUnblock[tid] = true; 2692292SN/A wroteToTimeBuffer = true; 2701060SN/A 2712292SN/A decodeStatus[tid] = Running; 2722292SN/A return true; 2731060SN/A } 2741681SN/A 2752329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2762329SN/A 2772292SN/A return false; 2781060SN/A} 2791060SN/A 2801060SN/Atemplate<class Impl> 2811060SN/Avoid 2826221Snate@binkert.orgDefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 2831060SN/A{ 2847720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 2857720Sgblack@eecs.umich.edu "prediction detected at decode.\n", tid, inst->seqNum); 2862292SN/A 2872348SN/A // Send back mispredict information. 2882292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2892935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2908842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].mispredictInst = inst; 2916036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 2922292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2936036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2947720Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 2958503Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].squashInst = inst; 2968842Smrinmoy.ghosh@arm.com if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 2978842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].branchTaken = true; 2988842Smrinmoy.ghosh@arm.com } 2996036Sksewell@umich.edu 3003093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 3012935Sksewell@umich.edu 3022348SN/A // Might have to tell fetch to unblock. 3032292SN/A if (decodeStatus[tid] == Blocked || 3042292SN/A decodeStatus[tid] == Unblocking) { 3052292SN/A toFetch->decodeUnblock[tid] = 1; 3062292SN/A } 3072292SN/A 3081060SN/A // Set status to squashing. 3092292SN/A decodeStatus[tid] = Squashing; 3101060SN/A 3112292SN/A for (int i=0; i<fromFetch->size; i++) { 3122292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3132935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3142731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3152292SN/A } 3162292SN/A } 3172292SN/A 3182348SN/A // Clear the instruction list and skid buffer in case they have any 3192348SN/A // insts in them. 3202292SN/A while (!insts[tid].empty()) { 3212292SN/A insts[tid].pop(); 3222292SN/A } 3231060SN/A 3242292SN/A while (!skidBuffer[tid].empty()) { 3252292SN/A skidBuffer[tid].pop(); 3262292SN/A } 3272292SN/A 3282292SN/A // Squash instructions up until this one 3292935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3302292SN/A} 3312292SN/A 3322292SN/Atemplate<class Impl> 3332292SN/Aunsigned 3346221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3352292SN/A{ 3362292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3372292SN/A 3382292SN/A if (decodeStatus[tid] == Blocked || 3392292SN/A decodeStatus[tid] == Unblocking) { 3408793Sgblack@eecs.umich.edu if (FullSystem) { 3418793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3422292SN/A } else { 3438793Sgblack@eecs.umich.edu // In syscall emulation, we can have both a block and a squash due 3448793Sgblack@eecs.umich.edu // to a syscall in the same cycle. This would cause both signals 3458793Sgblack@eecs.umich.edu // to be high. This shouldn't happen in full system. 3468793Sgblack@eecs.umich.edu // @todo: Determine if this still happens. 3478793Sgblack@eecs.umich.edu if (toFetch->decodeBlock[tid]) 3488793Sgblack@eecs.umich.edu toFetch->decodeBlock[tid] = 0; 3498793Sgblack@eecs.umich.edu else 3508793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3512292SN/A } 3522292SN/A } 3532292SN/A 3542292SN/A // Set status to squashing. 3552292SN/A decodeStatus[tid] = Squashing; 3562292SN/A 3572292SN/A // Go through incoming instructions from fetch and squash them. 3582292SN/A unsigned squash_count = 0; 3592292SN/A 3602292SN/A for (int i=0; i<fromFetch->size; i++) { 3612292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3622731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3632292SN/A squash_count++; 3642292SN/A } 3652292SN/A } 3662292SN/A 3672348SN/A // Clear the instruction list and skid buffer in case they have any 3682348SN/A // insts in them. 3692292SN/A while (!insts[tid].empty()) { 3702292SN/A insts[tid].pop(); 3712292SN/A } 3722292SN/A 3732292SN/A while (!skidBuffer[tid].empty()) { 3742292SN/A skidBuffer[tid].pop(); 3752292SN/A } 3762292SN/A 3772292SN/A return squash_count; 3782292SN/A} 3792292SN/A 3802292SN/Atemplate<class Impl> 3812292SN/Avoid 3826221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 3832292SN/A{ 3842292SN/A DynInstPtr inst = NULL; 3852292SN/A 3862292SN/A while (!insts[tid].empty()) { 3872292SN/A inst = insts[tid].front(); 3882292SN/A 3892292SN/A insts[tid].pop(); 3902292SN/A 3912292SN/A assert(tid == inst->threadNumber); 3922292SN/A 3937720Sgblack@eecs.umich.edu DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 3947720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState(), inst->threadNumber); 3952292SN/A 3962292SN/A skidBuffer[tid].push(inst); 3972292SN/A } 3982292SN/A 3992329SN/A // @todo: Eventually need to enforce this by not letting a thread 4002292SN/A // fetch past its skidbuffer 4012292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4022292SN/A} 4032292SN/A 4042292SN/Atemplate<class Impl> 4052292SN/Abool 4062292SN/ADefaultDecode<Impl>::skidsEmpty() 4072292SN/A{ 4086221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4096221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4102292SN/A 4113867Sbinkertn@umich.edu while (threads != end) { 4126221Snate@binkert.org ThreadID tid = *threads++; 4133867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4142292SN/A return false; 4152292SN/A } 4162292SN/A 4172292SN/A return true; 4182292SN/A} 4192292SN/A 4202292SN/Atemplate<class Impl> 4212292SN/Avoid 4222292SN/ADefaultDecode<Impl>::updateStatus() 4232292SN/A{ 4242292SN/A bool any_unblocking = false; 4252292SN/A 4266221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4276221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4282292SN/A 4293867Sbinkertn@umich.edu while (threads != end) { 4306221Snate@binkert.org ThreadID tid = *threads++; 4312292SN/A 4322292SN/A if (decodeStatus[tid] == Unblocking) { 4332292SN/A any_unblocking = true; 4342292SN/A break; 4352292SN/A } 4362292SN/A } 4372292SN/A 4382292SN/A // Decode will have activity if it's unblocking. 4392292SN/A if (any_unblocking) { 4402292SN/A if (_status == Inactive) { 4412292SN/A _status = Active; 4422292SN/A 4432292SN/A DPRINTF(Activity, "Activating stage.\n"); 4442292SN/A 4452733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4462292SN/A } 4472292SN/A } else { 4482292SN/A // If it's not unblocking, then decode will not have any internal 4492292SN/A // activity. Switch it to inactive. 4502292SN/A if (_status == Active) { 4512292SN/A _status = Inactive; 4522292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4532292SN/A 4542733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4552292SN/A } 4562292SN/A } 4572292SN/A} 4582292SN/A 4592292SN/Atemplate <class Impl> 4602292SN/Avoid 4612292SN/ADefaultDecode<Impl>::sortInsts() 4622292SN/A{ 4632292SN/A int insts_from_fetch = fromFetch->size; 4642292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4652292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4661060SN/A } 4671060SN/A} 4681060SN/A 4691060SN/Atemplate<class Impl> 4701060SN/Avoid 4716221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4721060SN/A{ 4732292SN/A if (fromRename->renameBlock[tid]) { 4742292SN/A stalls[tid].rename = true; 4752292SN/A } 4761060SN/A 4772292SN/A if (fromRename->renameUnblock[tid]) { 4782292SN/A assert(stalls[tid].rename); 4792292SN/A stalls[tid].rename = false; 4802292SN/A } 4811060SN/A 4822292SN/A if (fromIEW->iewBlock[tid]) { 4832292SN/A stalls[tid].iew = true; 4842292SN/A } 4851062SN/A 4862292SN/A if (fromIEW->iewUnblock[tid]) { 4872292SN/A assert(stalls[tid].iew); 4882292SN/A stalls[tid].iew = false; 4892292SN/A } 4901061SN/A 4912292SN/A if (fromCommit->commitBlock[tid]) { 4922292SN/A stalls[tid].commit = true; 4932292SN/A } 4941062SN/A 4952292SN/A if (fromCommit->commitUnblock[tid]) { 4962292SN/A assert(stalls[tid].commit); 4972292SN/A stalls[tid].commit = false; 4982292SN/A } 4992292SN/A} 5001060SN/A 5012292SN/Atemplate <class Impl> 5022292SN/Abool 5036221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 5042292SN/A{ 5052292SN/A // Check if there's a squash signal, squash if there is. 5062292SN/A // Check stall signals, block if necessary. 5072292SN/A // If status was blocked 5082292SN/A // Check if stall conditions have passed 5092292SN/A // if so then go to unblocking 5102292SN/A // If status was Squashing 5112292SN/A // check if squashing is not high. Switch to running this cycle. 5121060SN/A 5132292SN/A // Update the per thread stall statuses. 5142292SN/A readStallSignals(tid); 5151060SN/A 5162292SN/A // Check squash signals from commit. 5172292SN/A if (fromCommit->commitInfo[tid].squash) { 5181681SN/A 5192292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5202292SN/A "from commit.\n", tid); 5212292SN/A 5222292SN/A squash(tid); 5232292SN/A 5242292SN/A return true; 5252292SN/A } 5262292SN/A 5272292SN/A // Check ROB squash signals from commit. 5282292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5292703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5302292SN/A 5312292SN/A // Continue to squash. 5322292SN/A decodeStatus[tid] = Squashing; 5332292SN/A 5342292SN/A return true; 5352292SN/A } 5362292SN/A 5372292SN/A if (checkStall(tid)) { 5382292SN/A return block(tid); 5392292SN/A } 5402292SN/A 5412292SN/A if (decodeStatus[tid] == Blocked) { 5422292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5432292SN/A tid); 5442292SN/A 5452292SN/A decodeStatus[tid] = Unblocking; 5462292SN/A 5472292SN/A unblock(tid); 5482292SN/A 5492292SN/A return true; 5502292SN/A } 5512292SN/A 5522292SN/A if (decodeStatus[tid] == Squashing) { 5532292SN/A // Switch status to running if decode isn't being told to block or 5542292SN/A // squash this cycle. 5552292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5562292SN/A tid); 5572292SN/A 5582292SN/A decodeStatus[tid] = Running; 5592292SN/A 5602292SN/A return false; 5612292SN/A } 5622292SN/A 5632292SN/A // If we've reached this point, we have not gotten any signals that 5642292SN/A // cause decode to change its status. Decode remains the same as before. 5652292SN/A return false; 5662292SN/A} 5672292SN/A 5682292SN/Atemplate<class Impl> 5692292SN/Avoid 5702292SN/ADefaultDecode<Impl>::tick() 5712292SN/A{ 5722292SN/A wroteToTimeBuffer = false; 5732292SN/A 5742292SN/A bool status_change = false; 5752292SN/A 5762292SN/A toRenameIndex = 0; 5772292SN/A 5786221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5796221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5802292SN/A 5812292SN/A sortInsts(); 5822292SN/A 5832292SN/A //Check stall and squash signals. 5843867Sbinkertn@umich.edu while (threads != end) { 5856221Snate@binkert.org ThreadID tid = *threads++; 5862292SN/A 5872292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5882292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5892292SN/A 5902292SN/A decode(status_change, tid); 5912292SN/A } 5922292SN/A 5932292SN/A if (status_change) { 5942292SN/A updateStatus(); 5952292SN/A } 5962292SN/A 5972292SN/A if (wroteToTimeBuffer) { 5982292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5992292SN/A 6002292SN/A cpu->activityThisCycle(); 6011060SN/A } 6021060SN/A} 6031060SN/A 6041060SN/Atemplate<class Impl> 6051060SN/Avoid 6066221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 6071060SN/A{ 6082292SN/A // If status is Running or idle, 6092292SN/A // call decodeInsts() 6102292SN/A // If status is Unblocking, 6112292SN/A // buffer any instructions coming from fetch 6122292SN/A // continue trying to empty skid buffer 6132292SN/A // check if stall conditions have passed 6142292SN/A 6152292SN/A if (decodeStatus[tid] == Blocked) { 6162292SN/A ++decodeBlockedCycles; 6172292SN/A } else if (decodeStatus[tid] == Squashing) { 6182292SN/A ++decodeSquashCycles; 6191060SN/A } 6201060SN/A 6212292SN/A // Decode should try to decode as many instructions as its bandwidth 6222292SN/A // will allow, as long as it is not currently blocked. 6232292SN/A if (decodeStatus[tid] == Running || 6242292SN/A decodeStatus[tid] == Idle) { 6252935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6262292SN/A "stage.\n",tid); 6272292SN/A 6282292SN/A decodeInsts(tid); 6292292SN/A } else if (decodeStatus[tid] == Unblocking) { 6302292SN/A // Make sure that the skid buffer has something in it if the 6312292SN/A // status is unblocking. 6322292SN/A assert(!skidsEmpty()); 6332292SN/A 6342292SN/A // If the status was unblocking, then instructions from the skid 6352292SN/A // buffer were used. Remove those instructions and handle 6362292SN/A // the rest of unblocking. 6372292SN/A decodeInsts(tid); 6382292SN/A 6392292SN/A if (fetchInstsValid()) { 6402292SN/A // Add the current inputs to the skid buffer so they can be 6412292SN/A // reprocessed when this stage unblocks. 6422292SN/A skidInsert(tid); 6432292SN/A } 6442292SN/A 6452292SN/A status_change = unblock(tid) || status_change; 6461060SN/A } 6472292SN/A} 6481060SN/A 6492292SN/Atemplate <class Impl> 6502292SN/Avoid 6516221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6522292SN/A{ 6532292SN/A // Instructions can come either from the skid buffer or the list of 6542292SN/A // instructions coming from fetch, depending on decode's status. 6552292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6562292SN/A skidBuffer[tid].size() : insts[tid].size(); 6572292SN/A 6582292SN/A if (insts_available == 0) { 6592292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6602292SN/A " early.\n",tid); 6611060SN/A // Should I change the status to idle? 6621062SN/A ++decodeIdleCycles; 6631060SN/A return; 6642292SN/A } else if (decodeStatus[tid] == Unblocking) { 6652292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6662292SN/A "buffer.\n",tid); 6672292SN/A ++decodeUnblockCycles; 6682292SN/A } else if (decodeStatus[tid] == Running) { 6692292SN/A ++decodeRunCycles; 6701060SN/A } 6711060SN/A 6721061SN/A DynInstPtr inst; 6731061SN/A 6742292SN/A std::queue<DynInstPtr> 6752292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6762292SN/A skidBuffer[tid] : insts[tid]; 6771061SN/A 6782292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6791060SN/A 6802292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6812292SN/A assert(!insts_to_decode.empty()); 6821060SN/A 6832292SN/A inst = insts_to_decode.front(); 6841062SN/A 6852292SN/A insts_to_decode.pop(); 6861061SN/A 6872292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 6887720Sgblack@eecs.umich.edu "PC %s\n", tid, inst->seqNum, inst->pcState()); 6891061SN/A 6901061SN/A if (inst->isSquashed()) { 6917720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 6921061SN/A "squashed, skipping.\n", 6937720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6941061SN/A 6951062SN/A ++decodeSquashedInsts; 6961062SN/A 6971061SN/A --insts_available; 6981061SN/A 6991061SN/A continue; 7001061SN/A } 7011060SN/A 7021681SN/A // Also check if instructions have no source registers. Mark 7031681SN/A // them as ready to issue at any time. Not sure if this check 7041681SN/A // should exist here or at a later stage; however it doesn't matter 7051681SN/A // too much for function correctness. 7061681SN/A if (inst->numSrcRegs() == 0) { 7071681SN/A inst->setCanIssue(); 7081681SN/A } 7091681SN/A 7101060SN/A // This current instruction is valid, so add it into the decode 7111060SN/A // queue. The next instruction may not be valid, so check to 7121060SN/A // see if branches were predicted correctly. 7132292SN/A toRename->insts[toRenameIndex] = inst; 7141061SN/A 7151061SN/A ++(toRename->size); 7162292SN/A ++toRenameIndex; 7172292SN/A ++decodeDecodedInsts; 7182292SN/A --insts_available; 7191060SN/A 7208471SGiacomo.Gabrielli@arm.com#if TRACING_ON 7219527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7229527SMatt.Horsnell@arm.com inst->decodeTick = curTick() - inst->fetchTick; 7239527SMatt.Horsnell@arm.com } 7248471SGiacomo.Gabrielli@arm.com#endif 7258471SGiacomo.Gabrielli@arm.com 7261060SN/A // Ensure that if it was predicted as a branch, it really is a 7271061SN/A // branch. 7283796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7291060SN/A panic("Instruction predicted as a branch!"); 7301060SN/A 7311062SN/A ++decodeControlMispred; 7322292SN/A 7331060SN/A // Might want to set some sort of boolean and just do 7341060SN/A // a check at the end 7352292SN/A squash(inst, inst->threadNumber); 7362292SN/A 7371060SN/A break; 7381060SN/A } 7391060SN/A 7401062SN/A // Go ahead and compute any PC-relative branches. 7411063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7422307SN/A ++decodeBranchResolved; 7431062SN/A 7447720Sgblack@eecs.umich.edu if (!(inst->branchTarget() == inst->readPredTarg())) { 7451062SN/A ++decodeBranchMispred; 7462292SN/A 7471060SN/A // Might want to set some sort of boolean and just do 7481060SN/A // a check at the end 7492292SN/A squash(inst, inst->threadNumber); 7507720Sgblack@eecs.umich.edu TheISA::PCState target = inst->branchTarget(); 7516036Sksewell@umich.edu 7527720Sgblack@eecs.umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 7537720Sgblack@eecs.umich.edu inst->seqNum, target); 7546036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7557720Sgblack@eecs.umich.edu inst->setPredTarg(target); 7562935Sksewell@umich.edu break; 7572935Sksewell@umich.edu } 7582935Sksewell@umich.edu } 7591060SN/A } 7601061SN/A 7612292SN/A // If we didn't process all instructions, then we will need to block 7622292SN/A // and put all those instructions into the skid buffer. 7632292SN/A if (!insts_to_decode.empty()) { 7642292SN/A block(tid); 7652292SN/A } 7662292SN/A 7672292SN/A // Record that decode has written to the time buffer for activity 7682292SN/A // tracking. 7692292SN/A if (toRenameIndex) { 7702292SN/A wroteToTimeBuffer = true; 7712292SN/A } 7721060SN/A} 7739944Smatt.horsnell@ARM.com 7749944Smatt.horsnell@ARM.com#endif//__CPU_O3_DECODE_IMPL_HH__ 775