decode_impl.hh revision 9527
19444SAndreas.Sandberg@ARM.com/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 438230Snate@binkert.org#include "arch/types.hh" 448230Snate@binkert.org#include "base/trace.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 461717SN/A#include "cpu/o3/decode.hh" 478230Snate@binkert.org#include "cpu/inst_seq.hh" 488232Snate@binkert.org#include "debug/Activity.hh" 498232Snate@binkert.org#include "debug/Decode.hh" 509527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 516221Snate@binkert.org#include "params/DerivO3CPU.hh" 528793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 531060SN/A 548737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 558737Skoansin.tan@gmail.com// we open up the entire namespace std 568737Skoansin.tan@gmail.comusing std::list; 575529Snate@binkert.org 581060SN/Atemplate<class Impl> 595529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 604329Sktlim@umich.edu : cpu(_cpu), 614329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 622292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 632292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 642292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 652292SN/A decodeWidth(params->decodeWidth), 665529Snate@binkert.org numThreads(params->numThreads) 671060SN/A{ 689444SAndreas.Sandberg@ARM.com // @todo: Make into a parameter 699444SAndreas.Sandberg@ARM.com skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 709444SAndreas.Sandberg@ARM.com} 719444SAndreas.Sandberg@ARM.com 729444SAndreas.Sandberg@ARM.comtemplate<class Impl> 739444SAndreas.Sandberg@ARM.comvoid 749444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::startupStage() 759444SAndreas.Sandberg@ARM.com{ 769444SAndreas.Sandberg@ARM.com resetStage(); 779444SAndreas.Sandberg@ARM.com} 789444SAndreas.Sandberg@ARM.com 799444SAndreas.Sandberg@ARM.comtemplate<class Impl> 809444SAndreas.Sandberg@ARM.comvoid 819444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::resetStage() 829444SAndreas.Sandberg@ARM.com{ 832292SN/A _status = Inactive; 842292SN/A 852348SN/A // Setup status, make sure stall signals are clear. 866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 876221Snate@binkert.org decodeStatus[tid] = Idle; 882292SN/A 896221Snate@binkert.org stalls[tid].rename = false; 906221Snate@binkert.org stalls[tid].iew = false; 916221Snate@binkert.org stalls[tid].commit = false; 922292SN/A } 932292SN/A} 942292SN/A 952292SN/Atemplate <class Impl> 962292SN/Astd::string 972292SN/ADefaultDecode<Impl>::name() const 982292SN/A{ 992292SN/A return cpu->name() + ".decode"; 1001060SN/A} 1011060SN/A 1021062SN/Atemplate <class Impl> 1031062SN/Avoid 1042292SN/ADefaultDecode<Impl>::regStats() 1051062SN/A{ 1061062SN/A decodeIdleCycles 1078240Snate@binkert.org .name(name() + ".IdleCycles") 1081062SN/A .desc("Number of cycles decode is idle") 1091062SN/A .prereq(decodeIdleCycles); 1101062SN/A decodeBlockedCycles 1118240Snate@binkert.org .name(name() + ".BlockedCycles") 1121062SN/A .desc("Number of cycles decode is blocked") 1131062SN/A .prereq(decodeBlockedCycles); 1142292SN/A decodeRunCycles 1158240Snate@binkert.org .name(name() + ".RunCycles") 1162292SN/A .desc("Number of cycles decode is running") 1172292SN/A .prereq(decodeRunCycles); 1181062SN/A decodeUnblockCycles 1198240Snate@binkert.org .name(name() + ".UnblockCycles") 1201062SN/A .desc("Number of cycles decode is unblocking") 1211062SN/A .prereq(decodeUnblockCycles); 1221062SN/A decodeSquashCycles 1238240Snate@binkert.org .name(name() + ".SquashCycles") 1241062SN/A .desc("Number of cycles decode is squashing") 1251062SN/A .prereq(decodeSquashCycles); 1262307SN/A decodeBranchResolved 1278240Snate@binkert.org .name(name() + ".BranchResolved") 1282307SN/A .desc("Number of times decode resolved a branch") 1292307SN/A .prereq(decodeBranchResolved); 1301062SN/A decodeBranchMispred 1318240Snate@binkert.org .name(name() + ".BranchMispred") 1321062SN/A .desc("Number of times decode detected a branch misprediction") 1331062SN/A .prereq(decodeBranchMispred); 1341062SN/A decodeControlMispred 1358240Snate@binkert.org .name(name() + ".ControlMispred") 1361062SN/A .desc("Number of times decode detected an instruction incorrectly" 1371062SN/A " predicted as a control") 1381062SN/A .prereq(decodeControlMispred); 1391062SN/A decodeDecodedInsts 1408240Snate@binkert.org .name(name() + ".DecodedInsts") 1411062SN/A .desc("Number of instructions handled by decode") 1421062SN/A .prereq(decodeDecodedInsts); 1431062SN/A decodeSquashedInsts 1448240Snate@binkert.org .name(name() + ".SquashedInsts") 1451062SN/A .desc("Number of squashed instructions handled by decode") 1461062SN/A .prereq(decodeSquashedInsts); 1471062SN/A} 1481062SN/A 1491060SN/Atemplate<class Impl> 1501060SN/Avoid 1512292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1521060SN/A{ 1531060SN/A timeBuffer = tb_ptr; 1541060SN/A 1551060SN/A // Setup wire to write information back to fetch. 1561060SN/A toFetch = timeBuffer->getWire(0); 1571060SN/A 1581060SN/A // Create wires to get information from proper places in time buffer. 1591060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1601060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1611060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1621060SN/A} 1631060SN/A 1641060SN/Atemplate<class Impl> 1651060SN/Avoid 1662292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1671060SN/A{ 1681060SN/A decodeQueue = dq_ptr; 1691060SN/A 1701060SN/A // Setup wire to write information to proper place in decode queue. 1711060SN/A toRename = decodeQueue->getWire(0); 1721060SN/A} 1731060SN/A 1741060SN/Atemplate<class Impl> 1751060SN/Avoid 1762292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1771060SN/A{ 1781060SN/A fetchQueue = fq_ptr; 1791060SN/A 1801060SN/A // Setup wire to read information from fetch queue. 1811060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1821060SN/A} 1831060SN/A 1841060SN/Atemplate<class Impl> 1852292SN/Avoid 1866221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1872292SN/A{ 1882292SN/A activeThreads = at_ptr; 1892292SN/A} 1902292SN/A 1912307SN/Atemplate <class Impl> 1929444SAndreas.Sandberg@ARM.comvoid 1939444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::drainSanityCheck() const 1942307SN/A{ 1956221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1969444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 1979444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 1982307SN/A } 1992307SN/A} 2002307SN/A 2012292SN/Atemplate<class Impl> 2022292SN/Abool 2036221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 2042292SN/A{ 2052292SN/A bool ret_val = false; 2062292SN/A 2072292SN/A if (stalls[tid].rename) { 2082292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2092292SN/A ret_val = true; 2102292SN/A } else if (stalls[tid].iew) { 2112292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2122292SN/A ret_val = true; 2132292SN/A } else if (stalls[tid].commit) { 2142292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2152292SN/A ret_val = true; 2162292SN/A } 2172292SN/A 2182292SN/A return ret_val; 2192292SN/A} 2202292SN/A 2212292SN/Atemplate<class Impl> 2221681SN/Ainline bool 2232292SN/ADefaultDecode<Impl>::fetchInstsValid() 2241681SN/A{ 2251681SN/A return fromFetch->size > 0; 2261681SN/A} 2271681SN/A 2281681SN/Atemplate<class Impl> 2292292SN/Abool 2306221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2311060SN/A{ 2322292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2331060SN/A 2341060SN/A // Add the current inputs to the skid buffer so they can be 2351060SN/A // reprocessed when this stage unblocks. 2362292SN/A skidInsert(tid); 2371060SN/A 2382348SN/A // If the decode status is blocked or unblocking then decode has not yet 2392348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2402348SN/A // fetch to block. 2412292SN/A if (decodeStatus[tid] != Blocked) { 2422292SN/A // Set the status to Blocked. 2432292SN/A decodeStatus[tid] = Blocked; 2442348SN/A 2459514SAli.Saidi@ARM.com if (toFetch->decodeUnblock[tid]) { 2469514SAli.Saidi@ARM.com toFetch->decodeUnblock[tid] = false; 2479514SAli.Saidi@ARM.com } else { 2482348SN/A toFetch->decodeBlock[tid] = true; 2492348SN/A wroteToTimeBuffer = true; 2502348SN/A } 2512348SN/A 2522292SN/A return true; 2532292SN/A } 2542292SN/A 2552292SN/A return false; 2561060SN/A} 2571060SN/A 2581060SN/Atemplate<class Impl> 2592292SN/Abool 2606221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2611060SN/A{ 2622292SN/A // Decode is done unblocking only if the skid buffer is empty. 2632292SN/A if (skidBuffer[tid].empty()) { 2642292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2652292SN/A toFetch->decodeUnblock[tid] = true; 2662292SN/A wroteToTimeBuffer = true; 2671060SN/A 2682292SN/A decodeStatus[tid] = Running; 2692292SN/A return true; 2701060SN/A } 2711681SN/A 2722329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2732329SN/A 2742292SN/A return false; 2751060SN/A} 2761060SN/A 2771060SN/Atemplate<class Impl> 2781060SN/Avoid 2796221Snate@binkert.orgDefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 2801060SN/A{ 2817720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 2827720Sgblack@eecs.umich.edu "prediction detected at decode.\n", tid, inst->seqNum); 2832292SN/A 2842348SN/A // Send back mispredict information. 2852292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2862935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2878842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].mispredictInst = inst; 2886036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 2892292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2906036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2917720Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 2928503Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].squashInst = inst; 2938842Smrinmoy.ghosh@arm.com if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 2948842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].branchTaken = true; 2958842Smrinmoy.ghosh@arm.com } 2966036Sksewell@umich.edu 2973093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 2982935Sksewell@umich.edu 2992348SN/A // Might have to tell fetch to unblock. 3002292SN/A if (decodeStatus[tid] == Blocked || 3012292SN/A decodeStatus[tid] == Unblocking) { 3022292SN/A toFetch->decodeUnblock[tid] = 1; 3032292SN/A } 3042292SN/A 3051060SN/A // Set status to squashing. 3062292SN/A decodeStatus[tid] = Squashing; 3071060SN/A 3082292SN/A for (int i=0; i<fromFetch->size; i++) { 3092292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3102935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3112731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3122292SN/A } 3132292SN/A } 3142292SN/A 3152348SN/A // Clear the instruction list and skid buffer in case they have any 3162348SN/A // insts in them. 3172292SN/A while (!insts[tid].empty()) { 3182292SN/A insts[tid].pop(); 3192292SN/A } 3201060SN/A 3212292SN/A while (!skidBuffer[tid].empty()) { 3222292SN/A skidBuffer[tid].pop(); 3232292SN/A } 3242292SN/A 3252292SN/A // Squash instructions up until this one 3262935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3272292SN/A} 3282292SN/A 3292292SN/Atemplate<class Impl> 3302292SN/Aunsigned 3316221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3322292SN/A{ 3332292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3342292SN/A 3352292SN/A if (decodeStatus[tid] == Blocked || 3362292SN/A decodeStatus[tid] == Unblocking) { 3378793Sgblack@eecs.umich.edu if (FullSystem) { 3388793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3392292SN/A } else { 3408793Sgblack@eecs.umich.edu // In syscall emulation, we can have both a block and a squash due 3418793Sgblack@eecs.umich.edu // to a syscall in the same cycle. This would cause both signals 3428793Sgblack@eecs.umich.edu // to be high. This shouldn't happen in full system. 3438793Sgblack@eecs.umich.edu // @todo: Determine if this still happens. 3448793Sgblack@eecs.umich.edu if (toFetch->decodeBlock[tid]) 3458793Sgblack@eecs.umich.edu toFetch->decodeBlock[tid] = 0; 3468793Sgblack@eecs.umich.edu else 3478793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3482292SN/A } 3492292SN/A } 3502292SN/A 3512292SN/A // Set status to squashing. 3522292SN/A decodeStatus[tid] = Squashing; 3532292SN/A 3542292SN/A // Go through incoming instructions from fetch and squash them. 3552292SN/A unsigned squash_count = 0; 3562292SN/A 3572292SN/A for (int i=0; i<fromFetch->size; i++) { 3582292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3592731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3602292SN/A squash_count++; 3612292SN/A } 3622292SN/A } 3632292SN/A 3642348SN/A // Clear the instruction list and skid buffer in case they have any 3652348SN/A // insts in them. 3662292SN/A while (!insts[tid].empty()) { 3672292SN/A insts[tid].pop(); 3682292SN/A } 3692292SN/A 3702292SN/A while (!skidBuffer[tid].empty()) { 3712292SN/A skidBuffer[tid].pop(); 3722292SN/A } 3732292SN/A 3742292SN/A return squash_count; 3752292SN/A} 3762292SN/A 3772292SN/Atemplate<class Impl> 3782292SN/Avoid 3796221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 3802292SN/A{ 3812292SN/A DynInstPtr inst = NULL; 3822292SN/A 3832292SN/A while (!insts[tid].empty()) { 3842292SN/A inst = insts[tid].front(); 3852292SN/A 3862292SN/A insts[tid].pop(); 3872292SN/A 3882292SN/A assert(tid == inst->threadNumber); 3892292SN/A 3907720Sgblack@eecs.umich.edu DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 3917720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState(), inst->threadNumber); 3922292SN/A 3932292SN/A skidBuffer[tid].push(inst); 3942292SN/A } 3952292SN/A 3962329SN/A // @todo: Eventually need to enforce this by not letting a thread 3972292SN/A // fetch past its skidbuffer 3982292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 3992292SN/A} 4002292SN/A 4012292SN/Atemplate<class Impl> 4022292SN/Abool 4032292SN/ADefaultDecode<Impl>::skidsEmpty() 4042292SN/A{ 4056221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4066221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4072292SN/A 4083867Sbinkertn@umich.edu while (threads != end) { 4096221Snate@binkert.org ThreadID tid = *threads++; 4103867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4112292SN/A return false; 4122292SN/A } 4132292SN/A 4142292SN/A return true; 4152292SN/A} 4162292SN/A 4172292SN/Atemplate<class Impl> 4182292SN/Avoid 4192292SN/ADefaultDecode<Impl>::updateStatus() 4202292SN/A{ 4212292SN/A bool any_unblocking = false; 4222292SN/A 4236221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4246221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4252292SN/A 4263867Sbinkertn@umich.edu while (threads != end) { 4276221Snate@binkert.org ThreadID tid = *threads++; 4282292SN/A 4292292SN/A if (decodeStatus[tid] == Unblocking) { 4302292SN/A any_unblocking = true; 4312292SN/A break; 4322292SN/A } 4332292SN/A } 4342292SN/A 4352292SN/A // Decode will have activity if it's unblocking. 4362292SN/A if (any_unblocking) { 4372292SN/A if (_status == Inactive) { 4382292SN/A _status = Active; 4392292SN/A 4402292SN/A DPRINTF(Activity, "Activating stage.\n"); 4412292SN/A 4422733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4432292SN/A } 4442292SN/A } else { 4452292SN/A // If it's not unblocking, then decode will not have any internal 4462292SN/A // activity. Switch it to inactive. 4472292SN/A if (_status == Active) { 4482292SN/A _status = Inactive; 4492292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4502292SN/A 4512733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4522292SN/A } 4532292SN/A } 4542292SN/A} 4552292SN/A 4562292SN/Atemplate <class Impl> 4572292SN/Avoid 4582292SN/ADefaultDecode<Impl>::sortInsts() 4592292SN/A{ 4602292SN/A int insts_from_fetch = fromFetch->size; 4612292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4622292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4631060SN/A } 4641060SN/A} 4651060SN/A 4661060SN/Atemplate<class Impl> 4671060SN/Avoid 4686221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4691060SN/A{ 4702292SN/A if (fromRename->renameBlock[tid]) { 4712292SN/A stalls[tid].rename = true; 4722292SN/A } 4731060SN/A 4742292SN/A if (fromRename->renameUnblock[tid]) { 4752292SN/A assert(stalls[tid].rename); 4762292SN/A stalls[tid].rename = false; 4772292SN/A } 4781060SN/A 4792292SN/A if (fromIEW->iewBlock[tid]) { 4802292SN/A stalls[tid].iew = true; 4812292SN/A } 4821062SN/A 4832292SN/A if (fromIEW->iewUnblock[tid]) { 4842292SN/A assert(stalls[tid].iew); 4852292SN/A stalls[tid].iew = false; 4862292SN/A } 4871061SN/A 4882292SN/A if (fromCommit->commitBlock[tid]) { 4892292SN/A stalls[tid].commit = true; 4902292SN/A } 4911062SN/A 4922292SN/A if (fromCommit->commitUnblock[tid]) { 4932292SN/A assert(stalls[tid].commit); 4942292SN/A stalls[tid].commit = false; 4952292SN/A } 4962292SN/A} 4971060SN/A 4982292SN/Atemplate <class Impl> 4992292SN/Abool 5006221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 5012292SN/A{ 5022292SN/A // Check if there's a squash signal, squash if there is. 5032292SN/A // Check stall signals, block if necessary. 5042292SN/A // If status was blocked 5052292SN/A // Check if stall conditions have passed 5062292SN/A // if so then go to unblocking 5072292SN/A // If status was Squashing 5082292SN/A // check if squashing is not high. Switch to running this cycle. 5091060SN/A 5102292SN/A // Update the per thread stall statuses. 5112292SN/A readStallSignals(tid); 5121060SN/A 5132292SN/A // Check squash signals from commit. 5142292SN/A if (fromCommit->commitInfo[tid].squash) { 5151681SN/A 5162292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5172292SN/A "from commit.\n", tid); 5182292SN/A 5192292SN/A squash(tid); 5202292SN/A 5212292SN/A return true; 5222292SN/A } 5232292SN/A 5242292SN/A // Check ROB squash signals from commit. 5252292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5262703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5272292SN/A 5282292SN/A // Continue to squash. 5292292SN/A decodeStatus[tid] = Squashing; 5302292SN/A 5312292SN/A return true; 5322292SN/A } 5332292SN/A 5342292SN/A if (checkStall(tid)) { 5352292SN/A return block(tid); 5362292SN/A } 5372292SN/A 5382292SN/A if (decodeStatus[tid] == Blocked) { 5392292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5402292SN/A tid); 5412292SN/A 5422292SN/A decodeStatus[tid] = Unblocking; 5432292SN/A 5442292SN/A unblock(tid); 5452292SN/A 5462292SN/A return true; 5472292SN/A } 5482292SN/A 5492292SN/A if (decodeStatus[tid] == Squashing) { 5502292SN/A // Switch status to running if decode isn't being told to block or 5512292SN/A // squash this cycle. 5522292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5532292SN/A tid); 5542292SN/A 5552292SN/A decodeStatus[tid] = Running; 5562292SN/A 5572292SN/A return false; 5582292SN/A } 5592292SN/A 5602292SN/A // If we've reached this point, we have not gotten any signals that 5612292SN/A // cause decode to change its status. Decode remains the same as before. 5622292SN/A return false; 5632292SN/A} 5642292SN/A 5652292SN/Atemplate<class Impl> 5662292SN/Avoid 5672292SN/ADefaultDecode<Impl>::tick() 5682292SN/A{ 5692292SN/A wroteToTimeBuffer = false; 5702292SN/A 5712292SN/A bool status_change = false; 5722292SN/A 5732292SN/A toRenameIndex = 0; 5742292SN/A 5756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5772292SN/A 5782292SN/A sortInsts(); 5792292SN/A 5802292SN/A //Check stall and squash signals. 5813867Sbinkertn@umich.edu while (threads != end) { 5826221Snate@binkert.org ThreadID tid = *threads++; 5832292SN/A 5842292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5852292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5862292SN/A 5872292SN/A decode(status_change, tid); 5882292SN/A } 5892292SN/A 5902292SN/A if (status_change) { 5912292SN/A updateStatus(); 5922292SN/A } 5932292SN/A 5942292SN/A if (wroteToTimeBuffer) { 5952292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5962292SN/A 5972292SN/A cpu->activityThisCycle(); 5981060SN/A } 5991060SN/A} 6001060SN/A 6011060SN/Atemplate<class Impl> 6021060SN/Avoid 6036221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 6041060SN/A{ 6052292SN/A // If status is Running or idle, 6062292SN/A // call decodeInsts() 6072292SN/A // If status is Unblocking, 6082292SN/A // buffer any instructions coming from fetch 6092292SN/A // continue trying to empty skid buffer 6102292SN/A // check if stall conditions have passed 6112292SN/A 6122292SN/A if (decodeStatus[tid] == Blocked) { 6132292SN/A ++decodeBlockedCycles; 6142292SN/A } else if (decodeStatus[tid] == Squashing) { 6152292SN/A ++decodeSquashCycles; 6161060SN/A } 6171060SN/A 6182292SN/A // Decode should try to decode as many instructions as its bandwidth 6192292SN/A // will allow, as long as it is not currently blocked. 6202292SN/A if (decodeStatus[tid] == Running || 6212292SN/A decodeStatus[tid] == Idle) { 6222935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6232292SN/A "stage.\n",tid); 6242292SN/A 6252292SN/A decodeInsts(tid); 6262292SN/A } else if (decodeStatus[tid] == Unblocking) { 6272292SN/A // Make sure that the skid buffer has something in it if the 6282292SN/A // status is unblocking. 6292292SN/A assert(!skidsEmpty()); 6302292SN/A 6312292SN/A // If the status was unblocking, then instructions from the skid 6322292SN/A // buffer were used. Remove those instructions and handle 6332292SN/A // the rest of unblocking. 6342292SN/A decodeInsts(tid); 6352292SN/A 6362292SN/A if (fetchInstsValid()) { 6372292SN/A // Add the current inputs to the skid buffer so they can be 6382292SN/A // reprocessed when this stage unblocks. 6392292SN/A skidInsert(tid); 6402292SN/A } 6412292SN/A 6422292SN/A status_change = unblock(tid) || status_change; 6431060SN/A } 6442292SN/A} 6451060SN/A 6462292SN/Atemplate <class Impl> 6472292SN/Avoid 6486221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6492292SN/A{ 6502292SN/A // Instructions can come either from the skid buffer or the list of 6512292SN/A // instructions coming from fetch, depending on decode's status. 6522292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6532292SN/A skidBuffer[tid].size() : insts[tid].size(); 6542292SN/A 6552292SN/A if (insts_available == 0) { 6562292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6572292SN/A " early.\n",tid); 6581060SN/A // Should I change the status to idle? 6591062SN/A ++decodeIdleCycles; 6601060SN/A return; 6612292SN/A } else if (decodeStatus[tid] == Unblocking) { 6622292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6632292SN/A "buffer.\n",tid); 6642292SN/A ++decodeUnblockCycles; 6652292SN/A } else if (decodeStatus[tid] == Running) { 6662292SN/A ++decodeRunCycles; 6671060SN/A } 6681060SN/A 6691061SN/A DynInstPtr inst; 6701061SN/A 6712292SN/A std::queue<DynInstPtr> 6722292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6732292SN/A skidBuffer[tid] : insts[tid]; 6741061SN/A 6752292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6761060SN/A 6772292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6782292SN/A assert(!insts_to_decode.empty()); 6791060SN/A 6802292SN/A inst = insts_to_decode.front(); 6811062SN/A 6822292SN/A insts_to_decode.pop(); 6831061SN/A 6842292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 6857720Sgblack@eecs.umich.edu "PC %s\n", tid, inst->seqNum, inst->pcState()); 6861061SN/A 6871061SN/A if (inst->isSquashed()) { 6887720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 6891061SN/A "squashed, skipping.\n", 6907720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6911061SN/A 6921062SN/A ++decodeSquashedInsts; 6931062SN/A 6941061SN/A --insts_available; 6951061SN/A 6961061SN/A continue; 6971061SN/A } 6981060SN/A 6991681SN/A // Also check if instructions have no source registers. Mark 7001681SN/A // them as ready to issue at any time. Not sure if this check 7011681SN/A // should exist here or at a later stage; however it doesn't matter 7021681SN/A // too much for function correctness. 7031681SN/A if (inst->numSrcRegs() == 0) { 7041681SN/A inst->setCanIssue(); 7051681SN/A } 7061681SN/A 7071060SN/A // This current instruction is valid, so add it into the decode 7081060SN/A // queue. The next instruction may not be valid, so check to 7091060SN/A // see if branches were predicted correctly. 7102292SN/A toRename->insts[toRenameIndex] = inst; 7111061SN/A 7121061SN/A ++(toRename->size); 7132292SN/A ++toRenameIndex; 7142292SN/A ++decodeDecodedInsts; 7152292SN/A --insts_available; 7161060SN/A 7178471SGiacomo.Gabrielli@arm.com#if TRACING_ON 7189527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7199527SMatt.Horsnell@arm.com inst->decodeTick = curTick() - inst->fetchTick; 7209527SMatt.Horsnell@arm.com } 7218471SGiacomo.Gabrielli@arm.com#endif 7228471SGiacomo.Gabrielli@arm.com 7231060SN/A // Ensure that if it was predicted as a branch, it really is a 7241061SN/A // branch. 7253796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7261060SN/A panic("Instruction predicted as a branch!"); 7271060SN/A 7281062SN/A ++decodeControlMispred; 7292292SN/A 7301060SN/A // Might want to set some sort of boolean and just do 7311060SN/A // a check at the end 7322292SN/A squash(inst, inst->threadNumber); 7332292SN/A 7341060SN/A break; 7351060SN/A } 7361060SN/A 7371062SN/A // Go ahead and compute any PC-relative branches. 7381063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7392307SN/A ++decodeBranchResolved; 7401062SN/A 7417720Sgblack@eecs.umich.edu if (!(inst->branchTarget() == inst->readPredTarg())) { 7421062SN/A ++decodeBranchMispred; 7432292SN/A 7441060SN/A // Might want to set some sort of boolean and just do 7451060SN/A // a check at the end 7462292SN/A squash(inst, inst->threadNumber); 7477720Sgblack@eecs.umich.edu TheISA::PCState target = inst->branchTarget(); 7486036Sksewell@umich.edu 7497720Sgblack@eecs.umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 7507720Sgblack@eecs.umich.edu inst->seqNum, target); 7516036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7527720Sgblack@eecs.umich.edu inst->setPredTarg(target); 7532935Sksewell@umich.edu break; 7542935Sksewell@umich.edu } 7552935Sksewell@umich.edu } 7561060SN/A } 7571061SN/A 7582292SN/A // If we didn't process all instructions, then we will need to block 7592292SN/A // and put all those instructions into the skid buffer. 7602292SN/A if (!insts_to_decode.empty()) { 7612292SN/A block(tid); 7622292SN/A } 7632292SN/A 7642292SN/A // Record that decode has written to the time buffer for activity 7652292SN/A // tracking. 7662292SN/A if (toRenameIndex) { 7672292SN/A wroteToTimeBuffer = true; 7682292SN/A } 7691060SN/A} 770