decode_impl.hh revision 8503
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 318230Snate@binkert.org#include "arch/types.hh" 328230Snate@binkert.org#include "base/trace.hh" 338230Snate@binkert.org#include "config/full_system.hh" 346658Snate@binkert.org#include "config/the_isa.hh" 351717SN/A#include "cpu/o3/decode.hh" 368230Snate@binkert.org#include "cpu/inst_seq.hh" 378232Snate@binkert.org#include "debug/Activity.hh" 388232Snate@binkert.org#include "debug/Decode.hh" 396221Snate@binkert.org#include "params/DerivO3CPU.hh" 401060SN/A 416221Snate@binkert.orgusing namespace std; 425529Snate@binkert.org 431060SN/Atemplate<class Impl> 445529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 454329Sktlim@umich.edu : cpu(_cpu), 464329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 472292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 482292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 492292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 502292SN/A decodeWidth(params->decodeWidth), 515529Snate@binkert.org numThreads(params->numThreads) 521060SN/A{ 532292SN/A _status = Inactive; 542292SN/A 552348SN/A // Setup status, make sure stall signals are clear. 566221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 576221Snate@binkert.org decodeStatus[tid] = Idle; 582292SN/A 596221Snate@binkert.org stalls[tid].rename = false; 606221Snate@binkert.org stalls[tid].iew = false; 616221Snate@binkert.org stalls[tid].commit = false; 622292SN/A } 632292SN/A 642292SN/A // @todo: Make into a parameter 652292SN/A skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 662292SN/A} 672292SN/A 682292SN/Atemplate <class Impl> 692292SN/Astd::string 702292SN/ADefaultDecode<Impl>::name() const 712292SN/A{ 722292SN/A return cpu->name() + ".decode"; 731060SN/A} 741060SN/A 751062SN/Atemplate <class Impl> 761062SN/Avoid 772292SN/ADefaultDecode<Impl>::regStats() 781062SN/A{ 791062SN/A decodeIdleCycles 808240Snate@binkert.org .name(name() + ".IdleCycles") 811062SN/A .desc("Number of cycles decode is idle") 821062SN/A .prereq(decodeIdleCycles); 831062SN/A decodeBlockedCycles 848240Snate@binkert.org .name(name() + ".BlockedCycles") 851062SN/A .desc("Number of cycles decode is blocked") 861062SN/A .prereq(decodeBlockedCycles); 872292SN/A decodeRunCycles 888240Snate@binkert.org .name(name() + ".RunCycles") 892292SN/A .desc("Number of cycles decode is running") 902292SN/A .prereq(decodeRunCycles); 911062SN/A decodeUnblockCycles 928240Snate@binkert.org .name(name() + ".UnblockCycles") 931062SN/A .desc("Number of cycles decode is unblocking") 941062SN/A .prereq(decodeUnblockCycles); 951062SN/A decodeSquashCycles 968240Snate@binkert.org .name(name() + ".SquashCycles") 971062SN/A .desc("Number of cycles decode is squashing") 981062SN/A .prereq(decodeSquashCycles); 992307SN/A decodeBranchResolved 1008240Snate@binkert.org .name(name() + ".BranchResolved") 1012307SN/A .desc("Number of times decode resolved a branch") 1022307SN/A .prereq(decodeBranchResolved); 1031062SN/A decodeBranchMispred 1048240Snate@binkert.org .name(name() + ".BranchMispred") 1051062SN/A .desc("Number of times decode detected a branch misprediction") 1061062SN/A .prereq(decodeBranchMispred); 1071062SN/A decodeControlMispred 1088240Snate@binkert.org .name(name() + ".ControlMispred") 1091062SN/A .desc("Number of times decode detected an instruction incorrectly" 1101062SN/A " predicted as a control") 1111062SN/A .prereq(decodeControlMispred); 1121062SN/A decodeDecodedInsts 1138240Snate@binkert.org .name(name() + ".DecodedInsts") 1141062SN/A .desc("Number of instructions handled by decode") 1151062SN/A .prereq(decodeDecodedInsts); 1161062SN/A decodeSquashedInsts 1178240Snate@binkert.org .name(name() + ".SquashedInsts") 1181062SN/A .desc("Number of squashed instructions handled by decode") 1191062SN/A .prereq(decodeSquashedInsts); 1201062SN/A} 1211062SN/A 1221060SN/Atemplate<class Impl> 1231060SN/Avoid 1242292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1251060SN/A{ 1261060SN/A timeBuffer = tb_ptr; 1271060SN/A 1281060SN/A // Setup wire to write information back to fetch. 1291060SN/A toFetch = timeBuffer->getWire(0); 1301060SN/A 1311060SN/A // Create wires to get information from proper places in time buffer. 1321060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1331060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1341060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1351060SN/A} 1361060SN/A 1371060SN/Atemplate<class Impl> 1381060SN/Avoid 1392292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1401060SN/A{ 1411060SN/A decodeQueue = dq_ptr; 1421060SN/A 1431060SN/A // Setup wire to write information to proper place in decode queue. 1441060SN/A toRename = decodeQueue->getWire(0); 1451060SN/A} 1461060SN/A 1471060SN/Atemplate<class Impl> 1481060SN/Avoid 1492292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1501060SN/A{ 1511060SN/A fetchQueue = fq_ptr; 1521060SN/A 1531060SN/A // Setup wire to read information from fetch queue. 1541060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1551060SN/A} 1561060SN/A 1571060SN/Atemplate<class Impl> 1582292SN/Avoid 1596221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1602292SN/A{ 1612292SN/A activeThreads = at_ptr; 1622292SN/A} 1632292SN/A 1642307SN/Atemplate <class Impl> 1652863Sktlim@umich.edubool 1662843Sktlim@umich.eduDefaultDecode<Impl>::drain() 1672307SN/A{ 1682843Sktlim@umich.edu // Decode is done draining at any time. 1692843Sktlim@umich.edu cpu->signalDrained(); 1702863Sktlim@umich.edu return true; 1712307SN/A} 1722307SN/A 1732307SN/Atemplate <class Impl> 1742307SN/Avoid 1752307SN/ADefaultDecode<Impl>::takeOverFrom() 1762307SN/A{ 1772307SN/A _status = Inactive; 1782307SN/A 1792348SN/A // Be sure to reset state and clear out any old instructions. 1806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1816221Snate@binkert.org decodeStatus[tid] = Idle; 1822307SN/A 1836221Snate@binkert.org stalls[tid].rename = false; 1846221Snate@binkert.org stalls[tid].iew = false; 1856221Snate@binkert.org stalls[tid].commit = false; 1866221Snate@binkert.org while (!insts[tid].empty()) 1876221Snate@binkert.org insts[tid].pop(); 1886221Snate@binkert.org while (!skidBuffer[tid].empty()) 1896221Snate@binkert.org skidBuffer[tid].pop(); 1906221Snate@binkert.org branchCount[tid] = 0; 1912307SN/A } 1922307SN/A wroteToTimeBuffer = false; 1932307SN/A} 1942307SN/A 1952292SN/Atemplate<class Impl> 1962292SN/Abool 1976221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 1982292SN/A{ 1992292SN/A bool ret_val = false; 2002292SN/A 2012292SN/A if (stalls[tid].rename) { 2022292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2032292SN/A ret_val = true; 2042292SN/A } else if (stalls[tid].iew) { 2052292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2062292SN/A ret_val = true; 2072292SN/A } else if (stalls[tid].commit) { 2082292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2092292SN/A ret_val = true; 2102292SN/A } 2112292SN/A 2122292SN/A return ret_val; 2132292SN/A} 2142292SN/A 2152292SN/Atemplate<class Impl> 2161681SN/Ainline bool 2172292SN/ADefaultDecode<Impl>::fetchInstsValid() 2181681SN/A{ 2191681SN/A return fromFetch->size > 0; 2201681SN/A} 2211681SN/A 2221681SN/Atemplate<class Impl> 2232292SN/Abool 2246221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2251060SN/A{ 2262292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2271060SN/A 2281060SN/A // Add the current inputs to the skid buffer so they can be 2291060SN/A // reprocessed when this stage unblocks. 2302292SN/A skidInsert(tid); 2311060SN/A 2322348SN/A // If the decode status is blocked or unblocking then decode has not yet 2332348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2342348SN/A // fetch to block. 2352292SN/A if (decodeStatus[tid] != Blocked) { 2362292SN/A // Set the status to Blocked. 2372292SN/A decodeStatus[tid] = Blocked; 2382348SN/A 2392348SN/A if (decodeStatus[tid] != Unblocking) { 2402348SN/A toFetch->decodeBlock[tid] = true; 2412348SN/A wroteToTimeBuffer = true; 2422348SN/A } 2432348SN/A 2442292SN/A return true; 2452292SN/A } 2462292SN/A 2472292SN/A return false; 2481060SN/A} 2491060SN/A 2501060SN/Atemplate<class Impl> 2512292SN/Abool 2526221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2531060SN/A{ 2542292SN/A // Decode is done unblocking only if the skid buffer is empty. 2552292SN/A if (skidBuffer[tid].empty()) { 2562292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2572292SN/A toFetch->decodeUnblock[tid] = true; 2582292SN/A wroteToTimeBuffer = true; 2591060SN/A 2602292SN/A decodeStatus[tid] = Running; 2612292SN/A return true; 2621060SN/A } 2631681SN/A 2642329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2652329SN/A 2662292SN/A return false; 2671060SN/A} 2681060SN/A 2691060SN/Atemplate<class Impl> 2701060SN/Avoid 2716221Snate@binkert.orgDefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 2721060SN/A{ 2737720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 2747720Sgblack@eecs.umich.edu "prediction detected at decode.\n", tid, inst->seqNum); 2752292SN/A 2762348SN/A // Send back mispredict information. 2772292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2782935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2796036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 2802292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2816036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2827720Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 2838503Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].squashInst = inst; 2846036Sksewell@umich.edu 2853093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 2862935Sksewell@umich.edu 2872348SN/A // Might have to tell fetch to unblock. 2882292SN/A if (decodeStatus[tid] == Blocked || 2892292SN/A decodeStatus[tid] == Unblocking) { 2902292SN/A toFetch->decodeUnblock[tid] = 1; 2912292SN/A } 2922292SN/A 2931060SN/A // Set status to squashing. 2942292SN/A decodeStatus[tid] = Squashing; 2951060SN/A 2962292SN/A for (int i=0; i<fromFetch->size; i++) { 2972292SN/A if (fromFetch->insts[i]->threadNumber == tid && 2982935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 2992731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3002292SN/A } 3012292SN/A } 3022292SN/A 3032348SN/A // Clear the instruction list and skid buffer in case they have any 3042348SN/A // insts in them. 3052292SN/A while (!insts[tid].empty()) { 3062292SN/A insts[tid].pop(); 3072292SN/A } 3081060SN/A 3092292SN/A while (!skidBuffer[tid].empty()) { 3102292SN/A skidBuffer[tid].pop(); 3112292SN/A } 3122292SN/A 3132292SN/A // Squash instructions up until this one 3142935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3152292SN/A} 3162292SN/A 3172292SN/Atemplate<class Impl> 3182292SN/Aunsigned 3196221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3202292SN/A{ 3212292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3222292SN/A 3232292SN/A if (decodeStatus[tid] == Blocked || 3242292SN/A decodeStatus[tid] == Unblocking) { 3252292SN/A#if !FULL_SYSTEM 3262292SN/A // In syscall emulation, we can have both a block and a squash due 3272292SN/A // to a syscall in the same cycle. This would cause both signals to 3282292SN/A // be high. This shouldn't happen in full system. 3292329SN/A // @todo: Determine if this still happens. 3302292SN/A if (toFetch->decodeBlock[tid]) { 3312292SN/A toFetch->decodeBlock[tid] = 0; 3322292SN/A } else { 3332292SN/A toFetch->decodeUnblock[tid] = 1; 3342292SN/A } 3352292SN/A#else 3362292SN/A toFetch->decodeUnblock[tid] = 1; 3372292SN/A#endif 3382292SN/A } 3392292SN/A 3402292SN/A // Set status to squashing. 3412292SN/A decodeStatus[tid] = Squashing; 3422292SN/A 3432292SN/A // Go through incoming instructions from fetch and squash them. 3442292SN/A unsigned squash_count = 0; 3452292SN/A 3462292SN/A for (int i=0; i<fromFetch->size; i++) { 3472292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3482731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3492292SN/A squash_count++; 3502292SN/A } 3512292SN/A } 3522292SN/A 3532348SN/A // Clear the instruction list and skid buffer in case they have any 3542348SN/A // insts in them. 3552292SN/A while (!insts[tid].empty()) { 3562292SN/A insts[tid].pop(); 3572292SN/A } 3582292SN/A 3592292SN/A while (!skidBuffer[tid].empty()) { 3602292SN/A skidBuffer[tid].pop(); 3612292SN/A } 3622292SN/A 3632292SN/A return squash_count; 3642292SN/A} 3652292SN/A 3662292SN/Atemplate<class Impl> 3672292SN/Avoid 3686221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 3692292SN/A{ 3702292SN/A DynInstPtr inst = NULL; 3712292SN/A 3722292SN/A while (!insts[tid].empty()) { 3732292SN/A inst = insts[tid].front(); 3742292SN/A 3752292SN/A insts[tid].pop(); 3762292SN/A 3772292SN/A assert(tid == inst->threadNumber); 3782292SN/A 3797720Sgblack@eecs.umich.edu DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 3807720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState(), inst->threadNumber); 3812292SN/A 3822292SN/A skidBuffer[tid].push(inst); 3832292SN/A } 3842292SN/A 3852329SN/A // @todo: Eventually need to enforce this by not letting a thread 3862292SN/A // fetch past its skidbuffer 3872292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 3882292SN/A} 3892292SN/A 3902292SN/Atemplate<class Impl> 3912292SN/Abool 3922292SN/ADefaultDecode<Impl>::skidsEmpty() 3932292SN/A{ 3946221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3956221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3962292SN/A 3973867Sbinkertn@umich.edu while (threads != end) { 3986221Snate@binkert.org ThreadID tid = *threads++; 3993867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4002292SN/A return false; 4012292SN/A } 4022292SN/A 4032292SN/A return true; 4042292SN/A} 4052292SN/A 4062292SN/Atemplate<class Impl> 4072292SN/Avoid 4082292SN/ADefaultDecode<Impl>::updateStatus() 4092292SN/A{ 4102292SN/A bool any_unblocking = false; 4112292SN/A 4126221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4136221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4142292SN/A 4153867Sbinkertn@umich.edu while (threads != end) { 4166221Snate@binkert.org ThreadID tid = *threads++; 4172292SN/A 4182292SN/A if (decodeStatus[tid] == Unblocking) { 4192292SN/A any_unblocking = true; 4202292SN/A break; 4212292SN/A } 4222292SN/A } 4232292SN/A 4242292SN/A // Decode will have activity if it's unblocking. 4252292SN/A if (any_unblocking) { 4262292SN/A if (_status == Inactive) { 4272292SN/A _status = Active; 4282292SN/A 4292292SN/A DPRINTF(Activity, "Activating stage.\n"); 4302292SN/A 4312733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4322292SN/A } 4332292SN/A } else { 4342292SN/A // If it's not unblocking, then decode will not have any internal 4352292SN/A // activity. Switch it to inactive. 4362292SN/A if (_status == Active) { 4372292SN/A _status = Inactive; 4382292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4392292SN/A 4402733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4412292SN/A } 4422292SN/A } 4432292SN/A} 4442292SN/A 4452292SN/Atemplate <class Impl> 4462292SN/Avoid 4472292SN/ADefaultDecode<Impl>::sortInsts() 4482292SN/A{ 4492292SN/A int insts_from_fetch = fromFetch->size; 4502329SN/A#ifdef DEBUG 4516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 4526221Snate@binkert.org assert(insts[tid].empty()); 4532329SN/A#endif 4542292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4552292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4561060SN/A } 4571060SN/A} 4581060SN/A 4591060SN/Atemplate<class Impl> 4601060SN/Avoid 4616221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4621060SN/A{ 4632292SN/A if (fromRename->renameBlock[tid]) { 4642292SN/A stalls[tid].rename = true; 4652292SN/A } 4661060SN/A 4672292SN/A if (fromRename->renameUnblock[tid]) { 4682292SN/A assert(stalls[tid].rename); 4692292SN/A stalls[tid].rename = false; 4702292SN/A } 4711060SN/A 4722292SN/A if (fromIEW->iewBlock[tid]) { 4732292SN/A stalls[tid].iew = true; 4742292SN/A } 4751062SN/A 4762292SN/A if (fromIEW->iewUnblock[tid]) { 4772292SN/A assert(stalls[tid].iew); 4782292SN/A stalls[tid].iew = false; 4792292SN/A } 4801061SN/A 4812292SN/A if (fromCommit->commitBlock[tid]) { 4822292SN/A stalls[tid].commit = true; 4832292SN/A } 4841062SN/A 4852292SN/A if (fromCommit->commitUnblock[tid]) { 4862292SN/A assert(stalls[tid].commit); 4872292SN/A stalls[tid].commit = false; 4882292SN/A } 4892292SN/A} 4901060SN/A 4912292SN/Atemplate <class Impl> 4922292SN/Abool 4936221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 4942292SN/A{ 4952292SN/A // Check if there's a squash signal, squash if there is. 4962292SN/A // Check stall signals, block if necessary. 4972292SN/A // If status was blocked 4982292SN/A // Check if stall conditions have passed 4992292SN/A // if so then go to unblocking 5002292SN/A // If status was Squashing 5012292SN/A // check if squashing is not high. Switch to running this cycle. 5021060SN/A 5032292SN/A // Update the per thread stall statuses. 5042292SN/A readStallSignals(tid); 5051060SN/A 5062292SN/A // Check squash signals from commit. 5072292SN/A if (fromCommit->commitInfo[tid].squash) { 5081681SN/A 5092292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5102292SN/A "from commit.\n", tid); 5112292SN/A 5122292SN/A squash(tid); 5132292SN/A 5142292SN/A return true; 5152292SN/A } 5162292SN/A 5172292SN/A // Check ROB squash signals from commit. 5182292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5192703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5202292SN/A 5212292SN/A // Continue to squash. 5222292SN/A decodeStatus[tid] = Squashing; 5232292SN/A 5242292SN/A return true; 5252292SN/A } 5262292SN/A 5272292SN/A if (checkStall(tid)) { 5282292SN/A return block(tid); 5292292SN/A } 5302292SN/A 5312292SN/A if (decodeStatus[tid] == Blocked) { 5322292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5332292SN/A tid); 5342292SN/A 5352292SN/A decodeStatus[tid] = Unblocking; 5362292SN/A 5372292SN/A unblock(tid); 5382292SN/A 5392292SN/A return true; 5402292SN/A } 5412292SN/A 5422292SN/A if (decodeStatus[tid] == Squashing) { 5432292SN/A // Switch status to running if decode isn't being told to block or 5442292SN/A // squash this cycle. 5452292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5462292SN/A tid); 5472292SN/A 5482292SN/A decodeStatus[tid] = Running; 5492292SN/A 5502292SN/A return false; 5512292SN/A } 5522292SN/A 5532292SN/A // If we've reached this point, we have not gotten any signals that 5542292SN/A // cause decode to change its status. Decode remains the same as before. 5552292SN/A return false; 5562292SN/A} 5572292SN/A 5582292SN/Atemplate<class Impl> 5592292SN/Avoid 5602292SN/ADefaultDecode<Impl>::tick() 5612292SN/A{ 5622292SN/A wroteToTimeBuffer = false; 5632292SN/A 5642292SN/A bool status_change = false; 5652292SN/A 5662292SN/A toRenameIndex = 0; 5672292SN/A 5686221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5696221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5702292SN/A 5712292SN/A sortInsts(); 5722292SN/A 5732292SN/A //Check stall and squash signals. 5743867Sbinkertn@umich.edu while (threads != end) { 5756221Snate@binkert.org ThreadID tid = *threads++; 5762292SN/A 5772292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5782292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5792292SN/A 5802292SN/A decode(status_change, tid); 5812292SN/A } 5822292SN/A 5832292SN/A if (status_change) { 5842292SN/A updateStatus(); 5852292SN/A } 5862292SN/A 5872292SN/A if (wroteToTimeBuffer) { 5882292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5892292SN/A 5902292SN/A cpu->activityThisCycle(); 5911060SN/A } 5921060SN/A} 5931060SN/A 5941060SN/Atemplate<class Impl> 5951060SN/Avoid 5966221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 5971060SN/A{ 5982292SN/A // If status is Running or idle, 5992292SN/A // call decodeInsts() 6002292SN/A // If status is Unblocking, 6012292SN/A // buffer any instructions coming from fetch 6022292SN/A // continue trying to empty skid buffer 6032292SN/A // check if stall conditions have passed 6042292SN/A 6052292SN/A if (decodeStatus[tid] == Blocked) { 6062292SN/A ++decodeBlockedCycles; 6072292SN/A } else if (decodeStatus[tid] == Squashing) { 6082292SN/A ++decodeSquashCycles; 6091060SN/A } 6101060SN/A 6112292SN/A // Decode should try to decode as many instructions as its bandwidth 6122292SN/A // will allow, as long as it is not currently blocked. 6132292SN/A if (decodeStatus[tid] == Running || 6142292SN/A decodeStatus[tid] == Idle) { 6152935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6162292SN/A "stage.\n",tid); 6172292SN/A 6182292SN/A decodeInsts(tid); 6192292SN/A } else if (decodeStatus[tid] == Unblocking) { 6202292SN/A // Make sure that the skid buffer has something in it if the 6212292SN/A // status is unblocking. 6222292SN/A assert(!skidsEmpty()); 6232292SN/A 6242292SN/A // If the status was unblocking, then instructions from the skid 6252292SN/A // buffer were used. Remove those instructions and handle 6262292SN/A // the rest of unblocking. 6272292SN/A decodeInsts(tid); 6282292SN/A 6292292SN/A if (fetchInstsValid()) { 6302292SN/A // Add the current inputs to the skid buffer so they can be 6312292SN/A // reprocessed when this stage unblocks. 6322292SN/A skidInsert(tid); 6332292SN/A } 6342292SN/A 6352292SN/A status_change = unblock(tid) || status_change; 6361060SN/A } 6372292SN/A} 6381060SN/A 6392292SN/Atemplate <class Impl> 6402292SN/Avoid 6416221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6422292SN/A{ 6432292SN/A // Instructions can come either from the skid buffer or the list of 6442292SN/A // instructions coming from fetch, depending on decode's status. 6452292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6462292SN/A skidBuffer[tid].size() : insts[tid].size(); 6472292SN/A 6482292SN/A if (insts_available == 0) { 6492292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6502292SN/A " early.\n",tid); 6511060SN/A // Should I change the status to idle? 6521062SN/A ++decodeIdleCycles; 6531060SN/A return; 6542292SN/A } else if (decodeStatus[tid] == Unblocking) { 6552292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6562292SN/A "buffer.\n",tid); 6572292SN/A ++decodeUnblockCycles; 6582292SN/A } else if (decodeStatus[tid] == Running) { 6592292SN/A ++decodeRunCycles; 6601060SN/A } 6611060SN/A 6621061SN/A DynInstPtr inst; 6631061SN/A 6642292SN/A std::queue<DynInstPtr> 6652292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6662292SN/A skidBuffer[tid] : insts[tid]; 6671061SN/A 6682292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6691060SN/A 6702292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6712292SN/A assert(!insts_to_decode.empty()); 6721060SN/A 6732292SN/A inst = insts_to_decode.front(); 6741062SN/A 6752292SN/A insts_to_decode.pop(); 6761061SN/A 6772292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 6787720Sgblack@eecs.umich.edu "PC %s\n", tid, inst->seqNum, inst->pcState()); 6791061SN/A 6801061SN/A if (inst->isSquashed()) { 6817720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 6821061SN/A "squashed, skipping.\n", 6837720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6841061SN/A 6851062SN/A ++decodeSquashedInsts; 6861062SN/A 6871061SN/A --insts_available; 6881061SN/A 6891061SN/A continue; 6901061SN/A } 6911060SN/A 6921681SN/A // Also check if instructions have no source registers. Mark 6931681SN/A // them as ready to issue at any time. Not sure if this check 6941681SN/A // should exist here or at a later stage; however it doesn't matter 6951681SN/A // too much for function correctness. 6961681SN/A if (inst->numSrcRegs() == 0) { 6971681SN/A inst->setCanIssue(); 6981681SN/A } 6991681SN/A 7001060SN/A // This current instruction is valid, so add it into the decode 7011060SN/A // queue. The next instruction may not be valid, so check to 7021060SN/A // see if branches were predicted correctly. 7032292SN/A toRename->insts[toRenameIndex] = inst; 7041061SN/A 7051061SN/A ++(toRename->size); 7062292SN/A ++toRenameIndex; 7072292SN/A ++decodeDecodedInsts; 7082292SN/A --insts_available; 7091060SN/A 7108471SGiacomo.Gabrielli@arm.com#if TRACING_ON 7118471SGiacomo.Gabrielli@arm.com inst->decodeTick = curTick(); 7128471SGiacomo.Gabrielli@arm.com#endif 7138471SGiacomo.Gabrielli@arm.com 7141060SN/A // Ensure that if it was predicted as a branch, it really is a 7151061SN/A // branch. 7163796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7171060SN/A panic("Instruction predicted as a branch!"); 7181060SN/A 7191062SN/A ++decodeControlMispred; 7202292SN/A 7211060SN/A // Might want to set some sort of boolean and just do 7221060SN/A // a check at the end 7232292SN/A squash(inst, inst->threadNumber); 7242292SN/A 7251060SN/A break; 7261060SN/A } 7271060SN/A 7281062SN/A // Go ahead and compute any PC-relative branches. 7291063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7302307SN/A ++decodeBranchResolved; 7311062SN/A 7327720Sgblack@eecs.umich.edu if (!(inst->branchTarget() == inst->readPredTarg())) { 7331062SN/A ++decodeBranchMispred; 7342292SN/A 7351060SN/A // Might want to set some sort of boolean and just do 7361060SN/A // a check at the end 7372292SN/A squash(inst, inst->threadNumber); 7387720Sgblack@eecs.umich.edu TheISA::PCState target = inst->branchTarget(); 7396036Sksewell@umich.edu 7407720Sgblack@eecs.umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 7417720Sgblack@eecs.umich.edu inst->seqNum, target); 7426036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7437720Sgblack@eecs.umich.edu inst->setPredTarg(target); 7442935Sksewell@umich.edu break; 7452935Sksewell@umich.edu } 7462935Sksewell@umich.edu } 7471060SN/A } 7481061SN/A 7492292SN/A // If we didn't process all instructions, then we will need to block 7502292SN/A // and put all those instructions into the skid buffer. 7512292SN/A if (!insts_to_decode.empty()) { 7522292SN/A block(tid); 7532292SN/A } 7542292SN/A 7552292SN/A // Record that decode has written to the time buffer for activity 7562292SN/A // tracking. 7572292SN/A if (toRenameIndex) { 7582292SN/A wroteToTimeBuffer = true; 7592292SN/A } 7601060SN/A} 761