decode_impl.hh revision 8471
12199SN/A/* 22199SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32199SN/A * All rights reserved. 42199SN/A * 52199SN/A * Redistribution and use in source and binary forms, with or without 62199SN/A * modification, are permitted provided that the following conditions are 72199SN/A * met: redistributions of source code must retain the above copyright 82199SN/A * notice, this list of conditions and the following disclaimer; 92199SN/A * redistributions in binary form must reproduce the above copyright 102199SN/A * notice, this list of conditions and the following disclaimer in the 112199SN/A * documentation and/or other materials provided with the distribution; 122199SN/A * neither the name of the copyright holders nor the names of its 132199SN/A * contributors may be used to endorse or promote products derived from 142199SN/A * this software without specific prior written permission. 152199SN/A * 162199SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172199SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182199SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192199SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202199SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212199SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222199SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232199SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242199SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252199SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262199SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu */ 302665Ssaidi@eecs.umich.edu 312199SN/A#include "arch/types.hh" 322199SN/A#include "base/trace.hh" 338229Snate@binkert.org#include "config/full_system.hh" 3411793Sbrandon.potter@amd.com#include "config/the_isa.hh" 352561SN/A#include "cpu/o3/decode.hh" 366329Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 3713988Sgabeblack@google.com#include "debug/Activity.hh" 382199SN/A#include "debug/Decode.hh" 392680Sktlim@umich.edu#include "params/DerivO3CPU.hh" 402199SN/A 412199SN/Ausing namespace std; 4211794Sbrandon.potter@amd.com 432199SN/Atemplate<class Impl> 442199SN/ADefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 452199SN/A : cpu(_cpu), 462209SN/A renameToDecodeDelay(params->renameToDecodeDelay), 472199SN/A iewToDecodeDelay(params->iewToDecodeDelay), 4813988Sgabeblack@google.com commitToDecodeDelay(params->commitToDecodeDelay), 4913988Sgabeblack@google.com fetchToDecodeDelay(params->fetchToDecodeDelay), 5013988Sgabeblack@google.com decodeWidth(params->decodeWidth), 5113988Sgabeblack@google.com numThreads(params->numThreads) 5213988Sgabeblack@google.com{ 5313988Sgabeblack@google.com _status = Inactive; 5413988Sgabeblack@google.com 5513988Sgabeblack@google.com // Setup status, make sure stall signals are clear. 5613988Sgabeblack@google.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 5713988Sgabeblack@google.com decodeStatus[tid] = Idle; 5813988Sgabeblack@google.com 5913988Sgabeblack@google.com stalls[tid].rename = false; 6013988Sgabeblack@google.com stalls[tid].iew = false; 6113988Sgabeblack@google.com stalls[tid].commit = false; 6213988Sgabeblack@google.com } 6313988Sgabeblack@google.com 6413988Sgabeblack@google.com // @todo: Make into a parameter 6513988Sgabeblack@google.com skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 6613988Sgabeblack@google.com} 6713988Sgabeblack@google.com 6813988Sgabeblack@google.comtemplate <class Impl> 6913988Sgabeblack@google.comstd::string 7013988Sgabeblack@google.comDefaultDecode<Impl>::name() const 7113988Sgabeblack@google.com{ 7213988Sgabeblack@google.com return cpu->name() + ".decode"; 7313988Sgabeblack@google.com} 7413988Sgabeblack@google.com 7513988Sgabeblack@google.comtemplate <class Impl> 7613988Sgabeblack@google.comvoid 7713988Sgabeblack@google.comDefaultDecode<Impl>::regStats() 7813988Sgabeblack@google.com{ 7913988Sgabeblack@google.com decodeIdleCycles 8013988Sgabeblack@google.com .name(name() + ".IdleCycles") 8113988Sgabeblack@google.com .desc("Number of cycles decode is idle") 822199SN/A .prereq(decodeIdleCycles); 832458SN/A decodeBlockedCycles 842199SN/A .name(name() + ".BlockedCycles") 855981Sstever@gmail.com .desc("Number of cycles decode is blocked") 862199SN/A .prereq(decodeBlockedCycles); 872199SN/A decodeRunCycles 882199SN/A .name(name() + ".RunCycles") 894111Sgblack@eecs.umich.edu .desc("Number of cycles decode is running") 904188Sgblack@eecs.umich.edu .prereq(decodeRunCycles); 914188Sgblack@eecs.umich.edu decodeUnblockCycles 924188Sgblack@eecs.umich.edu .name(name() + ".UnblockCycles") 935981Sstever@gmail.com .desc("Number of cycles decode is unblocking") 944188Sgblack@eecs.umich.edu .prereq(decodeUnblockCycles); 954188Sgblack@eecs.umich.edu decodeSquashCycles 964188Sgblack@eecs.umich.edu .name(name() + ".SquashCycles") 974111Sgblack@eecs.umich.edu .desc("Number of cycles decode is squashing") 9811851Sbrandon.potter@amd.com .prereq(decodeSquashCycles); 995154Sgblack@eecs.umich.edu decodeBranchResolved 10011851Sbrandon.potter@amd.com .name(name() + ".BranchResolved") 1014111Sgblack@eecs.umich.edu .desc("Number of times decode resolved a branch") 1024111Sgblack@eecs.umich.edu .prereq(decodeBranchResolved); 10311877Sbrandon.potter@amd.com decodeBranchMispred 10411877Sbrandon.potter@amd.com .name(name() + ".BranchMispred") 1054111Sgblack@eecs.umich.edu .desc("Number of times decode detected a branch misprediction") 1067741Sgblack@eecs.umich.edu .prereq(decodeBranchMispred); 1074111Sgblack@eecs.umich.edu decodeControlMispred 10811877Sbrandon.potter@amd.com .name(name() + ".ControlMispred") 1094111Sgblack@eecs.umich.edu .desc("Number of times decode detected an instruction incorrectly" 1104111Sgblack@eecs.umich.edu " predicted as a control") 11111877Sbrandon.potter@amd.com .prereq(decodeControlMispred); 1124111Sgblack@eecs.umich.edu decodeDecodedInsts 1134111Sgblack@eecs.umich.edu .name(name() + ".DecodedInsts") 1144111Sgblack@eecs.umich.edu .desc("Number of instructions handled by decode") 11511851Sbrandon.potter@amd.com .prereq(decodeDecodedInsts); 1165154Sgblack@eecs.umich.edu decodeSquashedInsts 11711851Sbrandon.potter@amd.com .name(name() + ".SquashedInsts") 1184111Sgblack@eecs.umich.edu .desc("Number of squashed instructions handled by decode") 1194111Sgblack@eecs.umich.edu .prereq(decodeSquashedInsts); 12011877Sbrandon.potter@amd.com} 12111877Sbrandon.potter@amd.com 1224111Sgblack@eecs.umich.edutemplate<class Impl> 1237741Sgblack@eecs.umich.eduvoid 1247741Sgblack@eecs.umich.eduDefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1257741Sgblack@eecs.umich.edu{ 12611877Sbrandon.potter@amd.com timeBuffer = tb_ptr; 1274111Sgblack@eecs.umich.edu 1284111Sgblack@eecs.umich.edu // Setup wire to write information back to fetch. 12911877Sbrandon.potter@amd.com toFetch = timeBuffer->getWire(0); 1304111Sgblack@eecs.umich.edu 1314111Sgblack@eecs.umich.edu // Create wires to get information from proper places in time buffer. 132 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 133 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 134 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 135} 136 137template<class Impl> 138void 139DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 140{ 141 decodeQueue = dq_ptr; 142 143 // Setup wire to write information to proper place in decode queue. 144 toRename = decodeQueue->getWire(0); 145} 146 147template<class Impl> 148void 149DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 150{ 151 fetchQueue = fq_ptr; 152 153 // Setup wire to read information from fetch queue. 154 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 155} 156 157template<class Impl> 158void 159DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 160{ 161 activeThreads = at_ptr; 162} 163 164template <class Impl> 165bool 166DefaultDecode<Impl>::drain() 167{ 168 // Decode is done draining at any time. 169 cpu->signalDrained(); 170 return true; 171} 172 173template <class Impl> 174void 175DefaultDecode<Impl>::takeOverFrom() 176{ 177 _status = Inactive; 178 179 // Be sure to reset state and clear out any old instructions. 180 for (ThreadID tid = 0; tid < numThreads; ++tid) { 181 decodeStatus[tid] = Idle; 182 183 stalls[tid].rename = false; 184 stalls[tid].iew = false; 185 stalls[tid].commit = false; 186 while (!insts[tid].empty()) 187 insts[tid].pop(); 188 while (!skidBuffer[tid].empty()) 189 skidBuffer[tid].pop(); 190 branchCount[tid] = 0; 191 } 192 wroteToTimeBuffer = false; 193} 194 195template<class Impl> 196bool 197DefaultDecode<Impl>::checkStall(ThreadID tid) const 198{ 199 bool ret_val = false; 200 201 if (stalls[tid].rename) { 202 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 203 ret_val = true; 204 } else if (stalls[tid].iew) { 205 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 206 ret_val = true; 207 } else if (stalls[tid].commit) { 208 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 209 ret_val = true; 210 } 211 212 return ret_val; 213} 214 215template<class Impl> 216inline bool 217DefaultDecode<Impl>::fetchInstsValid() 218{ 219 return fromFetch->size > 0; 220} 221 222template<class Impl> 223bool 224DefaultDecode<Impl>::block(ThreadID tid) 225{ 226 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 227 228 // Add the current inputs to the skid buffer so they can be 229 // reprocessed when this stage unblocks. 230 skidInsert(tid); 231 232 // If the decode status is blocked or unblocking then decode has not yet 233 // signalled fetch to unblock. In that case, there is no need to tell 234 // fetch to block. 235 if (decodeStatus[tid] != Blocked) { 236 // Set the status to Blocked. 237 decodeStatus[tid] = Blocked; 238 239 if (decodeStatus[tid] != Unblocking) { 240 toFetch->decodeBlock[tid] = true; 241 wroteToTimeBuffer = true; 242 } 243 244 return true; 245 } 246 247 return false; 248} 249 250template<class Impl> 251bool 252DefaultDecode<Impl>::unblock(ThreadID tid) 253{ 254 // Decode is done unblocking only if the skid buffer is empty. 255 if (skidBuffer[tid].empty()) { 256 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 257 toFetch->decodeUnblock[tid] = true; 258 wroteToTimeBuffer = true; 259 260 decodeStatus[tid] = Running; 261 return true; 262 } 263 264 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 265 266 return false; 267} 268 269template<class Impl> 270void 271DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 272{ 273 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 274 "prediction detected at decode.\n", tid, inst->seqNum); 275 276 // Send back mispredict information. 277 toFetch->decodeInfo[tid].branchMispredict = true; 278 toFetch->decodeInfo[tid].predIncorrect = true; 279 toFetch->decodeInfo[tid].squash = true; 280 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 281 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 282 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 283 284 InstSeqNum squash_seq_num = inst->seqNum; 285 286 // Might have to tell fetch to unblock. 287 if (decodeStatus[tid] == Blocked || 288 decodeStatus[tid] == Unblocking) { 289 toFetch->decodeUnblock[tid] = 1; 290 } 291 292 // Set status to squashing. 293 decodeStatus[tid] = Squashing; 294 295 for (int i=0; i<fromFetch->size; i++) { 296 if (fromFetch->insts[i]->threadNumber == tid && 297 fromFetch->insts[i]->seqNum > squash_seq_num) { 298 fromFetch->insts[i]->setSquashed(); 299 } 300 } 301 302 // Clear the instruction list and skid buffer in case they have any 303 // insts in them. 304 while (!insts[tid].empty()) { 305 insts[tid].pop(); 306 } 307 308 while (!skidBuffer[tid].empty()) { 309 skidBuffer[tid].pop(); 310 } 311 312 // Squash instructions up until this one 313 cpu->removeInstsUntil(squash_seq_num, tid); 314} 315 316template<class Impl> 317unsigned 318DefaultDecode<Impl>::squash(ThreadID tid) 319{ 320 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 321 322 if (decodeStatus[tid] == Blocked || 323 decodeStatus[tid] == Unblocking) { 324#if !FULL_SYSTEM 325 // In syscall emulation, we can have both a block and a squash due 326 // to a syscall in the same cycle. This would cause both signals to 327 // be high. This shouldn't happen in full system. 328 // @todo: Determine if this still happens. 329 if (toFetch->decodeBlock[tid]) { 330 toFetch->decodeBlock[tid] = 0; 331 } else { 332 toFetch->decodeUnblock[tid] = 1; 333 } 334#else 335 toFetch->decodeUnblock[tid] = 1; 336#endif 337 } 338 339 // Set status to squashing. 340 decodeStatus[tid] = Squashing; 341 342 // Go through incoming instructions from fetch and squash them. 343 unsigned squash_count = 0; 344 345 for (int i=0; i<fromFetch->size; i++) { 346 if (fromFetch->insts[i]->threadNumber == tid) { 347 fromFetch->insts[i]->setSquashed(); 348 squash_count++; 349 } 350 } 351 352 // Clear the instruction list and skid buffer in case they have any 353 // insts in them. 354 while (!insts[tid].empty()) { 355 insts[tid].pop(); 356 } 357 358 while (!skidBuffer[tid].empty()) { 359 skidBuffer[tid].pop(); 360 } 361 362 return squash_count; 363} 364 365template<class Impl> 366void 367DefaultDecode<Impl>::skidInsert(ThreadID tid) 368{ 369 DynInstPtr inst = NULL; 370 371 while (!insts[tid].empty()) { 372 inst = insts[tid].front(); 373 374 insts[tid].pop(); 375 376 assert(tid == inst->threadNumber); 377 378 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 379 inst->seqNum, inst->pcState(), inst->threadNumber); 380 381 skidBuffer[tid].push(inst); 382 } 383 384 // @todo: Eventually need to enforce this by not letting a thread 385 // fetch past its skidbuffer 386 assert(skidBuffer[tid].size() <= skidBufferMax); 387} 388 389template<class Impl> 390bool 391DefaultDecode<Impl>::skidsEmpty() 392{ 393 list<ThreadID>::iterator threads = activeThreads->begin(); 394 list<ThreadID>::iterator end = activeThreads->end(); 395 396 while (threads != end) { 397 ThreadID tid = *threads++; 398 if (!skidBuffer[tid].empty()) 399 return false; 400 } 401 402 return true; 403} 404 405template<class Impl> 406void 407DefaultDecode<Impl>::updateStatus() 408{ 409 bool any_unblocking = false; 410 411 list<ThreadID>::iterator threads = activeThreads->begin(); 412 list<ThreadID>::iterator end = activeThreads->end(); 413 414 while (threads != end) { 415 ThreadID tid = *threads++; 416 417 if (decodeStatus[tid] == Unblocking) { 418 any_unblocking = true; 419 break; 420 } 421 } 422 423 // Decode will have activity if it's unblocking. 424 if (any_unblocking) { 425 if (_status == Inactive) { 426 _status = Active; 427 428 DPRINTF(Activity, "Activating stage.\n"); 429 430 cpu->activateStage(O3CPU::DecodeIdx); 431 } 432 } else { 433 // If it's not unblocking, then decode will not have any internal 434 // activity. Switch it to inactive. 435 if (_status == Active) { 436 _status = Inactive; 437 DPRINTF(Activity, "Deactivating stage.\n"); 438 439 cpu->deactivateStage(O3CPU::DecodeIdx); 440 } 441 } 442} 443 444template <class Impl> 445void 446DefaultDecode<Impl>::sortInsts() 447{ 448 int insts_from_fetch = fromFetch->size; 449#ifdef DEBUG 450 for (ThreadID tid = 0; tid < numThreads; tid++) 451 assert(insts[tid].empty()); 452#endif 453 for (int i = 0; i < insts_from_fetch; ++i) { 454 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 455 } 456} 457 458template<class Impl> 459void 460DefaultDecode<Impl>::readStallSignals(ThreadID tid) 461{ 462 if (fromRename->renameBlock[tid]) { 463 stalls[tid].rename = true; 464 } 465 466 if (fromRename->renameUnblock[tid]) { 467 assert(stalls[tid].rename); 468 stalls[tid].rename = false; 469 } 470 471 if (fromIEW->iewBlock[tid]) { 472 stalls[tid].iew = true; 473 } 474 475 if (fromIEW->iewUnblock[tid]) { 476 assert(stalls[tid].iew); 477 stalls[tid].iew = false; 478 } 479 480 if (fromCommit->commitBlock[tid]) { 481 stalls[tid].commit = true; 482 } 483 484 if (fromCommit->commitUnblock[tid]) { 485 assert(stalls[tid].commit); 486 stalls[tid].commit = false; 487 } 488} 489 490template <class Impl> 491bool 492DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 493{ 494 // Check if there's a squash signal, squash if there is. 495 // Check stall signals, block if necessary. 496 // If status was blocked 497 // Check if stall conditions have passed 498 // if so then go to unblocking 499 // If status was Squashing 500 // check if squashing is not high. Switch to running this cycle. 501 502 // Update the per thread stall statuses. 503 readStallSignals(tid); 504 505 // Check squash signals from commit. 506 if (fromCommit->commitInfo[tid].squash) { 507 508 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 509 "from commit.\n", tid); 510 511 squash(tid); 512 513 return true; 514 } 515 516 // Check ROB squash signals from commit. 517 if (fromCommit->commitInfo[tid].robSquashing) { 518 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 519 520 // Continue to squash. 521 decodeStatus[tid] = Squashing; 522 523 return true; 524 } 525 526 if (checkStall(tid)) { 527 return block(tid); 528 } 529 530 if (decodeStatus[tid] == Blocked) { 531 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 532 tid); 533 534 decodeStatus[tid] = Unblocking; 535 536 unblock(tid); 537 538 return true; 539 } 540 541 if (decodeStatus[tid] == Squashing) { 542 // Switch status to running if decode isn't being told to block or 543 // squash this cycle. 544 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 545 tid); 546 547 decodeStatus[tid] = Running; 548 549 return false; 550 } 551 552 // If we've reached this point, we have not gotten any signals that 553 // cause decode to change its status. Decode remains the same as before. 554 return false; 555} 556 557template<class Impl> 558void 559DefaultDecode<Impl>::tick() 560{ 561 wroteToTimeBuffer = false; 562 563 bool status_change = false; 564 565 toRenameIndex = 0; 566 567 list<ThreadID>::iterator threads = activeThreads->begin(); 568 list<ThreadID>::iterator end = activeThreads->end(); 569 570 sortInsts(); 571 572 //Check stall and squash signals. 573 while (threads != end) { 574 ThreadID tid = *threads++; 575 576 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 577 status_change = checkSignalsAndUpdate(tid) || status_change; 578 579 decode(status_change, tid); 580 } 581 582 if (status_change) { 583 updateStatus(); 584 } 585 586 if (wroteToTimeBuffer) { 587 DPRINTF(Activity, "Activity this cycle.\n"); 588 589 cpu->activityThisCycle(); 590 } 591} 592 593template<class Impl> 594void 595DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 596{ 597 // If status is Running or idle, 598 // call decodeInsts() 599 // If status is Unblocking, 600 // buffer any instructions coming from fetch 601 // continue trying to empty skid buffer 602 // check if stall conditions have passed 603 604 if (decodeStatus[tid] == Blocked) { 605 ++decodeBlockedCycles; 606 } else if (decodeStatus[tid] == Squashing) { 607 ++decodeSquashCycles; 608 } 609 610 // Decode should try to decode as many instructions as its bandwidth 611 // will allow, as long as it is not currently blocked. 612 if (decodeStatus[tid] == Running || 613 decodeStatus[tid] == Idle) { 614 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 615 "stage.\n",tid); 616 617 decodeInsts(tid); 618 } else if (decodeStatus[tid] == Unblocking) { 619 // Make sure that the skid buffer has something in it if the 620 // status is unblocking. 621 assert(!skidsEmpty()); 622 623 // If the status was unblocking, then instructions from the skid 624 // buffer were used. Remove those instructions and handle 625 // the rest of unblocking. 626 decodeInsts(tid); 627 628 if (fetchInstsValid()) { 629 // Add the current inputs to the skid buffer so they can be 630 // reprocessed when this stage unblocks. 631 skidInsert(tid); 632 } 633 634 status_change = unblock(tid) || status_change; 635 } 636} 637 638template <class Impl> 639void 640DefaultDecode<Impl>::decodeInsts(ThreadID tid) 641{ 642 // Instructions can come either from the skid buffer or the list of 643 // instructions coming from fetch, depending on decode's status. 644 int insts_available = decodeStatus[tid] == Unblocking ? 645 skidBuffer[tid].size() : insts[tid].size(); 646 647 if (insts_available == 0) { 648 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 649 " early.\n",tid); 650 // Should I change the status to idle? 651 ++decodeIdleCycles; 652 return; 653 } else if (decodeStatus[tid] == Unblocking) { 654 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 655 "buffer.\n",tid); 656 ++decodeUnblockCycles; 657 } else if (decodeStatus[tid] == Running) { 658 ++decodeRunCycles; 659 } 660 661 DynInstPtr inst; 662 663 std::queue<DynInstPtr> 664 &insts_to_decode = decodeStatus[tid] == Unblocking ? 665 skidBuffer[tid] : insts[tid]; 666 667 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 668 669 while (insts_available > 0 && toRenameIndex < decodeWidth) { 670 assert(!insts_to_decode.empty()); 671 672 inst = insts_to_decode.front(); 673 674 insts_to_decode.pop(); 675 676 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 677 "PC %s\n", tid, inst->seqNum, inst->pcState()); 678 679 if (inst->isSquashed()) { 680 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 681 "squashed, skipping.\n", 682 tid, inst->seqNum, inst->pcState()); 683 684 ++decodeSquashedInsts; 685 686 --insts_available; 687 688 continue; 689 } 690 691 // Also check if instructions have no source registers. Mark 692 // them as ready to issue at any time. Not sure if this check 693 // should exist here or at a later stage; however it doesn't matter 694 // too much for function correctness. 695 if (inst->numSrcRegs() == 0) { 696 inst->setCanIssue(); 697 } 698 699 // This current instruction is valid, so add it into the decode 700 // queue. The next instruction may not be valid, so check to 701 // see if branches were predicted correctly. 702 toRename->insts[toRenameIndex] = inst; 703 704 ++(toRename->size); 705 ++toRenameIndex; 706 ++decodeDecodedInsts; 707 --insts_available; 708 709#if TRACING_ON 710 inst->decodeTick = curTick(); 711#endif 712 713 // Ensure that if it was predicted as a branch, it really is a 714 // branch. 715 if (inst->readPredTaken() && !inst->isControl()) { 716 panic("Instruction predicted as a branch!"); 717 718 ++decodeControlMispred; 719 720 // Might want to set some sort of boolean and just do 721 // a check at the end 722 squash(inst, inst->threadNumber); 723 724 break; 725 } 726 727 // Go ahead and compute any PC-relative branches. 728 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 729 ++decodeBranchResolved; 730 731 if (!(inst->branchTarget() == inst->readPredTarg())) { 732 ++decodeBranchMispred; 733 734 // Might want to set some sort of boolean and just do 735 // a check at the end 736 squash(inst, inst->threadNumber); 737 TheISA::PCState target = inst->branchTarget(); 738 739 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 740 inst->seqNum, target); 741 //The micro pc after an instruction level branch should be 0 742 inst->setPredTarg(target); 743 break; 744 } 745 } 746 } 747 748 // If we didn't process all instructions, then we will need to block 749 // and put all those instructions into the skid buffer. 750 if (!insts_to_decode.empty()) { 751 block(tid); 752 } 753 754 // Record that decode has written to the time buffer for activity 755 // tracking. 756 if (toRenameIndex) { 757 wroteToTimeBuffer = true; 758 } 759} 760