decode_impl.hh revision 4329
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311717SN/A#include "cpu/o3/decode.hh" 321060SN/A 331060SN/Atemplate<class Impl> 344329Sktlim@umich.eduDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params) 354329Sktlim@umich.edu : cpu(_cpu), 364329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 372292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 382292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 392292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 402292SN/A decodeWidth(params->decodeWidth), 412292SN/A numThreads(params->numberOfThreads) 421060SN/A{ 432292SN/A _status = Inactive; 442292SN/A 452348SN/A // Setup status, make sure stall signals are clear. 462292SN/A for (int i = 0; i < numThreads; ++i) { 472292SN/A decodeStatus[i] = Idle; 482292SN/A 492292SN/A stalls[i].rename = false; 502292SN/A stalls[i].iew = false; 512292SN/A stalls[i].commit = false; 522935Sksewell@umich.edu 532935Sksewell@umich.edu squashAfterDelaySlot[i] = false; 542292SN/A } 552292SN/A 562292SN/A // @todo: Make into a parameter 572292SN/A skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 582292SN/A} 592292SN/A 602292SN/Atemplate <class Impl> 612292SN/Astd::string 622292SN/ADefaultDecode<Impl>::name() const 632292SN/A{ 642292SN/A return cpu->name() + ".decode"; 651060SN/A} 661060SN/A 671062SN/Atemplate <class Impl> 681062SN/Avoid 692292SN/ADefaultDecode<Impl>::regStats() 701062SN/A{ 711062SN/A decodeIdleCycles 722307SN/A .name(name() + ".DECODE:IdleCycles") 731062SN/A .desc("Number of cycles decode is idle") 741062SN/A .prereq(decodeIdleCycles); 751062SN/A decodeBlockedCycles 762307SN/A .name(name() + ".DECODE:BlockedCycles") 771062SN/A .desc("Number of cycles decode is blocked") 781062SN/A .prereq(decodeBlockedCycles); 792292SN/A decodeRunCycles 802307SN/A .name(name() + ".DECODE:RunCycles") 812292SN/A .desc("Number of cycles decode is running") 822292SN/A .prereq(decodeRunCycles); 831062SN/A decodeUnblockCycles 842307SN/A .name(name() + ".DECODE:UnblockCycles") 851062SN/A .desc("Number of cycles decode is unblocking") 861062SN/A .prereq(decodeUnblockCycles); 871062SN/A decodeSquashCycles 882307SN/A .name(name() + ".DECODE:SquashCycles") 891062SN/A .desc("Number of cycles decode is squashing") 901062SN/A .prereq(decodeSquashCycles); 912307SN/A decodeBranchResolved 922307SN/A .name(name() + ".DECODE:BranchResolved") 932307SN/A .desc("Number of times decode resolved a branch") 942307SN/A .prereq(decodeBranchResolved); 951062SN/A decodeBranchMispred 962307SN/A .name(name() + ".DECODE:BranchMispred") 971062SN/A .desc("Number of times decode detected a branch misprediction") 981062SN/A .prereq(decodeBranchMispred); 991062SN/A decodeControlMispred 1002307SN/A .name(name() + ".DECODE:ControlMispred") 1011062SN/A .desc("Number of times decode detected an instruction incorrectly" 1021062SN/A " predicted as a control") 1031062SN/A .prereq(decodeControlMispred); 1041062SN/A decodeDecodedInsts 1052307SN/A .name(name() + ".DECODE:DecodedInsts") 1061062SN/A .desc("Number of instructions handled by decode") 1071062SN/A .prereq(decodeDecodedInsts); 1081062SN/A decodeSquashedInsts 1092307SN/A .name(name() + ".DECODE:SquashedInsts") 1101062SN/A .desc("Number of squashed instructions handled by decode") 1111062SN/A .prereq(decodeSquashedInsts); 1121062SN/A} 1131062SN/A 1141060SN/Atemplate<class Impl> 1151060SN/Avoid 1162292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1171060SN/A{ 1181060SN/A timeBuffer = tb_ptr; 1191060SN/A 1201060SN/A // Setup wire to write information back to fetch. 1211060SN/A toFetch = timeBuffer->getWire(0); 1221060SN/A 1231060SN/A // Create wires to get information from proper places in time buffer. 1241060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1251060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1261060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1271060SN/A} 1281060SN/A 1291060SN/Atemplate<class Impl> 1301060SN/Avoid 1312292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1321060SN/A{ 1331060SN/A decodeQueue = dq_ptr; 1341060SN/A 1351060SN/A // Setup wire to write information to proper place in decode queue. 1361060SN/A toRename = decodeQueue->getWire(0); 1371060SN/A} 1381060SN/A 1391060SN/Atemplate<class Impl> 1401060SN/Avoid 1412292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1421060SN/A{ 1431060SN/A fetchQueue = fq_ptr; 1441060SN/A 1451060SN/A // Setup wire to read information from fetch queue. 1461060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1471060SN/A} 1481060SN/A 1491060SN/Atemplate<class Impl> 1502292SN/Avoid 1512980Sgblack@eecs.umich.eduDefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 1522292SN/A{ 1532292SN/A activeThreads = at_ptr; 1542292SN/A} 1552292SN/A 1562307SN/Atemplate <class Impl> 1572863Sktlim@umich.edubool 1582843Sktlim@umich.eduDefaultDecode<Impl>::drain() 1592307SN/A{ 1602843Sktlim@umich.edu // Decode is done draining at any time. 1612843Sktlim@umich.edu cpu->signalDrained(); 1622863Sktlim@umich.edu return true; 1632307SN/A} 1642307SN/A 1652307SN/Atemplate <class Impl> 1662307SN/Avoid 1672307SN/ADefaultDecode<Impl>::takeOverFrom() 1682307SN/A{ 1692307SN/A _status = Inactive; 1702307SN/A 1712348SN/A // Be sure to reset state and clear out any old instructions. 1722307SN/A for (int i = 0; i < numThreads; ++i) { 1732307SN/A decodeStatus[i] = Idle; 1742307SN/A 1752307SN/A stalls[i].rename = false; 1762307SN/A stalls[i].iew = false; 1772307SN/A stalls[i].commit = false; 1782307SN/A while (!insts[i].empty()) 1792307SN/A insts[i].pop(); 1802307SN/A while (!skidBuffer[i].empty()) 1812307SN/A skidBuffer[i].pop(); 1822307SN/A branchCount[i] = 0; 1832307SN/A } 1842307SN/A wroteToTimeBuffer = false; 1852307SN/A} 1862307SN/A 1872292SN/Atemplate<class Impl> 1882292SN/Abool 1892292SN/ADefaultDecode<Impl>::checkStall(unsigned tid) const 1902292SN/A{ 1912292SN/A bool ret_val = false; 1922292SN/A 1932292SN/A if (stalls[tid].rename) { 1942292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 1952292SN/A ret_val = true; 1962292SN/A } else if (stalls[tid].iew) { 1972292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 1982292SN/A ret_val = true; 1992292SN/A } else if (stalls[tid].commit) { 2002292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2012292SN/A ret_val = true; 2022292SN/A } 2032292SN/A 2042292SN/A return ret_val; 2052292SN/A} 2062292SN/A 2072292SN/Atemplate<class Impl> 2081681SN/Ainline bool 2092292SN/ADefaultDecode<Impl>::fetchInstsValid() 2101681SN/A{ 2111681SN/A return fromFetch->size > 0; 2121681SN/A} 2131681SN/A 2141681SN/Atemplate<class Impl> 2152292SN/Abool 2162292SN/ADefaultDecode<Impl>::block(unsigned tid) 2171060SN/A{ 2182292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2191060SN/A 2201060SN/A // Add the current inputs to the skid buffer so they can be 2211060SN/A // reprocessed when this stage unblocks. 2222292SN/A skidInsert(tid); 2231060SN/A 2242348SN/A // If the decode status is blocked or unblocking then decode has not yet 2252348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2262348SN/A // fetch to block. 2272292SN/A if (decodeStatus[tid] != Blocked) { 2282292SN/A // Set the status to Blocked. 2292292SN/A decodeStatus[tid] = Blocked; 2302348SN/A 2312348SN/A if (decodeStatus[tid] != Unblocking) { 2322348SN/A toFetch->decodeBlock[tid] = true; 2332348SN/A wroteToTimeBuffer = true; 2342348SN/A } 2352348SN/A 2362292SN/A return true; 2372292SN/A } 2382292SN/A 2392292SN/A return false; 2401060SN/A} 2411060SN/A 2421060SN/Atemplate<class Impl> 2432292SN/Abool 2442292SN/ADefaultDecode<Impl>::unblock(unsigned tid) 2451060SN/A{ 2462292SN/A // Decode is done unblocking only if the skid buffer is empty. 2472292SN/A if (skidBuffer[tid].empty()) { 2482292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2492292SN/A toFetch->decodeUnblock[tid] = true; 2502292SN/A wroteToTimeBuffer = true; 2511060SN/A 2522292SN/A decodeStatus[tid] = Running; 2532292SN/A return true; 2541060SN/A } 2551681SN/A 2562329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2572329SN/A 2582292SN/A return false; 2591060SN/A} 2601060SN/A 2611060SN/Atemplate<class Impl> 2621060SN/Avoid 2632292SN/ADefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 2641060SN/A{ 2652292SN/A DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 2662292SN/A "detected at decode.\n", tid); 2672292SN/A 2682348SN/A // Send back mispredict information. 2692292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2702935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2712292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2722292SN/A toFetch->decodeInfo[tid].squash = true; 2732678Sktlim@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2743967Sgblack@eecs.umich.edu ///FIXME There needs to be a way to set the nextPC and nextNPC 2753967Sgblack@eecs.umich.edu ///explicitly for ISAs with delay slots. 2763967Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].nextNPC = 2773967Sgblack@eecs.umich.edu inst->branchTarget() + sizeof(TheISA::MachInst); 2783093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 2792935Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 2802935Sksewell@umich.edu (inst->readNextPC() + sizeof(TheISA::MachInst)); 2812935Sksewell@umich.edu 2822935Sksewell@umich.edu toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 2832935Sksewell@umich.edu squashAfterDelaySlot[tid] = false; 2842935Sksewell@umich.edu 2852935Sksewell@umich.edu InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 2863093Sksewell@umich.edu#else 2873093Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = 2883093Sksewell@umich.edu inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 2893093Sksewell@umich.edu 2903093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 2912935Sksewell@umich.edu#endif 2922935Sksewell@umich.edu 2932348SN/A // Might have to tell fetch to unblock. 2942292SN/A if (decodeStatus[tid] == Blocked || 2952292SN/A decodeStatus[tid] == Unblocking) { 2962292SN/A toFetch->decodeUnblock[tid] = 1; 2972292SN/A } 2982292SN/A 2991060SN/A // Set status to squashing. 3002292SN/A decodeStatus[tid] = Squashing; 3011060SN/A 3022292SN/A for (int i=0; i<fromFetch->size; i++) { 3032292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3042935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3052731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3062292SN/A } 3072292SN/A } 3082292SN/A 3092348SN/A // Clear the instruction list and skid buffer in case they have any 3102348SN/A // insts in them. 3112292SN/A while (!insts[tid].empty()) { 3122935Sksewell@umich.edu 3133093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3142935Sksewell@umich.edu if (insts[tid].front()->seqNum <= squash_seq_num) { 3152935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 3162935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3172935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3182935Sksewell@umich.edu insts[tid].size()); 3192935Sksewell@umich.edu break; 3202935Sksewell@umich.edu } 3212935Sksewell@umich.edu#endif 3222292SN/A insts[tid].pop(); 3232292SN/A } 3241060SN/A 3252292SN/A while (!skidBuffer[tid].empty()) { 3262935Sksewell@umich.edu 3273093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3282935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 3292935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 3302935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3312935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3322935Sksewell@umich.edu insts[tid].size()); 3332935Sksewell@umich.edu break; 3342935Sksewell@umich.edu } 3352935Sksewell@umich.edu#endif 3362292SN/A skidBuffer[tid].pop(); 3372292SN/A } 3382292SN/A 3392292SN/A // Squash instructions up until this one 3402935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3412292SN/A} 3422292SN/A 3432292SN/Atemplate<class Impl> 3442292SN/Aunsigned 3452292SN/ADefaultDecode<Impl>::squash(unsigned tid) 3462292SN/A{ 3472292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3482292SN/A 3492292SN/A if (decodeStatus[tid] == Blocked || 3502292SN/A decodeStatus[tid] == Unblocking) { 3512292SN/A#if !FULL_SYSTEM 3522292SN/A // In syscall emulation, we can have both a block and a squash due 3532292SN/A // to a syscall in the same cycle. This would cause both signals to 3542292SN/A // be high. This shouldn't happen in full system. 3552329SN/A // @todo: Determine if this still happens. 3562292SN/A if (toFetch->decodeBlock[tid]) { 3572292SN/A toFetch->decodeBlock[tid] = 0; 3582292SN/A } else { 3592292SN/A toFetch->decodeUnblock[tid] = 1; 3602292SN/A } 3612292SN/A#else 3622292SN/A toFetch->decodeUnblock[tid] = 1; 3632292SN/A#endif 3642292SN/A } 3652292SN/A 3662292SN/A // Set status to squashing. 3672292SN/A decodeStatus[tid] = Squashing; 3682292SN/A 3692292SN/A // Go through incoming instructions from fetch and squash them. 3702292SN/A unsigned squash_count = 0; 3712292SN/A 3722292SN/A for (int i=0; i<fromFetch->size; i++) { 3732292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3742731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3752292SN/A squash_count++; 3762292SN/A } 3772292SN/A } 3782292SN/A 3792348SN/A // Clear the instruction list and skid buffer in case they have any 3802348SN/A // insts in them. 3812292SN/A while (!insts[tid].empty()) { 3822292SN/A insts[tid].pop(); 3832292SN/A } 3842292SN/A 3852292SN/A while (!skidBuffer[tid].empty()) { 3862292SN/A skidBuffer[tid].pop(); 3872292SN/A } 3882292SN/A 3892292SN/A return squash_count; 3902292SN/A} 3912292SN/A 3922292SN/Atemplate<class Impl> 3932292SN/Avoid 3942292SN/ADefaultDecode<Impl>::skidInsert(unsigned tid) 3952292SN/A{ 3962292SN/A DynInstPtr inst = NULL; 3972292SN/A 3982292SN/A while (!insts[tid].empty()) { 3992292SN/A inst = insts[tid].front(); 4002292SN/A 4012292SN/A insts[tid].pop(); 4022292SN/A 4032292SN/A assert(tid == inst->threadNumber); 4042292SN/A 4052292SN/A DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 4062292SN/A inst->seqNum, inst->readPC(), inst->threadNumber); 4072292SN/A 4082292SN/A skidBuffer[tid].push(inst); 4092292SN/A } 4102292SN/A 4112329SN/A // @todo: Eventually need to enforce this by not letting a thread 4122292SN/A // fetch past its skidbuffer 4132292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4142292SN/A} 4152292SN/A 4162292SN/Atemplate<class Impl> 4172292SN/Abool 4182292SN/ADefaultDecode<Impl>::skidsEmpty() 4192292SN/A{ 4203867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4213867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4222292SN/A 4233867Sbinkertn@umich.edu while (threads != end) { 4243867Sbinkertn@umich.edu unsigned tid = *threads++; 4253867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4262292SN/A return false; 4272292SN/A } 4282292SN/A 4292292SN/A return true; 4302292SN/A} 4312292SN/A 4322292SN/Atemplate<class Impl> 4332292SN/Avoid 4342292SN/ADefaultDecode<Impl>::updateStatus() 4352292SN/A{ 4362292SN/A bool any_unblocking = false; 4372292SN/A 4383867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4393867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4402292SN/A 4413867Sbinkertn@umich.edu while (threads != end) { 4422292SN/A unsigned tid = *threads++; 4432292SN/A 4442292SN/A if (decodeStatus[tid] == Unblocking) { 4452292SN/A any_unblocking = true; 4462292SN/A break; 4472292SN/A } 4482292SN/A } 4492292SN/A 4502292SN/A // Decode will have activity if it's unblocking. 4512292SN/A if (any_unblocking) { 4522292SN/A if (_status == Inactive) { 4532292SN/A _status = Active; 4542292SN/A 4552292SN/A DPRINTF(Activity, "Activating stage.\n"); 4562292SN/A 4572733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4582292SN/A } 4592292SN/A } else { 4602292SN/A // If it's not unblocking, then decode will not have any internal 4612292SN/A // activity. Switch it to inactive. 4622292SN/A if (_status == Active) { 4632292SN/A _status = Inactive; 4642292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4652292SN/A 4662733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4672292SN/A } 4682292SN/A } 4692292SN/A} 4702292SN/A 4712292SN/Atemplate <class Impl> 4722292SN/Avoid 4732292SN/ADefaultDecode<Impl>::sortInsts() 4742292SN/A{ 4752292SN/A int insts_from_fetch = fromFetch->size; 4762329SN/A#ifdef DEBUG 4772292SN/A for (int i=0; i < numThreads; i++) 4782292SN/A assert(insts[i].empty()); 4792329SN/A#endif 4802292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4812292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4821060SN/A } 4831060SN/A} 4841060SN/A 4851060SN/Atemplate<class Impl> 4861060SN/Avoid 4872292SN/ADefaultDecode<Impl>::readStallSignals(unsigned tid) 4881060SN/A{ 4892292SN/A if (fromRename->renameBlock[tid]) { 4902292SN/A stalls[tid].rename = true; 4912292SN/A } 4921060SN/A 4932292SN/A if (fromRename->renameUnblock[tid]) { 4942292SN/A assert(stalls[tid].rename); 4952292SN/A stalls[tid].rename = false; 4962292SN/A } 4971060SN/A 4982292SN/A if (fromIEW->iewBlock[tid]) { 4992292SN/A stalls[tid].iew = true; 5002292SN/A } 5011062SN/A 5022292SN/A if (fromIEW->iewUnblock[tid]) { 5032292SN/A assert(stalls[tid].iew); 5042292SN/A stalls[tid].iew = false; 5052292SN/A } 5061061SN/A 5072292SN/A if (fromCommit->commitBlock[tid]) { 5082292SN/A stalls[tid].commit = true; 5092292SN/A } 5101062SN/A 5112292SN/A if (fromCommit->commitUnblock[tid]) { 5122292SN/A assert(stalls[tid].commit); 5132292SN/A stalls[tid].commit = false; 5142292SN/A } 5152292SN/A} 5161060SN/A 5172292SN/Atemplate <class Impl> 5182292SN/Abool 5192292SN/ADefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 5202292SN/A{ 5212292SN/A // Check if there's a squash signal, squash if there is. 5222292SN/A // Check stall signals, block if necessary. 5232292SN/A // If status was blocked 5242292SN/A // Check if stall conditions have passed 5252292SN/A // if so then go to unblocking 5262292SN/A // If status was Squashing 5272292SN/A // check if squashing is not high. Switch to running this cycle. 5281060SN/A 5292292SN/A // Update the per thread stall statuses. 5302292SN/A readStallSignals(tid); 5311060SN/A 5322292SN/A // Check squash signals from commit. 5332292SN/A if (fromCommit->commitInfo[tid].squash) { 5341681SN/A 5352292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5362292SN/A "from commit.\n", tid); 5372292SN/A 5382292SN/A squash(tid); 5392292SN/A 5402292SN/A return true; 5412292SN/A } 5422292SN/A 5432292SN/A // Check ROB squash signals from commit. 5442292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5452703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5462292SN/A 5472292SN/A // Continue to squash. 5482292SN/A decodeStatus[tid] = Squashing; 5492292SN/A 5502292SN/A return true; 5512292SN/A } 5522292SN/A 5532292SN/A if (checkStall(tid)) { 5542292SN/A return block(tid); 5552292SN/A } 5562292SN/A 5572292SN/A if (decodeStatus[tid] == Blocked) { 5582292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5592292SN/A tid); 5602292SN/A 5612292SN/A decodeStatus[tid] = Unblocking; 5622292SN/A 5632292SN/A unblock(tid); 5642292SN/A 5652292SN/A return true; 5662292SN/A } 5672292SN/A 5682292SN/A if (decodeStatus[tid] == Squashing) { 5692292SN/A // Switch status to running if decode isn't being told to block or 5702292SN/A // squash this cycle. 5712292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5722292SN/A tid); 5732292SN/A 5742292SN/A decodeStatus[tid] = Running; 5752292SN/A 5762292SN/A return false; 5772292SN/A } 5782292SN/A 5792292SN/A // If we've reached this point, we have not gotten any signals that 5802292SN/A // cause decode to change its status. Decode remains the same as before. 5812292SN/A return false; 5822292SN/A} 5832292SN/A 5842292SN/Atemplate<class Impl> 5852292SN/Avoid 5862292SN/ADefaultDecode<Impl>::tick() 5872292SN/A{ 5882292SN/A wroteToTimeBuffer = false; 5892292SN/A 5902292SN/A bool status_change = false; 5912292SN/A 5922292SN/A toRenameIndex = 0; 5932292SN/A 5943867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 5953867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 5962292SN/A 5972292SN/A sortInsts(); 5982292SN/A 5992292SN/A //Check stall and squash signals. 6003867Sbinkertn@umich.edu while (threads != end) { 6013867Sbinkertn@umich.edu unsigned tid = *threads++; 6022292SN/A 6032292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 6042292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 6052292SN/A 6062292SN/A decode(status_change, tid); 6072292SN/A } 6082292SN/A 6092292SN/A if (status_change) { 6102292SN/A updateStatus(); 6112292SN/A } 6122292SN/A 6132292SN/A if (wroteToTimeBuffer) { 6142292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 6152292SN/A 6162292SN/A cpu->activityThisCycle(); 6171060SN/A } 6181060SN/A} 6191060SN/A 6201060SN/Atemplate<class Impl> 6211060SN/Avoid 6222292SN/ADefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 6231060SN/A{ 6242292SN/A // If status is Running or idle, 6252292SN/A // call decodeInsts() 6262292SN/A // If status is Unblocking, 6272292SN/A // buffer any instructions coming from fetch 6282292SN/A // continue trying to empty skid buffer 6292292SN/A // check if stall conditions have passed 6302292SN/A 6312292SN/A if (decodeStatus[tid] == Blocked) { 6322292SN/A ++decodeBlockedCycles; 6332292SN/A } else if (decodeStatus[tid] == Squashing) { 6342292SN/A ++decodeSquashCycles; 6351060SN/A } 6361060SN/A 6372292SN/A // Decode should try to decode as many instructions as its bandwidth 6382292SN/A // will allow, as long as it is not currently blocked. 6392292SN/A if (decodeStatus[tid] == Running || 6402292SN/A decodeStatus[tid] == Idle) { 6412935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6422292SN/A "stage.\n",tid); 6432292SN/A 6442292SN/A decodeInsts(tid); 6452292SN/A } else if (decodeStatus[tid] == Unblocking) { 6462292SN/A // Make sure that the skid buffer has something in it if the 6472292SN/A // status is unblocking. 6482292SN/A assert(!skidsEmpty()); 6492292SN/A 6502292SN/A // If the status was unblocking, then instructions from the skid 6512292SN/A // buffer were used. Remove those instructions and handle 6522292SN/A // the rest of unblocking. 6532292SN/A decodeInsts(tid); 6542292SN/A 6552292SN/A if (fetchInstsValid()) { 6562292SN/A // Add the current inputs to the skid buffer so they can be 6572292SN/A // reprocessed when this stage unblocks. 6582292SN/A skidInsert(tid); 6592292SN/A } 6602292SN/A 6612292SN/A status_change = unblock(tid) || status_change; 6621060SN/A } 6632292SN/A} 6641060SN/A 6652292SN/Atemplate <class Impl> 6662292SN/Avoid 6672292SN/ADefaultDecode<Impl>::decodeInsts(unsigned tid) 6682292SN/A{ 6692292SN/A // Instructions can come either from the skid buffer or the list of 6702292SN/A // instructions coming from fetch, depending on decode's status. 6712292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6722292SN/A skidBuffer[tid].size() : insts[tid].size(); 6732292SN/A 6742292SN/A if (insts_available == 0) { 6752292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6762292SN/A " early.\n",tid); 6771060SN/A // Should I change the status to idle? 6781062SN/A ++decodeIdleCycles; 6791060SN/A return; 6802292SN/A } else if (decodeStatus[tid] == Unblocking) { 6812292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6822292SN/A "buffer.\n",tid); 6832292SN/A ++decodeUnblockCycles; 6842292SN/A } else if (decodeStatus[tid] == Running) { 6852292SN/A ++decodeRunCycles; 6861060SN/A } 6871060SN/A 6881061SN/A DynInstPtr inst; 6891061SN/A 6902292SN/A std::queue<DynInstPtr> 6912292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6922292SN/A skidBuffer[tid] : insts[tid]; 6931061SN/A 6942292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6951060SN/A 6962292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6972292SN/A assert(!insts_to_decode.empty()); 6981060SN/A 6992292SN/A inst = insts_to_decode.front(); 7001062SN/A 7012292SN/A insts_to_decode.pop(); 7021061SN/A 7032292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 7042292SN/A "PC %#x\n", 7052292SN/A tid, inst->seqNum, inst->readPC()); 7061061SN/A 7071061SN/A if (inst->isSquashed()) { 7082292SN/A DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 7091061SN/A "squashed, skipping.\n", 7102292SN/A tid, inst->seqNum, inst->readPC()); 7111061SN/A 7121062SN/A ++decodeSquashedInsts; 7131062SN/A 7141061SN/A --insts_available; 7151061SN/A 7161061SN/A continue; 7171061SN/A } 7181060SN/A 7191681SN/A // Also check if instructions have no source registers. Mark 7201681SN/A // them as ready to issue at any time. Not sure if this check 7211681SN/A // should exist here or at a later stage; however it doesn't matter 7221681SN/A // too much for function correctness. 7231681SN/A if (inst->numSrcRegs() == 0) { 7241681SN/A inst->setCanIssue(); 7251681SN/A } 7261681SN/A 7271060SN/A // This current instruction is valid, so add it into the decode 7281060SN/A // queue. The next instruction may not be valid, so check to 7291060SN/A // see if branches were predicted correctly. 7302292SN/A toRename->insts[toRenameIndex] = inst; 7311061SN/A 7321061SN/A ++(toRename->size); 7332292SN/A ++toRenameIndex; 7342292SN/A ++decodeDecodedInsts; 7352292SN/A --insts_available; 7361060SN/A 7371060SN/A // Ensure that if it was predicted as a branch, it really is a 7381061SN/A // branch. 7393796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7403967Sgblack@eecs.umich.edu DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 7413967Sgblack@eecs.umich.edu inst->readPredPC(), inst->readNextPC() + 4); 7422935Sksewell@umich.edu 7431060SN/A panic("Instruction predicted as a branch!"); 7441060SN/A 7451062SN/A ++decodeControlMispred; 7462292SN/A 7471060SN/A // Might want to set some sort of boolean and just do 7481060SN/A // a check at the end 7492292SN/A squash(inst, inst->threadNumber); 7502292SN/A 7511060SN/A break; 7521060SN/A } 7531060SN/A 7541062SN/A // Go ahead and compute any PC-relative branches. 7551063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7562307SN/A ++decodeBranchResolved; 7571062SN/A 7583796Sgblack@eecs.umich.edu if (inst->branchTarget() != inst->readPredPC()) { 7591062SN/A ++decodeBranchMispred; 7602292SN/A 7611060SN/A // Might want to set some sort of boolean and just do 7621060SN/A // a check at the end 7633093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 7642292SN/A squash(inst, inst->threadNumber); 7653796Sgblack@eecs.umich.edu Addr target = inst->branchTarget(); 7663796Sgblack@eecs.umich.edu inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 7672935Sksewell@umich.edu break; 7682935Sksewell@umich.edu#else 7692935Sksewell@umich.edu // If mispredicted as taken, then ignore delay slot 7702935Sksewell@umich.edu // instruction... else keep delay slot and squash 7712935Sksewell@umich.edu // after it is sent to rename 7723796Sgblack@eecs.umich.edu if (inst->readPredTaken() && inst->isCondDelaySlot()) { 7732935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 7742935Sksewell@umich.edu "[sn:%i] PC %#x mispredicted as taken.\n", tid, 7752935Sksewell@umich.edu inst->seqNum, inst->PC); 7762935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum; 7772935Sksewell@umich.edu squash(inst, inst->threadNumber); 7783796Sgblack@eecs.umich.edu Addr target = inst->branchTarget(); 7793796Sgblack@eecs.umich.edu inst->setPredTarg(target, 7803796Sgblack@eecs.umich.edu target + sizeof(TheISA::MachInst)); 7812935Sksewell@umich.edu break; 7822935Sksewell@umich.edu } else { 7832935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 7842935Sksewell@umich.edu "[sn:%i] PC %#x, will squash after delay slot " 7852935Sksewell@umich.edu "inst. is sent to Rename\n", 7862935Sksewell@umich.edu tid, inst->seqNum, inst->PC); 7872935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum + 1; 7882935Sksewell@umich.edu squashAfterDelaySlot[tid] = true; 7892935Sksewell@umich.edu squashInst[tid] = inst; 7902935Sksewell@umich.edu continue; 7912935Sksewell@umich.edu } 7922935Sksewell@umich.edu#endif 7932935Sksewell@umich.edu } 7942935Sksewell@umich.edu } 7952292SN/A 7962935Sksewell@umich.edu if (squashAfterDelaySlot[tid]) { 7972935Sksewell@umich.edu assert(!inst->isSquashed()); 7982935Sksewell@umich.edu squash(squashInst[tid], squashInst[tid]->threadNumber); 7993796Sgblack@eecs.umich.edu Addr target = squashInst[tid]->branchTarget(); 8003796Sgblack@eecs.umich.edu squashInst[tid]->setPredTarg(target, 8013796Sgblack@eecs.umich.edu target + sizeof(TheISA::MachInst)); 8022935Sksewell@umich.edu assert(!inst->isSquashed()); 8032935Sksewell@umich.edu break; 8041060SN/A } 8051060SN/A } 8061061SN/A 8072292SN/A // If we didn't process all instructions, then we will need to block 8082292SN/A // and put all those instructions into the skid buffer. 8092292SN/A if (!insts_to_decode.empty()) { 8102292SN/A block(tid); 8112292SN/A } 8122292SN/A 8132292SN/A // Record that decode has written to the time buffer for activity 8142292SN/A // tracking. 8152292SN/A if (toRenameIndex) { 8162292SN/A wroteToTimeBuffer = true; 8172292SN/A } 8181060SN/A} 819