decode_impl.hh revision 3967
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311717SN/A#include "cpu/o3/decode.hh" 321060SN/A 331060SN/Atemplate<class Impl> 342292SN/ADefaultDecode<Impl>::DefaultDecode(Params *params) 352292SN/A : renameToDecodeDelay(params->renameToDecodeDelay), 362292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 372292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 382292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 392292SN/A decodeWidth(params->decodeWidth), 402292SN/A numThreads(params->numberOfThreads) 411060SN/A{ 422292SN/A _status = Inactive; 432292SN/A 442348SN/A // Setup status, make sure stall signals are clear. 452292SN/A for (int i = 0; i < numThreads; ++i) { 462292SN/A decodeStatus[i] = Idle; 472292SN/A 482292SN/A stalls[i].rename = false; 492292SN/A stalls[i].iew = false; 502292SN/A stalls[i].commit = false; 512935Sksewell@umich.edu 522935Sksewell@umich.edu squashAfterDelaySlot[i] = false; 532292SN/A } 542292SN/A 552292SN/A // @todo: Make into a parameter 562292SN/A skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 572292SN/A} 582292SN/A 592292SN/Atemplate <class Impl> 602292SN/Astd::string 612292SN/ADefaultDecode<Impl>::name() const 622292SN/A{ 632292SN/A return cpu->name() + ".decode"; 641060SN/A} 651060SN/A 661062SN/Atemplate <class Impl> 671062SN/Avoid 682292SN/ADefaultDecode<Impl>::regStats() 691062SN/A{ 701062SN/A decodeIdleCycles 712307SN/A .name(name() + ".DECODE:IdleCycles") 721062SN/A .desc("Number of cycles decode is idle") 731062SN/A .prereq(decodeIdleCycles); 741062SN/A decodeBlockedCycles 752307SN/A .name(name() + ".DECODE:BlockedCycles") 761062SN/A .desc("Number of cycles decode is blocked") 771062SN/A .prereq(decodeBlockedCycles); 782292SN/A decodeRunCycles 792307SN/A .name(name() + ".DECODE:RunCycles") 802292SN/A .desc("Number of cycles decode is running") 812292SN/A .prereq(decodeRunCycles); 821062SN/A decodeUnblockCycles 832307SN/A .name(name() + ".DECODE:UnblockCycles") 841062SN/A .desc("Number of cycles decode is unblocking") 851062SN/A .prereq(decodeUnblockCycles); 861062SN/A decodeSquashCycles 872307SN/A .name(name() + ".DECODE:SquashCycles") 881062SN/A .desc("Number of cycles decode is squashing") 891062SN/A .prereq(decodeSquashCycles); 902307SN/A decodeBranchResolved 912307SN/A .name(name() + ".DECODE:BranchResolved") 922307SN/A .desc("Number of times decode resolved a branch") 932307SN/A .prereq(decodeBranchResolved); 941062SN/A decodeBranchMispred 952307SN/A .name(name() + ".DECODE:BranchMispred") 961062SN/A .desc("Number of times decode detected a branch misprediction") 971062SN/A .prereq(decodeBranchMispred); 981062SN/A decodeControlMispred 992307SN/A .name(name() + ".DECODE:ControlMispred") 1001062SN/A .desc("Number of times decode detected an instruction incorrectly" 1011062SN/A " predicted as a control") 1021062SN/A .prereq(decodeControlMispred); 1031062SN/A decodeDecodedInsts 1042307SN/A .name(name() + ".DECODE:DecodedInsts") 1051062SN/A .desc("Number of instructions handled by decode") 1061062SN/A .prereq(decodeDecodedInsts); 1071062SN/A decodeSquashedInsts 1082307SN/A .name(name() + ".DECODE:SquashedInsts") 1091062SN/A .desc("Number of squashed instructions handled by decode") 1101062SN/A .prereq(decodeSquashedInsts); 1111062SN/A} 1121062SN/A 1131060SN/Atemplate<class Impl> 1141060SN/Avoid 1152733Sktlim@umich.eduDefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 1161060SN/A{ 1172292SN/A DPRINTF(Decode, "Setting CPU pointer.\n"); 1181060SN/A cpu = cpu_ptr; 1191060SN/A} 1201060SN/A 1211060SN/Atemplate<class Impl> 1221060SN/Avoid 1232292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1241060SN/A{ 1252292SN/A DPRINTF(Decode, "Setting time buffer pointer.\n"); 1261060SN/A timeBuffer = tb_ptr; 1271060SN/A 1281060SN/A // Setup wire to write information back to fetch. 1291060SN/A toFetch = timeBuffer->getWire(0); 1301060SN/A 1311060SN/A // Create wires to get information from proper places in time buffer. 1321060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1331060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1341060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1351060SN/A} 1361060SN/A 1371060SN/Atemplate<class Impl> 1381060SN/Avoid 1392292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1401060SN/A{ 1412292SN/A DPRINTF(Decode, "Setting decode queue pointer.\n"); 1421060SN/A decodeQueue = dq_ptr; 1431060SN/A 1441060SN/A // Setup wire to write information to proper place in decode queue. 1451060SN/A toRename = decodeQueue->getWire(0); 1461060SN/A} 1471060SN/A 1481060SN/Atemplate<class Impl> 1491060SN/Avoid 1502292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1511060SN/A{ 1522292SN/A DPRINTF(Decode, "Setting fetch queue pointer.\n"); 1531060SN/A fetchQueue = fq_ptr; 1541060SN/A 1551060SN/A // Setup wire to read information from fetch queue. 1561060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1571060SN/A} 1581060SN/A 1591060SN/Atemplate<class Impl> 1602292SN/Avoid 1612980Sgblack@eecs.umich.eduDefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 1622292SN/A{ 1632292SN/A DPRINTF(Decode, "Setting active threads list pointer.\n"); 1642292SN/A activeThreads = at_ptr; 1652292SN/A} 1662292SN/A 1672307SN/Atemplate <class Impl> 1682863Sktlim@umich.edubool 1692843Sktlim@umich.eduDefaultDecode<Impl>::drain() 1702307SN/A{ 1712843Sktlim@umich.edu // Decode is done draining at any time. 1722843Sktlim@umich.edu cpu->signalDrained(); 1732863Sktlim@umich.edu return true; 1742307SN/A} 1752307SN/A 1762307SN/Atemplate <class Impl> 1772307SN/Avoid 1782307SN/ADefaultDecode<Impl>::takeOverFrom() 1792307SN/A{ 1802307SN/A _status = Inactive; 1812307SN/A 1822348SN/A // Be sure to reset state and clear out any old instructions. 1832307SN/A for (int i = 0; i < numThreads; ++i) { 1842307SN/A decodeStatus[i] = Idle; 1852307SN/A 1862307SN/A stalls[i].rename = false; 1872307SN/A stalls[i].iew = false; 1882307SN/A stalls[i].commit = false; 1892307SN/A while (!insts[i].empty()) 1902307SN/A insts[i].pop(); 1912307SN/A while (!skidBuffer[i].empty()) 1922307SN/A skidBuffer[i].pop(); 1932307SN/A branchCount[i] = 0; 1942307SN/A } 1952307SN/A wroteToTimeBuffer = false; 1962307SN/A} 1972307SN/A 1982292SN/Atemplate<class Impl> 1992292SN/Abool 2002292SN/ADefaultDecode<Impl>::checkStall(unsigned tid) const 2012292SN/A{ 2022292SN/A bool ret_val = false; 2032292SN/A 2042292SN/A if (stalls[tid].rename) { 2052292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2062292SN/A ret_val = true; 2072292SN/A } else if (stalls[tid].iew) { 2082292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2092292SN/A ret_val = true; 2102292SN/A } else if (stalls[tid].commit) { 2112292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2122292SN/A ret_val = true; 2132292SN/A } 2142292SN/A 2152292SN/A return ret_val; 2162292SN/A} 2172292SN/A 2182292SN/Atemplate<class Impl> 2191681SN/Ainline bool 2202292SN/ADefaultDecode<Impl>::fetchInstsValid() 2211681SN/A{ 2221681SN/A return fromFetch->size > 0; 2231681SN/A} 2241681SN/A 2251681SN/Atemplate<class Impl> 2262292SN/Abool 2272292SN/ADefaultDecode<Impl>::block(unsigned tid) 2281060SN/A{ 2292292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2301060SN/A 2311060SN/A // Add the current inputs to the skid buffer so they can be 2321060SN/A // reprocessed when this stage unblocks. 2332292SN/A skidInsert(tid); 2341060SN/A 2352348SN/A // If the decode status is blocked or unblocking then decode has not yet 2362348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2372348SN/A // fetch to block. 2382292SN/A if (decodeStatus[tid] != Blocked) { 2392292SN/A // Set the status to Blocked. 2402292SN/A decodeStatus[tid] = Blocked; 2412348SN/A 2422348SN/A if (decodeStatus[tid] != Unblocking) { 2432348SN/A toFetch->decodeBlock[tid] = true; 2442348SN/A wroteToTimeBuffer = true; 2452348SN/A } 2462348SN/A 2472292SN/A return true; 2482292SN/A } 2492292SN/A 2502292SN/A return false; 2511060SN/A} 2521060SN/A 2531060SN/Atemplate<class Impl> 2542292SN/Abool 2552292SN/ADefaultDecode<Impl>::unblock(unsigned tid) 2561060SN/A{ 2572292SN/A // Decode is done unblocking only if the skid buffer is empty. 2582292SN/A if (skidBuffer[tid].empty()) { 2592292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2602292SN/A toFetch->decodeUnblock[tid] = true; 2612292SN/A wroteToTimeBuffer = true; 2621060SN/A 2632292SN/A decodeStatus[tid] = Running; 2642292SN/A return true; 2651060SN/A } 2661681SN/A 2672329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2682329SN/A 2692292SN/A return false; 2701060SN/A} 2711060SN/A 2721060SN/Atemplate<class Impl> 2731060SN/Avoid 2742292SN/ADefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 2751060SN/A{ 2762292SN/A DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 2772292SN/A "detected at decode.\n", tid); 2782292SN/A 2792348SN/A // Send back mispredict information. 2802292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2812935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2822292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2832292SN/A toFetch->decodeInfo[tid].squash = true; 2842678Sktlim@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2853967Sgblack@eecs.umich.edu ///FIXME There needs to be a way to set the nextPC and nextNPC 2863967Sgblack@eecs.umich.edu ///explicitly for ISAs with delay slots. 2873967Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].nextNPC = 2883967Sgblack@eecs.umich.edu inst->branchTarget() + sizeof(TheISA::MachInst); 2893093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 2902935Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 2912935Sksewell@umich.edu (inst->readNextPC() + sizeof(TheISA::MachInst)); 2922935Sksewell@umich.edu 2932935Sksewell@umich.edu toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 2942935Sksewell@umich.edu squashAfterDelaySlot[tid] = false; 2952935Sksewell@umich.edu 2962935Sksewell@umich.edu InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 2973093Sksewell@umich.edu#else 2983093Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = 2993093Sksewell@umich.edu inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 3003093Sksewell@umich.edu 3013093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 3022935Sksewell@umich.edu#endif 3032935Sksewell@umich.edu 3042348SN/A // Might have to tell fetch to unblock. 3052292SN/A if (decodeStatus[tid] == Blocked || 3062292SN/A decodeStatus[tid] == Unblocking) { 3072292SN/A toFetch->decodeUnblock[tid] = 1; 3082292SN/A } 3092292SN/A 3101060SN/A // Set status to squashing. 3112292SN/A decodeStatus[tid] = Squashing; 3121060SN/A 3132292SN/A for (int i=0; i<fromFetch->size; i++) { 3142292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3152935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3162731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3172292SN/A } 3182292SN/A } 3192292SN/A 3202348SN/A // Clear the instruction list and skid buffer in case they have any 3212348SN/A // insts in them. 3222292SN/A while (!insts[tid].empty()) { 3232935Sksewell@umich.edu 3243093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3252935Sksewell@umich.edu if (insts[tid].front()->seqNum <= squash_seq_num) { 3262935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 3272935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3282935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3292935Sksewell@umich.edu insts[tid].size()); 3302935Sksewell@umich.edu break; 3312935Sksewell@umich.edu } 3322935Sksewell@umich.edu#endif 3332292SN/A insts[tid].pop(); 3342292SN/A } 3351060SN/A 3362292SN/A while (!skidBuffer[tid].empty()) { 3372935Sksewell@umich.edu 3383093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3392935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 3402935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 3412935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3422935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3432935Sksewell@umich.edu insts[tid].size()); 3442935Sksewell@umich.edu break; 3452935Sksewell@umich.edu } 3462935Sksewell@umich.edu#endif 3472292SN/A skidBuffer[tid].pop(); 3482292SN/A } 3492292SN/A 3502292SN/A // Squash instructions up until this one 3512935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3522292SN/A} 3532292SN/A 3542292SN/Atemplate<class Impl> 3552292SN/Aunsigned 3562292SN/ADefaultDecode<Impl>::squash(unsigned tid) 3572292SN/A{ 3582292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3592292SN/A 3602292SN/A if (decodeStatus[tid] == Blocked || 3612292SN/A decodeStatus[tid] == Unblocking) { 3622292SN/A#if !FULL_SYSTEM 3632292SN/A // In syscall emulation, we can have both a block and a squash due 3642292SN/A // to a syscall in the same cycle. This would cause both signals to 3652292SN/A // be high. This shouldn't happen in full system. 3662329SN/A // @todo: Determine if this still happens. 3672292SN/A if (toFetch->decodeBlock[tid]) { 3682292SN/A toFetch->decodeBlock[tid] = 0; 3692292SN/A } else { 3702292SN/A toFetch->decodeUnblock[tid] = 1; 3712292SN/A } 3722292SN/A#else 3732292SN/A toFetch->decodeUnblock[tid] = 1; 3742292SN/A#endif 3752292SN/A } 3762292SN/A 3772292SN/A // Set status to squashing. 3782292SN/A decodeStatus[tid] = Squashing; 3792292SN/A 3802292SN/A // Go through incoming instructions from fetch and squash them. 3812292SN/A unsigned squash_count = 0; 3822292SN/A 3832292SN/A for (int i=0; i<fromFetch->size; i++) { 3842292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3852731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3862292SN/A squash_count++; 3872292SN/A } 3882292SN/A } 3892292SN/A 3902348SN/A // Clear the instruction list and skid buffer in case they have any 3912348SN/A // insts in them. 3922292SN/A while (!insts[tid].empty()) { 3932292SN/A insts[tid].pop(); 3942292SN/A } 3952292SN/A 3962292SN/A while (!skidBuffer[tid].empty()) { 3972292SN/A skidBuffer[tid].pop(); 3982292SN/A } 3992292SN/A 4002292SN/A return squash_count; 4012292SN/A} 4022292SN/A 4032292SN/Atemplate<class Impl> 4042292SN/Avoid 4052292SN/ADefaultDecode<Impl>::skidInsert(unsigned tid) 4062292SN/A{ 4072292SN/A DynInstPtr inst = NULL; 4082292SN/A 4092292SN/A while (!insts[tid].empty()) { 4102292SN/A inst = insts[tid].front(); 4112292SN/A 4122292SN/A insts[tid].pop(); 4132292SN/A 4142292SN/A assert(tid == inst->threadNumber); 4152292SN/A 4162292SN/A DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 4172292SN/A inst->seqNum, inst->readPC(), inst->threadNumber); 4182292SN/A 4192292SN/A skidBuffer[tid].push(inst); 4202292SN/A } 4212292SN/A 4222329SN/A // @todo: Eventually need to enforce this by not letting a thread 4232292SN/A // fetch past its skidbuffer 4242292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4252292SN/A} 4262292SN/A 4272292SN/Atemplate<class Impl> 4282292SN/Abool 4292292SN/ADefaultDecode<Impl>::skidsEmpty() 4302292SN/A{ 4312980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4322292SN/A 4332292SN/A while (threads != (*activeThreads).end()) { 4342292SN/A if (!skidBuffer[*threads++].empty()) 4352292SN/A return false; 4362292SN/A } 4372292SN/A 4382292SN/A return true; 4392292SN/A} 4402292SN/A 4412292SN/Atemplate<class Impl> 4422292SN/Avoid 4432292SN/ADefaultDecode<Impl>::updateStatus() 4442292SN/A{ 4452292SN/A bool any_unblocking = false; 4462292SN/A 4472980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4482292SN/A 4492292SN/A threads = (*activeThreads).begin(); 4502292SN/A 4512292SN/A while (threads != (*activeThreads).end()) { 4522292SN/A unsigned tid = *threads++; 4532292SN/A 4542292SN/A if (decodeStatus[tid] == Unblocking) { 4552292SN/A any_unblocking = true; 4562292SN/A break; 4572292SN/A } 4582292SN/A } 4592292SN/A 4602292SN/A // Decode will have activity if it's unblocking. 4612292SN/A if (any_unblocking) { 4622292SN/A if (_status == Inactive) { 4632292SN/A _status = Active; 4642292SN/A 4652292SN/A DPRINTF(Activity, "Activating stage.\n"); 4662292SN/A 4672733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4682292SN/A } 4692292SN/A } else { 4702292SN/A // If it's not unblocking, then decode will not have any internal 4712292SN/A // activity. Switch it to inactive. 4722292SN/A if (_status == Active) { 4732292SN/A _status = Inactive; 4742292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4752292SN/A 4762733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4772292SN/A } 4782292SN/A } 4792292SN/A} 4802292SN/A 4812292SN/Atemplate <class Impl> 4822292SN/Avoid 4832292SN/ADefaultDecode<Impl>::sortInsts() 4842292SN/A{ 4852292SN/A int insts_from_fetch = fromFetch->size; 4862329SN/A#ifdef DEBUG 4872292SN/A for (int i=0; i < numThreads; i++) 4882292SN/A assert(insts[i].empty()); 4892329SN/A#endif 4902292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4912292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4921060SN/A } 4931060SN/A} 4941060SN/A 4951060SN/Atemplate<class Impl> 4961060SN/Avoid 4972292SN/ADefaultDecode<Impl>::readStallSignals(unsigned tid) 4981060SN/A{ 4992292SN/A if (fromRename->renameBlock[tid]) { 5002292SN/A stalls[tid].rename = true; 5012292SN/A } 5021060SN/A 5032292SN/A if (fromRename->renameUnblock[tid]) { 5042292SN/A assert(stalls[tid].rename); 5052292SN/A stalls[tid].rename = false; 5062292SN/A } 5071060SN/A 5082292SN/A if (fromIEW->iewBlock[tid]) { 5092292SN/A stalls[tid].iew = true; 5102292SN/A } 5111062SN/A 5122292SN/A if (fromIEW->iewUnblock[tid]) { 5132292SN/A assert(stalls[tid].iew); 5142292SN/A stalls[tid].iew = false; 5152292SN/A } 5161061SN/A 5172292SN/A if (fromCommit->commitBlock[tid]) { 5182292SN/A stalls[tid].commit = true; 5192292SN/A } 5201062SN/A 5212292SN/A if (fromCommit->commitUnblock[tid]) { 5222292SN/A assert(stalls[tid].commit); 5232292SN/A stalls[tid].commit = false; 5242292SN/A } 5252292SN/A} 5261060SN/A 5272292SN/Atemplate <class Impl> 5282292SN/Abool 5292292SN/ADefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 5302292SN/A{ 5312292SN/A // Check if there's a squash signal, squash if there is. 5322292SN/A // Check stall signals, block if necessary. 5332292SN/A // If status was blocked 5342292SN/A // Check if stall conditions have passed 5352292SN/A // if so then go to unblocking 5362292SN/A // If status was Squashing 5372292SN/A // check if squashing is not high. Switch to running this cycle. 5381060SN/A 5392292SN/A // Update the per thread stall statuses. 5402292SN/A readStallSignals(tid); 5411060SN/A 5422292SN/A // Check squash signals from commit. 5432292SN/A if (fromCommit->commitInfo[tid].squash) { 5441681SN/A 5452292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5462292SN/A "from commit.\n", tid); 5472292SN/A 5482292SN/A squash(tid); 5492292SN/A 5502292SN/A return true; 5512292SN/A } 5522292SN/A 5532292SN/A // Check ROB squash signals from commit. 5542292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5552703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5562292SN/A 5572292SN/A // Continue to squash. 5582292SN/A decodeStatus[tid] = Squashing; 5592292SN/A 5602292SN/A return true; 5612292SN/A } 5622292SN/A 5632292SN/A if (checkStall(tid)) { 5642292SN/A return block(tid); 5652292SN/A } 5662292SN/A 5672292SN/A if (decodeStatus[tid] == Blocked) { 5682292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5692292SN/A tid); 5702292SN/A 5712292SN/A decodeStatus[tid] = Unblocking; 5722292SN/A 5732292SN/A unblock(tid); 5742292SN/A 5752292SN/A return true; 5762292SN/A } 5772292SN/A 5782292SN/A if (decodeStatus[tid] == Squashing) { 5792292SN/A // Switch status to running if decode isn't being told to block or 5802292SN/A // squash this cycle. 5812292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5822292SN/A tid); 5832292SN/A 5842292SN/A decodeStatus[tid] = Running; 5852292SN/A 5862292SN/A return false; 5872292SN/A } 5882292SN/A 5892292SN/A // If we've reached this point, we have not gotten any signals that 5902292SN/A // cause decode to change its status. Decode remains the same as before. 5912292SN/A return false; 5922292SN/A} 5932292SN/A 5942292SN/Atemplate<class Impl> 5952292SN/Avoid 5962292SN/ADefaultDecode<Impl>::tick() 5972292SN/A{ 5982292SN/A wroteToTimeBuffer = false; 5992292SN/A 6002292SN/A bool status_change = false; 6012292SN/A 6022292SN/A toRenameIndex = 0; 6032292SN/A 6042980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 6052292SN/A 6062292SN/A sortInsts(); 6072292SN/A 6082292SN/A //Check stall and squash signals. 6092292SN/A while (threads != (*activeThreads).end()) { 6102292SN/A unsigned tid = *threads++; 6112292SN/A 6122292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 6132292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 6142292SN/A 6152292SN/A decode(status_change, tid); 6162292SN/A } 6172292SN/A 6182292SN/A if (status_change) { 6192292SN/A updateStatus(); 6202292SN/A } 6212292SN/A 6222292SN/A if (wroteToTimeBuffer) { 6232292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 6242292SN/A 6252292SN/A cpu->activityThisCycle(); 6261060SN/A } 6271060SN/A} 6281060SN/A 6291060SN/Atemplate<class Impl> 6301060SN/Avoid 6312292SN/ADefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 6321060SN/A{ 6332292SN/A // If status is Running or idle, 6342292SN/A // call decodeInsts() 6352292SN/A // If status is Unblocking, 6362292SN/A // buffer any instructions coming from fetch 6372292SN/A // continue trying to empty skid buffer 6382292SN/A // check if stall conditions have passed 6392292SN/A 6402292SN/A if (decodeStatus[tid] == Blocked) { 6412292SN/A ++decodeBlockedCycles; 6422292SN/A } else if (decodeStatus[tid] == Squashing) { 6432292SN/A ++decodeSquashCycles; 6441060SN/A } 6451060SN/A 6462292SN/A // Decode should try to decode as many instructions as its bandwidth 6472292SN/A // will allow, as long as it is not currently blocked. 6482292SN/A if (decodeStatus[tid] == Running || 6492292SN/A decodeStatus[tid] == Idle) { 6502935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6512292SN/A "stage.\n",tid); 6522292SN/A 6532292SN/A decodeInsts(tid); 6542292SN/A } else if (decodeStatus[tid] == Unblocking) { 6552292SN/A // Make sure that the skid buffer has something in it if the 6562292SN/A // status is unblocking. 6572292SN/A assert(!skidsEmpty()); 6582292SN/A 6592292SN/A // If the status was unblocking, then instructions from the skid 6602292SN/A // buffer were used. Remove those instructions and handle 6612292SN/A // the rest of unblocking. 6622292SN/A decodeInsts(tid); 6632292SN/A 6642292SN/A if (fetchInstsValid()) { 6652292SN/A // Add the current inputs to the skid buffer so they can be 6662292SN/A // reprocessed when this stage unblocks. 6672292SN/A skidInsert(tid); 6682292SN/A } 6692292SN/A 6702292SN/A status_change = unblock(tid) || status_change; 6711060SN/A } 6722292SN/A} 6731060SN/A 6742292SN/Atemplate <class Impl> 6752292SN/Avoid 6762292SN/ADefaultDecode<Impl>::decodeInsts(unsigned tid) 6772292SN/A{ 6782292SN/A // Instructions can come either from the skid buffer or the list of 6792292SN/A // instructions coming from fetch, depending on decode's status. 6802292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6812292SN/A skidBuffer[tid].size() : insts[tid].size(); 6822292SN/A 6832292SN/A if (insts_available == 0) { 6842292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6852292SN/A " early.\n",tid); 6861060SN/A // Should I change the status to idle? 6871062SN/A ++decodeIdleCycles; 6881060SN/A return; 6892292SN/A } else if (decodeStatus[tid] == Unblocking) { 6902292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6912292SN/A "buffer.\n",tid); 6922292SN/A ++decodeUnblockCycles; 6932292SN/A } else if (decodeStatus[tid] == Running) { 6942292SN/A ++decodeRunCycles; 6951060SN/A } 6961060SN/A 6971061SN/A DynInstPtr inst; 6981061SN/A 6992292SN/A std::queue<DynInstPtr> 7002292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 7012292SN/A skidBuffer[tid] : insts[tid]; 7021061SN/A 7032292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 7041060SN/A 7052292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 7062292SN/A assert(!insts_to_decode.empty()); 7071060SN/A 7082292SN/A inst = insts_to_decode.front(); 7091062SN/A 7102292SN/A insts_to_decode.pop(); 7111061SN/A 7122292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 7132292SN/A "PC %#x\n", 7142292SN/A tid, inst->seqNum, inst->readPC()); 7151061SN/A 7161061SN/A if (inst->isSquashed()) { 7172292SN/A DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 7181061SN/A "squashed, skipping.\n", 7192292SN/A tid, inst->seqNum, inst->readPC()); 7201061SN/A 7211062SN/A ++decodeSquashedInsts; 7221062SN/A 7231061SN/A --insts_available; 7241061SN/A 7251061SN/A continue; 7261061SN/A } 7271060SN/A 7281681SN/A // Also check if instructions have no source registers. Mark 7291681SN/A // them as ready to issue at any time. Not sure if this check 7301681SN/A // should exist here or at a later stage; however it doesn't matter 7311681SN/A // too much for function correctness. 7321681SN/A if (inst->numSrcRegs() == 0) { 7331681SN/A inst->setCanIssue(); 7341681SN/A } 7351681SN/A 7361060SN/A // This current instruction is valid, so add it into the decode 7371060SN/A // queue. The next instruction may not be valid, so check to 7381060SN/A // see if branches were predicted correctly. 7392292SN/A toRename->insts[toRenameIndex] = inst; 7401061SN/A 7411061SN/A ++(toRename->size); 7422292SN/A ++toRenameIndex; 7432292SN/A ++decodeDecodedInsts; 7442292SN/A --insts_available; 7451060SN/A 7461060SN/A // Ensure that if it was predicted as a branch, it really is a 7471061SN/A // branch. 7483796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7493967Sgblack@eecs.umich.edu DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 7503967Sgblack@eecs.umich.edu inst->readPredPC(), inst->readNextPC() + 4); 7512935Sksewell@umich.edu 7521060SN/A panic("Instruction predicted as a branch!"); 7531060SN/A 7541062SN/A ++decodeControlMispred; 7552292SN/A 7561060SN/A // Might want to set some sort of boolean and just do 7571060SN/A // a check at the end 7582292SN/A squash(inst, inst->threadNumber); 7592292SN/A 7601060SN/A break; 7611060SN/A } 7621060SN/A 7631062SN/A // Go ahead and compute any PC-relative branches. 7641063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7652307SN/A ++decodeBranchResolved; 7661062SN/A 7673796Sgblack@eecs.umich.edu if (inst->branchTarget() != inst->readPredPC()) { 7681062SN/A ++decodeBranchMispred; 7692292SN/A 7701060SN/A // Might want to set some sort of boolean and just do 7711060SN/A // a check at the end 7723093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 7732292SN/A squash(inst, inst->threadNumber); 7743796Sgblack@eecs.umich.edu Addr target = inst->branchTarget(); 7753796Sgblack@eecs.umich.edu inst->setPredTarg(target, target + sizeof(TheISA::MachInst)); 7762935Sksewell@umich.edu break; 7772935Sksewell@umich.edu#else 7782935Sksewell@umich.edu // If mispredicted as taken, then ignore delay slot 7792935Sksewell@umich.edu // instruction... else keep delay slot and squash 7802935Sksewell@umich.edu // after it is sent to rename 7813796Sgblack@eecs.umich.edu if (inst->readPredTaken() && inst->isCondDelaySlot()) { 7822935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 7832935Sksewell@umich.edu "[sn:%i] PC %#x mispredicted as taken.\n", tid, 7842935Sksewell@umich.edu inst->seqNum, inst->PC); 7852935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum; 7862935Sksewell@umich.edu squash(inst, inst->threadNumber); 7873796Sgblack@eecs.umich.edu Addr target = inst->branchTarget(); 7883796Sgblack@eecs.umich.edu inst->setPredTarg(target, 7893796Sgblack@eecs.umich.edu target + sizeof(TheISA::MachInst)); 7902935Sksewell@umich.edu break; 7912935Sksewell@umich.edu } else { 7922935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 7932935Sksewell@umich.edu "[sn:%i] PC %#x, will squash after delay slot " 7942935Sksewell@umich.edu "inst. is sent to Rename\n", 7952935Sksewell@umich.edu tid, inst->seqNum, inst->PC); 7962935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum + 1; 7972935Sksewell@umich.edu squashAfterDelaySlot[tid] = true; 7982935Sksewell@umich.edu squashInst[tid] = inst; 7992935Sksewell@umich.edu continue; 8002935Sksewell@umich.edu } 8012935Sksewell@umich.edu#endif 8022935Sksewell@umich.edu } 8032935Sksewell@umich.edu } 8042292SN/A 8052935Sksewell@umich.edu if (squashAfterDelaySlot[tid]) { 8062935Sksewell@umich.edu assert(!inst->isSquashed()); 8072935Sksewell@umich.edu squash(squashInst[tid], squashInst[tid]->threadNumber); 8083796Sgblack@eecs.umich.edu Addr target = squashInst[tid]->branchTarget(); 8093796Sgblack@eecs.umich.edu squashInst[tid]->setPredTarg(target, 8103796Sgblack@eecs.umich.edu target + sizeof(TheISA::MachInst)); 8112935Sksewell@umich.edu assert(!inst->isSquashed()); 8122935Sksewell@umich.edu break; 8131060SN/A } 8141060SN/A } 8151061SN/A 8162292SN/A // If we didn't process all instructions, then we will need to block 8172292SN/A // and put all those instructions into the skid buffer. 8182292SN/A if (!insts_to_decode.empty()) { 8192292SN/A block(tid); 8202292SN/A } 8212292SN/A 8222292SN/A // Record that decode has written to the time buffer for activity 8232292SN/A // tracking. 8242292SN/A if (toRenameIndex) { 8252292SN/A wroteToTimeBuffer = true; 8262292SN/A } 8271060SN/A} 828