decode_impl.hh revision 2935
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311717SN/A#include "cpu/o3/decode.hh" 321060SN/A 332292SN/Ausing namespace std; 342292SN/A 351060SN/Atemplate<class Impl> 362292SN/ADefaultDecode<Impl>::DefaultDecode(Params *params) 372292SN/A : renameToDecodeDelay(params->renameToDecodeDelay), 382292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 392292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 402292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 412292SN/A decodeWidth(params->decodeWidth), 422292SN/A numThreads(params->numberOfThreads) 431060SN/A{ 442292SN/A _status = Inactive; 452292SN/A 462348SN/A // Setup status, make sure stall signals are clear. 472292SN/A for (int i = 0; i < numThreads; ++i) { 482292SN/A decodeStatus[i] = Idle; 492292SN/A 502292SN/A stalls[i].rename = false; 512292SN/A stalls[i].iew = false; 522292SN/A stalls[i].commit = false; 532935Sksewell@umich.edu 542935Sksewell@umich.edu squashAfterDelaySlot[i] = false; 552292SN/A } 562292SN/A 572292SN/A // @todo: Make into a parameter 582292SN/A skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 592292SN/A} 602292SN/A 612292SN/Atemplate <class Impl> 622292SN/Astd::string 632292SN/ADefaultDecode<Impl>::name() const 642292SN/A{ 652292SN/A return cpu->name() + ".decode"; 661060SN/A} 671060SN/A 681062SN/Atemplate <class Impl> 691062SN/Avoid 702292SN/ADefaultDecode<Impl>::regStats() 711062SN/A{ 721062SN/A decodeIdleCycles 732307SN/A .name(name() + ".DECODE:IdleCycles") 741062SN/A .desc("Number of cycles decode is idle") 751062SN/A .prereq(decodeIdleCycles); 761062SN/A decodeBlockedCycles 772307SN/A .name(name() + ".DECODE:BlockedCycles") 781062SN/A .desc("Number of cycles decode is blocked") 791062SN/A .prereq(decodeBlockedCycles); 802292SN/A decodeRunCycles 812307SN/A .name(name() + ".DECODE:RunCycles") 822292SN/A .desc("Number of cycles decode is running") 832292SN/A .prereq(decodeRunCycles); 841062SN/A decodeUnblockCycles 852307SN/A .name(name() + ".DECODE:UnblockCycles") 861062SN/A .desc("Number of cycles decode is unblocking") 871062SN/A .prereq(decodeUnblockCycles); 881062SN/A decodeSquashCycles 892307SN/A .name(name() + ".DECODE:SquashCycles") 901062SN/A .desc("Number of cycles decode is squashing") 911062SN/A .prereq(decodeSquashCycles); 922307SN/A decodeBranchResolved 932307SN/A .name(name() + ".DECODE:BranchResolved") 942307SN/A .desc("Number of times decode resolved a branch") 952307SN/A .prereq(decodeBranchResolved); 961062SN/A decodeBranchMispred 972307SN/A .name(name() + ".DECODE:BranchMispred") 981062SN/A .desc("Number of times decode detected a branch misprediction") 991062SN/A .prereq(decodeBranchMispred); 1001062SN/A decodeControlMispred 1012307SN/A .name(name() + ".DECODE:ControlMispred") 1021062SN/A .desc("Number of times decode detected an instruction incorrectly" 1031062SN/A " predicted as a control") 1041062SN/A .prereq(decodeControlMispred); 1051062SN/A decodeDecodedInsts 1062307SN/A .name(name() + ".DECODE:DecodedInsts") 1071062SN/A .desc("Number of instructions handled by decode") 1081062SN/A .prereq(decodeDecodedInsts); 1091062SN/A decodeSquashedInsts 1102307SN/A .name(name() + ".DECODE:SquashedInsts") 1111062SN/A .desc("Number of squashed instructions handled by decode") 1121062SN/A .prereq(decodeSquashedInsts); 1131062SN/A} 1141062SN/A 1151060SN/Atemplate<class Impl> 1161060SN/Avoid 1172733Sktlim@umich.eduDefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr) 1181060SN/A{ 1192292SN/A DPRINTF(Decode, "Setting CPU pointer.\n"); 1201060SN/A cpu = cpu_ptr; 1211060SN/A} 1221060SN/A 1231060SN/Atemplate<class Impl> 1241060SN/Avoid 1252292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1261060SN/A{ 1272292SN/A DPRINTF(Decode, "Setting time buffer pointer.\n"); 1281060SN/A timeBuffer = tb_ptr; 1291060SN/A 1301060SN/A // Setup wire to write information back to fetch. 1311060SN/A toFetch = timeBuffer->getWire(0); 1321060SN/A 1331060SN/A // Create wires to get information from proper places in time buffer. 1341060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1351060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1361060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1371060SN/A} 1381060SN/A 1391060SN/Atemplate<class Impl> 1401060SN/Avoid 1412292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1421060SN/A{ 1432292SN/A DPRINTF(Decode, "Setting decode queue pointer.\n"); 1441060SN/A decodeQueue = dq_ptr; 1451060SN/A 1461060SN/A // Setup wire to write information to proper place in decode queue. 1471060SN/A toRename = decodeQueue->getWire(0); 1481060SN/A} 1491060SN/A 1501060SN/Atemplate<class Impl> 1511060SN/Avoid 1522292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1531060SN/A{ 1542292SN/A DPRINTF(Decode, "Setting fetch queue pointer.\n"); 1551060SN/A fetchQueue = fq_ptr; 1561060SN/A 1571060SN/A // Setup wire to read information from fetch queue. 1581060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1591060SN/A} 1601060SN/A 1611060SN/Atemplate<class Impl> 1622292SN/Avoid 1632292SN/ADefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) 1642292SN/A{ 1652292SN/A DPRINTF(Decode, "Setting active threads list pointer.\n"); 1662292SN/A activeThreads = at_ptr; 1672292SN/A} 1682292SN/A 1692307SN/Atemplate <class Impl> 1702863Sktlim@umich.edubool 1712843Sktlim@umich.eduDefaultDecode<Impl>::drain() 1722307SN/A{ 1732843Sktlim@umich.edu // Decode is done draining at any time. 1742843Sktlim@umich.edu cpu->signalDrained(); 1752863Sktlim@umich.edu return true; 1762307SN/A} 1772307SN/A 1782307SN/Atemplate <class Impl> 1792307SN/Avoid 1802307SN/ADefaultDecode<Impl>::takeOverFrom() 1812307SN/A{ 1822307SN/A _status = Inactive; 1832307SN/A 1842348SN/A // Be sure to reset state and clear out any old instructions. 1852307SN/A for (int i = 0; i < numThreads; ++i) { 1862307SN/A decodeStatus[i] = Idle; 1872307SN/A 1882307SN/A stalls[i].rename = false; 1892307SN/A stalls[i].iew = false; 1902307SN/A stalls[i].commit = false; 1912307SN/A while (!insts[i].empty()) 1922307SN/A insts[i].pop(); 1932307SN/A while (!skidBuffer[i].empty()) 1942307SN/A skidBuffer[i].pop(); 1952307SN/A branchCount[i] = 0; 1962307SN/A } 1972307SN/A wroteToTimeBuffer = false; 1982307SN/A} 1992307SN/A 2002292SN/Atemplate<class Impl> 2012292SN/Abool 2022292SN/ADefaultDecode<Impl>::checkStall(unsigned tid) const 2032292SN/A{ 2042292SN/A bool ret_val = false; 2052292SN/A 2062292SN/A if (stalls[tid].rename) { 2072292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2082292SN/A ret_val = true; 2092292SN/A } else if (stalls[tid].iew) { 2102292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2112292SN/A ret_val = true; 2122292SN/A } else if (stalls[tid].commit) { 2132292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2142292SN/A ret_val = true; 2152292SN/A } 2162292SN/A 2172292SN/A return ret_val; 2182292SN/A} 2192292SN/A 2202292SN/Atemplate<class Impl> 2211681SN/Ainline bool 2222292SN/ADefaultDecode<Impl>::fetchInstsValid() 2231681SN/A{ 2241681SN/A return fromFetch->size > 0; 2251681SN/A} 2261681SN/A 2271681SN/Atemplate<class Impl> 2282292SN/Abool 2292292SN/ADefaultDecode<Impl>::block(unsigned tid) 2301060SN/A{ 2312292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2321060SN/A 2331060SN/A // Add the current inputs to the skid buffer so they can be 2341060SN/A // reprocessed when this stage unblocks. 2352292SN/A skidInsert(tid); 2361060SN/A 2372348SN/A // If the decode status is blocked or unblocking then decode has not yet 2382348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2392348SN/A // fetch to block. 2402292SN/A if (decodeStatus[tid] != Blocked) { 2412292SN/A // Set the status to Blocked. 2422292SN/A decodeStatus[tid] = Blocked; 2432348SN/A 2442348SN/A if (decodeStatus[tid] != Unblocking) { 2452348SN/A toFetch->decodeBlock[tid] = true; 2462348SN/A wroteToTimeBuffer = true; 2472348SN/A } 2482348SN/A 2492292SN/A return true; 2502292SN/A } 2512292SN/A 2522292SN/A return false; 2531060SN/A} 2541060SN/A 2551060SN/Atemplate<class Impl> 2562292SN/Abool 2572292SN/ADefaultDecode<Impl>::unblock(unsigned tid) 2581060SN/A{ 2592292SN/A // Decode is done unblocking only if the skid buffer is empty. 2602292SN/A if (skidBuffer[tid].empty()) { 2612292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2622292SN/A toFetch->decodeUnblock[tid] = true; 2632292SN/A wroteToTimeBuffer = true; 2641060SN/A 2652292SN/A decodeStatus[tid] = Running; 2662292SN/A return true; 2671060SN/A } 2681681SN/A 2692329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2702329SN/A 2712292SN/A return false; 2721060SN/A} 2731060SN/A 2741060SN/Atemplate<class Impl> 2751060SN/Avoid 2762292SN/ADefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 2771060SN/A{ 2782292SN/A DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 2792292SN/A "detected at decode.\n", tid); 2802292SN/A 2812348SN/A // Send back mispredict information. 2822292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2832935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2842292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2852292SN/A toFetch->decodeInfo[tid].squash = true; 2862678Sktlim@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2872935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 2882348SN/A toFetch->decodeInfo[tid].branchTaken = 2892348SN/A inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 2902292SN/A 2912935Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 2922935Sksewell@umich.edu#else 2932935Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 2942935Sksewell@umich.edu (inst->readNextPC() + sizeof(TheISA::MachInst)); 2952935Sksewell@umich.edu 2962935Sksewell@umich.edu toFetch->decodeInfo[tid].bdelayDoneSeqNum = bdelayDoneSeqNum[tid]; 2972935Sksewell@umich.edu squashAfterDelaySlot[tid] = false; 2982935Sksewell@umich.edu 2992935Sksewell@umich.edu InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; 3002935Sksewell@umich.edu#endif 3012935Sksewell@umich.edu 3022348SN/A // Might have to tell fetch to unblock. 3032292SN/A if (decodeStatus[tid] == Blocked || 3042292SN/A decodeStatus[tid] == Unblocking) { 3052292SN/A toFetch->decodeUnblock[tid] = 1; 3062292SN/A } 3072292SN/A 3081060SN/A // Set status to squashing. 3092292SN/A decodeStatus[tid] = Squashing; 3101060SN/A 3112292SN/A for (int i=0; i<fromFetch->size; i++) { 3122292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3132935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3142731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3152292SN/A } 3162292SN/A } 3172292SN/A 3182348SN/A // Clear the instruction list and skid buffer in case they have any 3192348SN/A // insts in them. 3202292SN/A while (!insts[tid].empty()) { 3212935Sksewell@umich.edu 3222935Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 3232935Sksewell@umich.edu if (insts[tid].front()->seqNum <= squash_seq_num) { 3242935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " 3252935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3262935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3272935Sksewell@umich.edu insts[tid].size()); 3282935Sksewell@umich.edu break; 3292935Sksewell@umich.edu } 3302935Sksewell@umich.edu#endif 3312292SN/A insts[tid].pop(); 3322292SN/A } 3331060SN/A 3342292SN/A while (!skidBuffer[tid].empty()) { 3352935Sksewell@umich.edu 3362935Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 3372935Sksewell@umich.edu if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { 3382935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " 3392935Sksewell@umich.edu "instructions before delay slot [sn:%i]. %i insts" 3402935Sksewell@umich.edu "left in decode.\n", tid, squash_seq_num, 3412935Sksewell@umich.edu insts[tid].size()); 3422935Sksewell@umich.edu break; 3432935Sksewell@umich.edu } 3442935Sksewell@umich.edu#endif 3452292SN/A skidBuffer[tid].pop(); 3462292SN/A } 3472292SN/A 3482292SN/A // Squash instructions up until this one 3492935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3502292SN/A} 3512292SN/A 3522292SN/Atemplate<class Impl> 3532292SN/Aunsigned 3542292SN/ADefaultDecode<Impl>::squash(unsigned tid) 3552292SN/A{ 3562292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3572292SN/A 3582292SN/A if (decodeStatus[tid] == Blocked || 3592292SN/A decodeStatus[tid] == Unblocking) { 3602292SN/A#if !FULL_SYSTEM 3612292SN/A // In syscall emulation, we can have both a block and a squash due 3622292SN/A // to a syscall in the same cycle. This would cause both signals to 3632292SN/A // be high. This shouldn't happen in full system. 3642329SN/A // @todo: Determine if this still happens. 3652292SN/A if (toFetch->decodeBlock[tid]) { 3662292SN/A toFetch->decodeBlock[tid] = 0; 3672292SN/A } else { 3682292SN/A toFetch->decodeUnblock[tid] = 1; 3692292SN/A } 3702292SN/A#else 3712292SN/A toFetch->decodeUnblock[tid] = 1; 3722292SN/A#endif 3732292SN/A } 3742292SN/A 3752292SN/A // Set status to squashing. 3762292SN/A decodeStatus[tid] = Squashing; 3772292SN/A 3782292SN/A // Go through incoming instructions from fetch and squash them. 3792292SN/A unsigned squash_count = 0; 3802292SN/A 3812292SN/A for (int i=0; i<fromFetch->size; i++) { 3822292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3832731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3842292SN/A squash_count++; 3852292SN/A } 3862292SN/A } 3872292SN/A 3882348SN/A // Clear the instruction list and skid buffer in case they have any 3892348SN/A // insts in them. 3902292SN/A while (!insts[tid].empty()) { 3912292SN/A insts[tid].pop(); 3922292SN/A } 3932292SN/A 3942292SN/A while (!skidBuffer[tid].empty()) { 3952292SN/A skidBuffer[tid].pop(); 3962292SN/A } 3972292SN/A 3982292SN/A return squash_count; 3992292SN/A} 4002292SN/A 4012292SN/Atemplate<class Impl> 4022292SN/Avoid 4032292SN/ADefaultDecode<Impl>::skidInsert(unsigned tid) 4042292SN/A{ 4052292SN/A DynInstPtr inst = NULL; 4062292SN/A 4072292SN/A while (!insts[tid].empty()) { 4082292SN/A inst = insts[tid].front(); 4092292SN/A 4102292SN/A insts[tid].pop(); 4112292SN/A 4122292SN/A assert(tid == inst->threadNumber); 4132292SN/A 4142292SN/A DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 4152292SN/A inst->seqNum, inst->readPC(), inst->threadNumber); 4162292SN/A 4172292SN/A skidBuffer[tid].push(inst); 4182292SN/A } 4192292SN/A 4202329SN/A // @todo: Eventually need to enforce this by not letting a thread 4212292SN/A // fetch past its skidbuffer 4222292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4232292SN/A} 4242292SN/A 4252292SN/Atemplate<class Impl> 4262292SN/Abool 4272292SN/ADefaultDecode<Impl>::skidsEmpty() 4282292SN/A{ 4292292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4302292SN/A 4312292SN/A while (threads != (*activeThreads).end()) { 4322292SN/A if (!skidBuffer[*threads++].empty()) 4332292SN/A return false; 4342292SN/A } 4352292SN/A 4362292SN/A return true; 4372292SN/A} 4382292SN/A 4392292SN/Atemplate<class Impl> 4402292SN/Avoid 4412292SN/ADefaultDecode<Impl>::updateStatus() 4422292SN/A{ 4432292SN/A bool any_unblocking = false; 4442292SN/A 4452292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4462292SN/A 4472292SN/A threads = (*activeThreads).begin(); 4482292SN/A 4492292SN/A while (threads != (*activeThreads).end()) { 4502292SN/A unsigned tid = *threads++; 4512292SN/A 4522292SN/A if (decodeStatus[tid] == Unblocking) { 4532292SN/A any_unblocking = true; 4542292SN/A break; 4552292SN/A } 4562292SN/A } 4572292SN/A 4582292SN/A // Decode will have activity if it's unblocking. 4592292SN/A if (any_unblocking) { 4602292SN/A if (_status == Inactive) { 4612292SN/A _status = Active; 4622292SN/A 4632292SN/A DPRINTF(Activity, "Activating stage.\n"); 4642292SN/A 4652733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4662292SN/A } 4672292SN/A } else { 4682292SN/A // If it's not unblocking, then decode will not have any internal 4692292SN/A // activity. Switch it to inactive. 4702292SN/A if (_status == Active) { 4712292SN/A _status = Inactive; 4722292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4732292SN/A 4742733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4752292SN/A } 4762292SN/A } 4772292SN/A} 4782292SN/A 4792292SN/Atemplate <class Impl> 4802292SN/Avoid 4812292SN/ADefaultDecode<Impl>::sortInsts() 4822292SN/A{ 4832292SN/A int insts_from_fetch = fromFetch->size; 4842329SN/A#ifdef DEBUG 4852292SN/A for (int i=0; i < numThreads; i++) 4862292SN/A assert(insts[i].empty()); 4872329SN/A#endif 4882292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4892292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4901060SN/A } 4911060SN/A} 4921060SN/A 4931060SN/Atemplate<class Impl> 4941060SN/Avoid 4952292SN/ADefaultDecode<Impl>::readStallSignals(unsigned tid) 4961060SN/A{ 4972292SN/A if (fromRename->renameBlock[tid]) { 4982292SN/A stalls[tid].rename = true; 4992292SN/A } 5001060SN/A 5012292SN/A if (fromRename->renameUnblock[tid]) { 5022292SN/A assert(stalls[tid].rename); 5032292SN/A stalls[tid].rename = false; 5042292SN/A } 5051060SN/A 5062292SN/A if (fromIEW->iewBlock[tid]) { 5072292SN/A stalls[tid].iew = true; 5082292SN/A } 5091062SN/A 5102292SN/A if (fromIEW->iewUnblock[tid]) { 5112292SN/A assert(stalls[tid].iew); 5122292SN/A stalls[tid].iew = false; 5132292SN/A } 5141061SN/A 5152292SN/A if (fromCommit->commitBlock[tid]) { 5162292SN/A stalls[tid].commit = true; 5172292SN/A } 5181062SN/A 5192292SN/A if (fromCommit->commitUnblock[tid]) { 5202292SN/A assert(stalls[tid].commit); 5212292SN/A stalls[tid].commit = false; 5222292SN/A } 5232292SN/A} 5241060SN/A 5252292SN/Atemplate <class Impl> 5262292SN/Abool 5272292SN/ADefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 5282292SN/A{ 5292292SN/A // Check if there's a squash signal, squash if there is. 5302292SN/A // Check stall signals, block if necessary. 5312292SN/A // If status was blocked 5322292SN/A // Check if stall conditions have passed 5332292SN/A // if so then go to unblocking 5342292SN/A // If status was Squashing 5352292SN/A // check if squashing is not high. Switch to running this cycle. 5361060SN/A 5372292SN/A // Update the per thread stall statuses. 5382292SN/A readStallSignals(tid); 5391060SN/A 5402292SN/A // Check squash signals from commit. 5412292SN/A if (fromCommit->commitInfo[tid].squash) { 5421681SN/A 5432292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5442292SN/A "from commit.\n", tid); 5452292SN/A 5462292SN/A squash(tid); 5472292SN/A 5482292SN/A return true; 5492292SN/A } 5502292SN/A 5512292SN/A // Check ROB squash signals from commit. 5522292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5532703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5542292SN/A 5552292SN/A // Continue to squash. 5562292SN/A decodeStatus[tid] = Squashing; 5572292SN/A 5582292SN/A return true; 5592292SN/A } 5602292SN/A 5612292SN/A if (checkStall(tid)) { 5622292SN/A return block(tid); 5632292SN/A } 5642292SN/A 5652292SN/A if (decodeStatus[tid] == Blocked) { 5662292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5672292SN/A tid); 5682292SN/A 5692292SN/A decodeStatus[tid] = Unblocking; 5702292SN/A 5712292SN/A unblock(tid); 5722292SN/A 5732292SN/A return true; 5742292SN/A } 5752292SN/A 5762292SN/A if (decodeStatus[tid] == Squashing) { 5772292SN/A // Switch status to running if decode isn't being told to block or 5782292SN/A // squash this cycle. 5792292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5802292SN/A tid); 5812292SN/A 5822292SN/A decodeStatus[tid] = Running; 5832292SN/A 5842292SN/A return false; 5852292SN/A } 5862292SN/A 5872292SN/A // If we've reached this point, we have not gotten any signals that 5882292SN/A // cause decode to change its status. Decode remains the same as before. 5892292SN/A return false; 5902292SN/A} 5912292SN/A 5922292SN/Atemplate<class Impl> 5932292SN/Avoid 5942292SN/ADefaultDecode<Impl>::tick() 5952292SN/A{ 5962292SN/A wroteToTimeBuffer = false; 5972292SN/A 5982292SN/A bool status_change = false; 5992292SN/A 6002292SN/A toRenameIndex = 0; 6012292SN/A 6022292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6032292SN/A 6042292SN/A sortInsts(); 6052292SN/A 6062292SN/A //Check stall and squash signals. 6072292SN/A while (threads != (*activeThreads).end()) { 6082292SN/A unsigned tid = *threads++; 6092292SN/A 6102292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 6112292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 6122292SN/A 6132292SN/A decode(status_change, tid); 6142292SN/A } 6152292SN/A 6162292SN/A if (status_change) { 6172292SN/A updateStatus(); 6182292SN/A } 6192292SN/A 6202292SN/A if (wroteToTimeBuffer) { 6212292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 6222292SN/A 6232292SN/A cpu->activityThisCycle(); 6241060SN/A } 6251060SN/A} 6261060SN/A 6271060SN/Atemplate<class Impl> 6281060SN/Avoid 6292292SN/ADefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 6301060SN/A{ 6312292SN/A // If status is Running or idle, 6322292SN/A // call decodeInsts() 6332292SN/A // If status is Unblocking, 6342292SN/A // buffer any instructions coming from fetch 6352292SN/A // continue trying to empty skid buffer 6362292SN/A // check if stall conditions have passed 6372292SN/A 6382292SN/A if (decodeStatus[tid] == Blocked) { 6392292SN/A ++decodeBlockedCycles; 6402292SN/A } else if (decodeStatus[tid] == Squashing) { 6412292SN/A ++decodeSquashCycles; 6421060SN/A } 6431060SN/A 6442292SN/A // Decode should try to decode as many instructions as its bandwidth 6452292SN/A // will allow, as long as it is not currently blocked. 6462292SN/A if (decodeStatus[tid] == Running || 6472292SN/A decodeStatus[tid] == Idle) { 6482935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6492292SN/A "stage.\n",tid); 6502292SN/A 6512292SN/A decodeInsts(tid); 6522292SN/A } else if (decodeStatus[tid] == Unblocking) { 6532292SN/A // Make sure that the skid buffer has something in it if the 6542292SN/A // status is unblocking. 6552292SN/A assert(!skidsEmpty()); 6562292SN/A 6572292SN/A // If the status was unblocking, then instructions from the skid 6582292SN/A // buffer were used. Remove those instructions and handle 6592292SN/A // the rest of unblocking. 6602292SN/A decodeInsts(tid); 6612292SN/A 6622292SN/A if (fetchInstsValid()) { 6632292SN/A // Add the current inputs to the skid buffer so they can be 6642292SN/A // reprocessed when this stage unblocks. 6652292SN/A skidInsert(tid); 6662292SN/A } 6672292SN/A 6682292SN/A status_change = unblock(tid) || status_change; 6691060SN/A } 6702292SN/A} 6711060SN/A 6722292SN/Atemplate <class Impl> 6732292SN/Avoid 6742292SN/ADefaultDecode<Impl>::decodeInsts(unsigned tid) 6752292SN/A{ 6762292SN/A // Instructions can come either from the skid buffer or the list of 6772292SN/A // instructions coming from fetch, depending on decode's status. 6782292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6792292SN/A skidBuffer[tid].size() : insts[tid].size(); 6802292SN/A 6812292SN/A if (insts_available == 0) { 6822292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6832292SN/A " early.\n",tid); 6841060SN/A // Should I change the status to idle? 6851062SN/A ++decodeIdleCycles; 6861060SN/A return; 6872292SN/A } else if (decodeStatus[tid] == Unblocking) { 6882292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6892292SN/A "buffer.\n",tid); 6902292SN/A ++decodeUnblockCycles; 6912292SN/A } else if (decodeStatus[tid] == Running) { 6922292SN/A ++decodeRunCycles; 6931060SN/A } 6941060SN/A 6951061SN/A DynInstPtr inst; 6961061SN/A 6972292SN/A std::queue<DynInstPtr> 6982292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6992292SN/A skidBuffer[tid] : insts[tid]; 7001061SN/A 7012292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 7021060SN/A 7032292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 7042292SN/A assert(!insts_to_decode.empty()); 7051060SN/A 7062292SN/A inst = insts_to_decode.front(); 7071062SN/A 7082292SN/A insts_to_decode.pop(); 7091061SN/A 7102292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 7112292SN/A "PC %#x\n", 7122292SN/A tid, inst->seqNum, inst->readPC()); 7131061SN/A 7141061SN/A if (inst->isSquashed()) { 7152292SN/A DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 7161061SN/A "squashed, skipping.\n", 7172292SN/A tid, inst->seqNum, inst->readPC()); 7181061SN/A 7191062SN/A ++decodeSquashedInsts; 7201062SN/A 7211061SN/A --insts_available; 7221061SN/A 7231061SN/A continue; 7241061SN/A } 7251060SN/A 7261681SN/A // Also check if instructions have no source registers. Mark 7271681SN/A // them as ready to issue at any time. Not sure if this check 7281681SN/A // should exist here or at a later stage; however it doesn't matter 7291681SN/A // too much for function correctness. 7301681SN/A if (inst->numSrcRegs() == 0) { 7311681SN/A inst->setCanIssue(); 7321681SN/A } 7331681SN/A 7341060SN/A // This current instruction is valid, so add it into the decode 7351060SN/A // queue. The next instruction may not be valid, so check to 7361060SN/A // see if branches were predicted correctly. 7372292SN/A toRename->insts[toRenameIndex] = inst; 7381061SN/A 7391061SN/A ++(toRename->size); 7402292SN/A ++toRenameIndex; 7412292SN/A ++decodeDecodedInsts; 7422292SN/A --insts_available; 7431060SN/A 7441060SN/A // Ensure that if it was predicted as a branch, it really is a 7451061SN/A // branch. 7461060SN/A if (inst->predTaken() && !inst->isControl()) { 7472935Sksewell@umich.edu DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC, 7482935Sksewell@umich.edu inst->nextPC + 4); 7492935Sksewell@umich.edu 7501060SN/A panic("Instruction predicted as a branch!"); 7511060SN/A 7521062SN/A ++decodeControlMispred; 7532292SN/A 7541060SN/A // Might want to set some sort of boolean and just do 7551060SN/A // a check at the end 7562292SN/A squash(inst, inst->threadNumber); 7572292SN/A 7581060SN/A break; 7591060SN/A } 7601060SN/A 7611062SN/A // Go ahead and compute any PC-relative branches. 7621063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7632307SN/A ++decodeBranchResolved; 7641062SN/A 7652678Sktlim@umich.edu if (inst->branchTarget() != inst->readPredTarg()) { 7661062SN/A ++decodeBranchMispred; 7672292SN/A 7681060SN/A // Might want to set some sort of boolean and just do 7691060SN/A // a check at the end 7702935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 7712292SN/A squash(inst, inst->threadNumber); 7722345SN/A inst->setPredTarg(inst->branchTarget()); 7732935Sksewell@umich.edu break; 7742935Sksewell@umich.edu#else 7752935Sksewell@umich.edu // If mispredicted as taken, then ignore delay slot 7762935Sksewell@umich.edu // instruction... else keep delay slot and squash 7772935Sksewell@umich.edu // after it is sent to rename 7782935Sksewell@umich.edu if (inst->predTaken() && inst->isCondDelaySlot()) { 7792935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst." 7802935Sksewell@umich.edu "[sn:%i] PC %#x mispredicted as taken.\n", tid, 7812935Sksewell@umich.edu inst->seqNum, inst->PC); 7822935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum; 7832935Sksewell@umich.edu squash(inst, inst->threadNumber); 7842935Sksewell@umich.edu inst->setPredTarg(inst->branchTarget()); 7852935Sksewell@umich.edu break; 7862935Sksewell@umich.edu } else { 7872935Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: Misprediction detected at " 7882935Sksewell@umich.edu "[sn:%i] PC %#x, will squash after delay slot " 7892935Sksewell@umich.edu "inst. is sent to Rename\n", 7902935Sksewell@umich.edu tid, inst->seqNum, inst->PC); 7912935Sksewell@umich.edu bdelayDoneSeqNum[tid] = inst->seqNum + 1; 7922935Sksewell@umich.edu squashAfterDelaySlot[tid] = true; 7932935Sksewell@umich.edu squashInst[tid] = inst; 7942935Sksewell@umich.edu continue; 7952935Sksewell@umich.edu } 7962935Sksewell@umich.edu#endif 7972935Sksewell@umich.edu } 7982935Sksewell@umich.edu } 7992292SN/A 8002935Sksewell@umich.edu if (squashAfterDelaySlot[tid]) { 8012935Sksewell@umich.edu assert(!inst->isSquashed()); 8022935Sksewell@umich.edu squash(squashInst[tid], squashInst[tid]->threadNumber); 8032935Sksewell@umich.edu squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget()); 8042935Sksewell@umich.edu assert(!inst->isSquashed()); 8052935Sksewell@umich.edu break; 8061060SN/A } 8071060SN/A } 8081061SN/A 8092292SN/A // If we didn't process all instructions, then we will need to block 8102292SN/A // and put all those instructions into the skid buffer. 8112292SN/A if (!insts_to_decode.empty()) { 8122292SN/A block(tid); 8132292SN/A } 8142292SN/A 8152292SN/A // Record that decode has written to the time buffer for activity 8162292SN/A // tracking. 8172292SN/A if (toRenameIndex) { 8182292SN/A wroteToTimeBuffer = true; 8192292SN/A } 8201060SN/A} 821