decode_impl.hh revision 2316
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "cpu/o3/decode.hh" 30 31using namespace std; 32 33template<class Impl> 34DefaultDecode<Impl>::DefaultDecode(Params *params) 35 : renameToDecodeDelay(params->renameToDecodeDelay), 36 iewToDecodeDelay(params->iewToDecodeDelay), 37 commitToDecodeDelay(params->commitToDecodeDelay), 38 fetchToDecodeDelay(params->fetchToDecodeDelay), 39 decodeWidth(params->decodeWidth), 40 numThreads(params->numberOfThreads) 41{ 42 DPRINTF(Decode, "decodeWidth=%i.\n", decodeWidth); 43 _status = Inactive; 44 45 for (int i = 0; i < numThreads; ++i) { 46 decodeStatus[i] = Idle; 47 48 stalls[i].rename = false; 49 stalls[i].iew = false; 50 stalls[i].commit = false; 51 } 52 53 // @todo: Make into a parameter 54 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 55} 56 57template <class Impl> 58std::string 59DefaultDecode<Impl>::name() const 60{ 61 return cpu->name() + ".decode"; 62} 63 64template <class Impl> 65void 66DefaultDecode<Impl>::regStats() 67{ 68 decodeIdleCycles 69 .name(name() + ".DECODE:IdleCycles") 70 .desc("Number of cycles decode is idle") 71 .prereq(decodeIdleCycles); 72 decodeBlockedCycles 73 .name(name() + ".DECODE:BlockedCycles") 74 .desc("Number of cycles decode is blocked") 75 .prereq(decodeBlockedCycles); 76 decodeRunCycles 77 .name(name() + ".DECODE:RunCycles") 78 .desc("Number of cycles decode is running") 79 .prereq(decodeRunCycles); 80 decodeUnblockCycles 81 .name(name() + ".DECODE:UnblockCycles") 82 .desc("Number of cycles decode is unblocking") 83 .prereq(decodeUnblockCycles); 84 decodeSquashCycles 85 .name(name() + ".DECODE:SquashCycles") 86 .desc("Number of cycles decode is squashing") 87 .prereq(decodeSquashCycles); 88 decodeBranchResolved 89 .name(name() + ".DECODE:BranchResolved") 90 .desc("Number of times decode resolved a branch") 91 .prereq(decodeBranchResolved); 92 decodeBranchMispred 93 .name(name() + ".DECODE:BranchMispred") 94 .desc("Number of times decode detected a branch misprediction") 95 .prereq(decodeBranchMispred); 96 decodeControlMispred 97 .name(name() + ".DECODE:ControlMispred") 98 .desc("Number of times decode detected an instruction incorrectly" 99 " predicted as a control") 100 .prereq(decodeControlMispred); 101 decodeDecodedInsts 102 .name(name() + ".DECODE:DecodedInsts") 103 .desc("Number of instructions handled by decode") 104 .prereq(decodeDecodedInsts); 105 decodeSquashedInsts 106 .name(name() + ".DECODE:SquashedInsts") 107 .desc("Number of squashed instructions handled by decode") 108 .prereq(decodeSquashedInsts); 109} 110 111template<class Impl> 112void 113DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr) 114{ 115 DPRINTF(Decode, "Setting CPU pointer.\n"); 116 cpu = cpu_ptr; 117} 118 119template<class Impl> 120void 121DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 122{ 123 DPRINTF(Decode, "Setting time buffer pointer.\n"); 124 timeBuffer = tb_ptr; 125 126 // Setup wire to write information back to fetch. 127 toFetch = timeBuffer->getWire(0); 128 129 // Create wires to get information from proper places in time buffer. 130 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 131 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 132 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 133} 134 135template<class Impl> 136void 137DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 138{ 139 DPRINTF(Decode, "Setting decode queue pointer.\n"); 140 decodeQueue = dq_ptr; 141 142 // Setup wire to write information to proper place in decode queue. 143 toRename = decodeQueue->getWire(0); 144} 145 146template<class Impl> 147void 148DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 149{ 150 DPRINTF(Decode, "Setting fetch queue pointer.\n"); 151 fetchQueue = fq_ptr; 152 153 // Setup wire to read information from fetch queue. 154 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 155} 156 157template<class Impl> 158void 159DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) 160{ 161 DPRINTF(Decode, "Setting active threads list pointer.\n"); 162 activeThreads = at_ptr; 163} 164 165template <class Impl> 166void 167DefaultDecode<Impl>::switchOut() 168{ 169 cpu->signalSwitched(); 170} 171 172template <class Impl> 173void 174DefaultDecode<Impl>::takeOverFrom() 175{ 176 _status = Inactive; 177 178 for (int i = 0; i < numThreads; ++i) { 179 decodeStatus[i] = Idle; 180 181 stalls[i].rename = false; 182 stalls[i].iew = false; 183 stalls[i].commit = false; 184 while (!insts[i].empty()) 185 insts[i].pop(); 186 while (!skidBuffer[i].empty()) 187 skidBuffer[i].pop(); 188 branchCount[i] = 0; 189 } 190 wroteToTimeBuffer = false; 191} 192 193template<class Impl> 194bool 195DefaultDecode<Impl>::checkStall(unsigned tid) const 196{ 197 bool ret_val = false; 198 199 if (stalls[tid].rename) { 200 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 201 ret_val = true; 202 } else if (stalls[tid].iew) { 203 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 204 ret_val = true; 205 } else if (stalls[tid].commit) { 206 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 207 ret_val = true; 208 } 209 210 return ret_val; 211} 212 213template<class Impl> 214inline bool 215DefaultDecode<Impl>::fetchInstsValid() 216{ 217 return fromFetch->size > 0; 218} 219 220template<class Impl> 221bool 222DefaultDecode<Impl>::block(unsigned tid) 223{ 224 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 225 226 // If the decode status is blocked or unblocking then decode has not yet 227 // signalled fetch to unblock. In that case, there is no need to tell 228 // fetch to block. 229 if (decodeStatus[tid] != Blocked && 230 decodeStatus[tid] != Unblocking) { 231 toFetch->decodeBlock[tid] = true; 232 wroteToTimeBuffer = true; 233 } 234 235 // Add the current inputs to the skid buffer so they can be 236 // reprocessed when this stage unblocks. 237 skidInsert(tid); 238 239 if (decodeStatus[tid] != Blocked) { 240 // Set the status to Blocked. 241 decodeStatus[tid] = Blocked; 242 return true; 243 } 244 245 return false; 246} 247 248template<class Impl> 249bool 250DefaultDecode<Impl>::unblock(unsigned tid) 251{ 252 DPRINTF(Decode, "[tid:%u]: Trying to unblock.\n", tid); 253 254 // Decode is done unblocking only if the skid buffer is empty. 255 if (skidBuffer[tid].empty()) { 256 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 257 toFetch->decodeUnblock[tid] = true; 258 wroteToTimeBuffer = true; 259 260 decodeStatus[tid] = Running; 261 return true; 262 } 263 264 return false; 265} 266 267template<class Impl> 268void 269DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) 270{ 271 DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction " 272 "detected at decode.\n", tid); 273 274 toFetch->decodeInfo[tid].branchMispredict = true; 275 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 276 toFetch->decodeInfo[tid].predIncorrect = true; 277 toFetch->decodeInfo[tid].squash = true; 278 toFetch->decodeInfo[tid].nextPC = inst->readNextPC(); 279 toFetch->decodeInfo[tid].branchTaken = true; 280 281 if (decodeStatus[tid] == Blocked || 282 decodeStatus[tid] == Unblocking) { 283 toFetch->decodeUnblock[tid] = 1; 284 } 285 286 // Set status to squashing. 287 decodeStatus[tid] = Squashing; 288 289 for (int i=0; i<fromFetch->size; i++) { 290 if (fromFetch->insts[i]->threadNumber == tid && 291 fromFetch->insts[i]->seqNum > inst->seqNum) { 292 fromFetch->insts[i]->squashed = true; 293 } 294 } 295 296 while (!insts[tid].empty()) { 297 insts[tid].pop(); 298 } 299 300 // Clear the skid buffer in case it has any data in it. 301 while (!skidBuffer[tid].empty()) { 302 skidBuffer[tid].pop(); 303 } 304 305 // Squash instructions up until this one 306 cpu->removeInstsUntil(inst->seqNum, tid); 307} 308 309template<class Impl> 310unsigned 311DefaultDecode<Impl>::squash(unsigned tid) 312{ 313 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 314 315 if (decodeStatus[tid] == Blocked || 316 decodeStatus[tid] == Unblocking) { 317#if !FULL_SYSTEM 318 // In syscall emulation, we can have both a block and a squash due 319 // to a syscall in the same cycle. This would cause both signals to 320 // be high. This shouldn't happen in full system. 321 if (toFetch->decodeBlock[tid]) { 322 toFetch->decodeBlock[tid] = 0; 323 } else { 324 toFetch->decodeUnblock[tid] = 1; 325 } 326#else 327 toFetch->decodeUnblock[tid] = 1; 328#endif 329 } 330 331 // Set status to squashing. 332 decodeStatus[tid] = Squashing; 333 334 // Go through incoming instructions from fetch and squash them. 335 unsigned squash_count = 0; 336 337 for (int i=0; i<fromFetch->size; i++) { 338 if (fromFetch->insts[i]->threadNumber == tid) { 339 fromFetch->insts[i]->squashed = true; 340 squash_count++; 341 } 342 } 343 344 while (!insts[tid].empty()) { 345 insts[tid].pop(); 346 } 347 348 // Clear the skid buffer in case it has any data in it. 349 while (!skidBuffer[tid].empty()) { 350 skidBuffer[tid].pop(); 351 } 352 353 return squash_count; 354} 355 356template<class Impl> 357void 358DefaultDecode<Impl>::skidInsert(unsigned tid) 359{ 360 DynInstPtr inst = NULL; 361 362 while (!insts[tid].empty()) { 363 inst = insts[tid].front(); 364 365 insts[tid].pop(); 366 367 assert(tid == inst->threadNumber); 368 369 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 370 inst->seqNum, inst->readPC(), inst->threadNumber); 371 372 skidBuffer[tid].push(inst); 373 } 374 375 // Eventually need to enforce this by not letting a thread 376 // fetch past its skidbuffer 377 assert(skidBuffer[tid].size() <= skidBufferMax); 378} 379 380template<class Impl> 381bool 382DefaultDecode<Impl>::skidsEmpty() 383{ 384 list<unsigned>::iterator threads = (*activeThreads).begin(); 385 386 while (threads != (*activeThreads).end()) { 387 if (!skidBuffer[*threads++].empty()) 388 return false; 389 } 390 391 return true; 392} 393 394template<class Impl> 395void 396DefaultDecode<Impl>::updateStatus() 397{ 398 bool any_unblocking = false; 399 400 list<unsigned>::iterator threads = (*activeThreads).begin(); 401 402 threads = (*activeThreads).begin(); 403 404 while (threads != (*activeThreads).end()) { 405 unsigned tid = *threads++; 406 407 if (decodeStatus[tid] == Unblocking) { 408 any_unblocking = true; 409 break; 410 } 411 } 412 413 // Decode will have activity if it's unblocking. 414 if (any_unblocking) { 415 if (_status == Inactive) { 416 _status = Active; 417 418 DPRINTF(Activity, "Activating stage.\n"); 419 420 cpu->activateStage(FullCPU::DecodeIdx); 421 } 422 } else { 423 // If it's not unblocking, then decode will not have any internal 424 // activity. Switch it to inactive. 425 if (_status == Active) { 426 _status = Inactive; 427 DPRINTF(Activity, "Deactivating stage.\n"); 428 429 cpu->deactivateStage(FullCPU::DecodeIdx); 430 } 431 } 432} 433 434template <class Impl> 435void 436DefaultDecode<Impl>::sortInsts() 437{ 438 int insts_from_fetch = fromFetch->size; 439 440 for (int i=0; i < numThreads; i++) 441 assert(insts[i].empty()); 442 443 for (int i = 0; i < insts_from_fetch; ++i) { 444 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 445 } 446} 447 448template<class Impl> 449void 450DefaultDecode<Impl>::readStallSignals(unsigned tid) 451{ 452 if (fromRename->renameBlock[tid]) { 453 stalls[tid].rename = true; 454 } 455 456 if (fromRename->renameUnblock[tid]) { 457 assert(stalls[tid].rename); 458 stalls[tid].rename = false; 459 } 460 461 if (fromIEW->iewBlock[tid]) { 462 stalls[tid].iew = true; 463 } 464 465 if (fromIEW->iewUnblock[tid]) { 466 assert(stalls[tid].iew); 467 stalls[tid].iew = false; 468 } 469 470 if (fromCommit->commitBlock[tid]) { 471 stalls[tid].commit = true; 472 } 473 474 if (fromCommit->commitUnblock[tid]) { 475 assert(stalls[tid].commit); 476 stalls[tid].commit = false; 477 } 478} 479 480template <class Impl> 481bool 482DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid) 483{ 484 // Check if there's a squash signal, squash if there is. 485 // Check stall signals, block if necessary. 486 // If status was blocked 487 // Check if stall conditions have passed 488 // if so then go to unblocking 489 // If status was Squashing 490 // check if squashing is not high. Switch to running this cycle. 491 492 // Update the per thread stall statuses. 493 readStallSignals(tid); 494 495 // Check squash signals from commit. 496 if (fromCommit->commitInfo[tid].squash) { 497 498 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 499 "from commit.\n", tid); 500 501 squash(tid); 502 503 return true; 504 } 505 506 // Check ROB squash signals from commit. 507 if (fromCommit->commitInfo[tid].robSquashing) { 508 DPRINTF(Decode, "[tid:%]: ROB is still squashing.\n",tid); 509 510 // Continue to squash. 511 decodeStatus[tid] = Squashing; 512 513 return true; 514 } 515 516 if (checkStall(tid)) { 517 return block(tid); 518 } 519 520 if (decodeStatus[tid] == Blocked) { 521 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 522 tid); 523 524 decodeStatus[tid] = Unblocking; 525 526 unblock(tid); 527 528 return true; 529 } 530 531 if (decodeStatus[tid] == Squashing) { 532 // Switch status to running if decode isn't being told to block or 533 // squash this cycle. 534 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 535 tid); 536 537 decodeStatus[tid] = Running; 538 539 return false; 540 } 541 542 // If we've reached this point, we have not gotten any signals that 543 // cause decode to change its status. Decode remains the same as before. 544 return false; 545} 546 547template<class Impl> 548void 549DefaultDecode<Impl>::tick() 550{ 551 wroteToTimeBuffer = false; 552 553 bool status_change = false; 554 555 toRenameIndex = 0; 556 557 list<unsigned>::iterator threads = (*activeThreads).begin(); 558 559 sortInsts(); 560 561 //Check stall and squash signals. 562 while (threads != (*activeThreads).end()) { 563 unsigned tid = *threads++; 564 565 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 566 status_change = checkSignalsAndUpdate(tid) || status_change; 567 568 decode(status_change, tid); 569 } 570 571 if (status_change) { 572 updateStatus(); 573 } 574 575 if (wroteToTimeBuffer) { 576 DPRINTF(Activity, "Activity this cycle.\n"); 577 578 cpu->activityThisCycle(); 579 } 580} 581 582template<class Impl> 583void 584DefaultDecode<Impl>::decode(bool &status_change, unsigned tid) 585{ 586 // If status is Running or idle, 587 // call decodeInsts() 588 // If status is Unblocking, 589 // buffer any instructions coming from fetch 590 // continue trying to empty skid buffer 591 // check if stall conditions have passed 592 593 if (decodeStatus[tid] == Blocked) { 594 ++decodeBlockedCycles; 595 } else if (decodeStatus[tid] == Squashing) { 596 ++decodeSquashCycles; 597 } 598 599 // Decode should try to decode as many instructions as its bandwidth 600 // will allow, as long as it is not currently blocked. 601 if (decodeStatus[tid] == Running || 602 decodeStatus[tid] == Idle) { 603 DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run " 604 "stage.\n",tid); 605 606 decodeInsts(tid); 607 } else if (decodeStatus[tid] == Unblocking) { 608 // Make sure that the skid buffer has something in it if the 609 // status is unblocking. 610 assert(!skidsEmpty()); 611 612 // If the status was unblocking, then instructions from the skid 613 // buffer were used. Remove those instructions and handle 614 // the rest of unblocking. 615 decodeInsts(tid); 616 617 if (fetchInstsValid()) { 618 // Add the current inputs to the skid buffer so they can be 619 // reprocessed when this stage unblocks. 620 skidInsert(tid); 621 } 622 623 status_change = unblock(tid) || status_change; 624 } 625} 626 627template <class Impl> 628void 629DefaultDecode<Impl>::decodeInsts(unsigned tid) 630{ 631 // Instructions can come either from the skid buffer or the list of 632 // instructions coming from fetch, depending on decode's status. 633 int insts_available = decodeStatus[tid] == Unblocking ? 634 skidBuffer[tid].size() : insts[tid].size(); 635 636 if (insts_available == 0) { 637 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 638 " early.\n",tid); 639 // Should I change the status to idle? 640 ++decodeIdleCycles; 641 return; 642 } else if (decodeStatus[tid] == Unblocking) { 643 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 644 "buffer.\n",tid); 645 ++decodeUnblockCycles; 646 } else if (decodeStatus[tid] == Running) { 647 ++decodeRunCycles; 648 } 649 650 DynInstPtr inst; 651 652 std::queue<DynInstPtr> 653 &insts_to_decode = decodeStatus[tid] == Unblocking ? 654 skidBuffer[tid] : insts[tid]; 655 656 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 657 658 while (insts_available > 0 && toRenameIndex < decodeWidth) { 659 assert(!insts_to_decode.empty()); 660 661 inst = insts_to_decode.front(); 662 663 insts_to_decode.pop(); 664 665 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 666 "PC %#x\n", 667 tid, inst->seqNum, inst->readPC()); 668 669 if (inst->isSquashed()) { 670 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 671 "squashed, skipping.\n", 672 tid, inst->seqNum, inst->readPC()); 673 674 ++decodeSquashedInsts; 675 676 --insts_available; 677 678 continue; 679 } 680 681 // Also check if instructions have no source registers. Mark 682 // them as ready to issue at any time. Not sure if this check 683 // should exist here or at a later stage; however it doesn't matter 684 // too much for function correctness. 685 if (inst->numSrcRegs() == 0) { 686 inst->setCanIssue(); 687 } 688 689 // This current instruction is valid, so add it into the decode 690 // queue. The next instruction may not be valid, so check to 691 // see if branches were predicted correctly. 692 toRename->insts[toRenameIndex] = inst; 693 694 ++(toRename->size); 695 ++toRenameIndex; 696 ++decodeDecodedInsts; 697 --insts_available; 698 699 // Ensure that if it was predicted as a branch, it really is a 700 // branch. 701 if (inst->predTaken() && !inst->isControl()) { 702 panic("Instruction predicted as a branch!"); 703 704 ++decodeControlMispred; 705 706 // Might want to set some sort of boolean and just do 707 // a check at the end 708 squash(inst, inst->threadNumber); 709 710 break; 711 } 712 713 // Go ahead and compute any PC-relative branches. 714 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 715 ++decodeBranchResolved; 716 inst->setNextPC(inst->branchTarget()); 717 718 if (inst->mispredicted()) { 719 ++decodeBranchMispred; 720 721 // Might want to set some sort of boolean and just do 722 // a check at the end 723 squash(inst, inst->threadNumber); 724 725 break; 726 } 727 } 728 } 729 730 // If we didn't process all instructions, then we will need to block 731 // and put all those instructions into the skid buffer. 732 if (!insts_to_decode.empty()) { 733 block(tid); 734 } 735 736 // Record that decode has written to the time buffer for activity 737 // tracking. 738 if (toRenameIndex) { 739 wroteToTimeBuffer = true; 740 } 741} 742