decode_impl.hh revision 11650
12207SN/A/* 22207SN/A * Copyright (c) 2012, 2014 ARM Limited 32207SN/A * All rights reserved 42207SN/A * 52207SN/A * The license below extends only to copyright in the software and shall 62207SN/A * not be construed as granting a license to any other intellectual 72207SN/A * property including but not limited to intellectual property relating 82207SN/A * to a hardware implementation of the functionality of the software 92207SN/A * licensed hereunder. You may use the software subject to the license 102207SN/A * terms below provided that you ensure that this notice is replicated 112207SN/A * unmodified and in its entirety in all distributions of the software, 122207SN/A * modified or unmodified, in source code or in binary form. 132207SN/A * 142207SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152207SN/A * All rights reserved. 162207SN/A * 172207SN/A * Redistribution and use in source and binary forms, with or without 182207SN/A * modification, are permitted provided that the following conditions are 192207SN/A * met: redistributions of source code must retain the above copyright 202207SN/A * notice, this list of conditions and the following disclaimer; 212207SN/A * redistributions in binary form must reproduce the above copyright 222207SN/A * notice, this list of conditions and the following disclaimer in the 232207SN/A * documentation and/or other materials provided with the distribution; 242207SN/A * neither the name of the copyright holders nor the names of its 252207SN/A * contributors may be used to endorse or promote products derived from 262207SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322972Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342454SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355759Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362454SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372680Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385759Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395759Shsul@eecs.umich.edu * 402474SN/A * Authors: Kevin Lim 412207SN/A */ 422474SN/A 432474SN/A#ifndef __CPU_O3_DECODE_IMPL_HH__ 442474SN/A#define __CPU_O3_DECODE_IMPL_HH__ 455569Snate@binkert.org 465569Snate@binkert.org#include "arch/types.hh" 475154Sgblack@eecs.umich.edu#include "base/trace.hh" 482474SN/A#include "config/the_isa.hh" 492474SN/A#include "cpu/o3/decode.hh" 502474SN/A#include "cpu/inst_seq.hh" 512474SN/A#include "debug/Activity.hh" 522474SN/A#include "debug/Decode.hh" 532474SN/A#include "debug/O3PipeView.hh" 542474SN/A#include "params/DerivO3CPU.hh" 552474SN/A#include "sim/full_system.hh" 562474SN/A 572474SN/A// clang complains about std::set being overloaded with Packet::set if 582474SN/A// we open up the entire namespace std 592474SN/Ausing std::list; 602474SN/A 612474SN/Atemplate<class Impl> 622474SN/ADefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 632474SN/A : cpu(_cpu), 642474SN/A renameToDecodeDelay(params->renameToDecodeDelay), 652474SN/A iewToDecodeDelay(params->iewToDecodeDelay), 665759Shsul@eecs.umich.edu commitToDecodeDelay(params->commitToDecodeDelay), 675759Shsul@eecs.umich.edu fetchToDecodeDelay(params->fetchToDecodeDelay), 685759Shsul@eecs.umich.edu decodeWidth(params->decodeWidth), 695759Shsul@eecs.umich.edu numThreads(params->numThreads) 705759Shsul@eecs.umich.edu{ 715759Shsul@eecs.umich.edu if (decodeWidth > Impl::MaxWidth) 725759Shsul@eecs.umich.edu fatal("decodeWidth (%d) is larger than compiled limit (%d),\n" 735759Shsul@eecs.umich.edu "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 745759Shsul@eecs.umich.edu decodeWidth, static_cast<int>(Impl::MaxWidth)); 755759Shsul@eecs.umich.edu 765759Shsul@eecs.umich.edu // @todo: Make into a parameter 775759Shsul@eecs.umich.edu skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 785759Shsul@eecs.umich.edu} 795759Shsul@eecs.umich.edu 805759Shsul@eecs.umich.edutemplate<class Impl> 815759Shsul@eecs.umich.eduvoid 825759Shsul@eecs.umich.eduDefaultDecode<Impl>::startupStage() 835759Shsul@eecs.umich.edu{ 845759Shsul@eecs.umich.edu resetStage(); 855759Shsul@eecs.umich.edu} 865759Shsul@eecs.umich.edu 875759Shsul@eecs.umich.edutemplate<class Impl> 885759Shsul@eecs.umich.eduvoid 895759Shsul@eecs.umich.eduDefaultDecode<Impl>::resetStage() 905759Shsul@eecs.umich.edu{ 915759Shsul@eecs.umich.edu _status = Inactive; 925759Shsul@eecs.umich.edu 935759Shsul@eecs.umich.edu // Setup status, make sure stall signals are clear. 945759Shsul@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; ++tid) { 955759Shsul@eecs.umich.edu decodeStatus[tid] = Idle; 965759Shsul@eecs.umich.edu 975759Shsul@eecs.umich.edu stalls[tid].rename = false; 985759Shsul@eecs.umich.edu } 995759Shsul@eecs.umich.edu} 1005759Shsul@eecs.umich.edu 1015759Shsul@eecs.umich.edutemplate <class Impl> 1025759Shsul@eecs.umich.edustd::string 1035759Shsul@eecs.umich.eduDefaultDecode<Impl>::name() const 1045759Shsul@eecs.umich.edu{ 1055759Shsul@eecs.umich.edu return cpu->name() + ".decode"; 1065759Shsul@eecs.umich.edu} 1075759Shsul@eecs.umich.edu 1085759Shsul@eecs.umich.edutemplate <class Impl> 1095759Shsul@eecs.umich.eduvoid 1105759Shsul@eecs.umich.eduDefaultDecode<Impl>::regStats() 1115759Shsul@eecs.umich.edu{ 1125759Shsul@eecs.umich.edu decodeIdleCycles 1135759Shsul@eecs.umich.edu .name(name() + ".IdleCycles") 1145759Shsul@eecs.umich.edu .desc("Number of cycles decode is idle") 1155759Shsul@eecs.umich.edu .prereq(decodeIdleCycles); 1165759Shsul@eecs.umich.edu decodeBlockedCycles 1175759Shsul@eecs.umich.edu .name(name() + ".BlockedCycles") 1185759Shsul@eecs.umich.edu .desc("Number of cycles decode is blocked") 1195759Shsul@eecs.umich.edu .prereq(decodeBlockedCycles); 1205759Shsul@eecs.umich.edu decodeRunCycles 1215759Shsul@eecs.umich.edu .name(name() + ".RunCycles") 1225759Shsul@eecs.umich.edu .desc("Number of cycles decode is running") 1235759Shsul@eecs.umich.edu .prereq(decodeRunCycles); 1245759Shsul@eecs.umich.edu decodeUnblockCycles 1255759Shsul@eecs.umich.edu .name(name() + ".UnblockCycles") 1265759Shsul@eecs.umich.edu .desc("Number of cycles decode is unblocking") 1275759Shsul@eecs.umich.edu .prereq(decodeUnblockCycles); 1285759Shsul@eecs.umich.edu decodeSquashCycles 1295759Shsul@eecs.umich.edu .name(name() + ".SquashCycles") 1305759Shsul@eecs.umich.edu .desc("Number of cycles decode is squashing") 1315759Shsul@eecs.umich.edu .prereq(decodeSquashCycles); 1325759Shsul@eecs.umich.edu decodeBranchResolved 1335759Shsul@eecs.umich.edu .name(name() + ".BranchResolved") 1345759Shsul@eecs.umich.edu .desc("Number of times decode resolved a branch") 1355759Shsul@eecs.umich.edu .prereq(decodeBranchResolved); 1365759Shsul@eecs.umich.edu decodeBranchMispred 1375759Shsul@eecs.umich.edu .name(name() + ".BranchMispred") 1385759Shsul@eecs.umich.edu .desc("Number of times decode detected a branch misprediction") 1395759Shsul@eecs.umich.edu .prereq(decodeBranchMispred); 1405759Shsul@eecs.umich.edu decodeControlMispred 1415759Shsul@eecs.umich.edu .name(name() + ".ControlMispred") 1425759Shsul@eecs.umich.edu .desc("Number of times decode detected an instruction incorrectly" 1435759Shsul@eecs.umich.edu " predicted as a control") 1445759Shsul@eecs.umich.edu .prereq(decodeControlMispred); 1455759Shsul@eecs.umich.edu decodeDecodedInsts 1465759Shsul@eecs.umich.edu .name(name() + ".DecodedInsts") 1475759Shsul@eecs.umich.edu .desc("Number of instructions handled by decode") 1485759Shsul@eecs.umich.edu .prereq(decodeDecodedInsts); 1495759Shsul@eecs.umich.edu decodeSquashedInsts 1505759Shsul@eecs.umich.edu .name(name() + ".SquashedInsts") 1515759Shsul@eecs.umich.edu .desc("Number of squashed instructions handled by decode") 1525759Shsul@eecs.umich.edu .prereq(decodeSquashedInsts); 1535759Shsul@eecs.umich.edu} 1545759Shsul@eecs.umich.edu 1555759Shsul@eecs.umich.edutemplate<class Impl> 1565759Shsul@eecs.umich.eduvoid 1575759Shsul@eecs.umich.eduDefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1585759Shsul@eecs.umich.edu{ 1595759Shsul@eecs.umich.edu timeBuffer = tb_ptr; 1605759Shsul@eecs.umich.edu 1615759Shsul@eecs.umich.edu // Setup wire to write information back to fetch. 1625759Shsul@eecs.umich.edu toFetch = timeBuffer->getWire(0); 1635759Shsul@eecs.umich.edu 1645759Shsul@eecs.umich.edu // Create wires to get information from proper places in time buffer. 1655759Shsul@eecs.umich.edu fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1665759Shsul@eecs.umich.edu fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1675759Shsul@eecs.umich.edu fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1685759Shsul@eecs.umich.edu} 1695759Shsul@eecs.umich.edu 1705759Shsul@eecs.umich.edutemplate<class Impl> 1715759Shsul@eecs.umich.eduvoid 1725759Shsul@eecs.umich.eduDefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1735759Shsul@eecs.umich.edu{ 1745759Shsul@eecs.umich.edu decodeQueue = dq_ptr; 1755759Shsul@eecs.umich.edu 1765759Shsul@eecs.umich.edu // Setup wire to write information to proper place in decode queue. 1775759Shsul@eecs.umich.edu toRename = decodeQueue->getWire(0); 1785759Shsul@eecs.umich.edu} 1792474SN/A 1802474SN/Atemplate<class Impl> 1815183Ssaidi@eecs.umich.eduvoid 1825183Ssaidi@eecs.umich.eduDefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1835183Ssaidi@eecs.umich.edu{ 1845759Shsul@eecs.umich.edu fetchQueue = fq_ptr; 1855759Shsul@eecs.umich.edu 1862474SN/A // Setup wire to read information from fetch queue. 1872474SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1885713Shsul@eecs.umich.edu} 1895713Shsul@eecs.umich.edu 1905713Shsul@eecs.umich.edutemplate<class Impl> 1915713Shsul@eecs.umich.eduvoid 1924997Sgblack@eecs.umich.eduDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1935713Shsul@eecs.umich.edu{ 1944997Sgblack@eecs.umich.edu activeThreads = at_ptr; 1955713Shsul@eecs.umich.edu} 1962474SN/A 1972474SN/Atemplate <class Impl> 198void 199DefaultDecode<Impl>::drainSanityCheck() const 200{ 201 for (ThreadID tid = 0; tid < numThreads; ++tid) { 202 assert(insts[tid].empty()); 203 assert(skidBuffer[tid].empty()); 204 } 205} 206 207template <class Impl> 208bool 209DefaultDecode<Impl>::isDrained() const 210{ 211 for (ThreadID tid = 0; tid < numThreads; ++tid) { 212 if (!insts[tid].empty() || !skidBuffer[tid].empty() || 213 (decodeStatus[tid] != Running && decodeStatus[tid] != Idle)) 214 return false; 215 } 216 return true; 217} 218 219template<class Impl> 220bool 221DefaultDecode<Impl>::checkStall(ThreadID tid) const 222{ 223 bool ret_val = false; 224 225 if (stalls[tid].rename) { 226 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 227 ret_val = true; 228 } 229 230 return ret_val; 231} 232 233template<class Impl> 234inline bool 235DefaultDecode<Impl>::fetchInstsValid() 236{ 237 return fromFetch->size > 0; 238} 239 240template<class Impl> 241bool 242DefaultDecode<Impl>::block(ThreadID tid) 243{ 244 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 245 246 // Add the current inputs to the skid buffer so they can be 247 // reprocessed when this stage unblocks. 248 skidInsert(tid); 249 250 // If the decode status is blocked or unblocking then decode has not yet 251 // signalled fetch to unblock. In that case, there is no need to tell 252 // fetch to block. 253 if (decodeStatus[tid] != Blocked) { 254 // Set the status to Blocked. 255 decodeStatus[tid] = Blocked; 256 257 if (toFetch->decodeUnblock[tid]) { 258 toFetch->decodeUnblock[tid] = false; 259 } else { 260 toFetch->decodeBlock[tid] = true; 261 wroteToTimeBuffer = true; 262 } 263 264 return true; 265 } 266 267 return false; 268} 269 270template<class Impl> 271bool 272DefaultDecode<Impl>::unblock(ThreadID tid) 273{ 274 // Decode is done unblocking only if the skid buffer is empty. 275 if (skidBuffer[tid].empty()) { 276 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 277 toFetch->decodeUnblock[tid] = true; 278 wroteToTimeBuffer = true; 279 280 decodeStatus[tid] = Running; 281 return true; 282 } 283 284 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 285 286 return false; 287} 288 289template<class Impl> 290void 291DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 292{ 293 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 294 "prediction detected at decode.\n", tid, inst->seqNum); 295 296 // Send back mispredict information. 297 toFetch->decodeInfo[tid].branchMispredict = true; 298 toFetch->decodeInfo[tid].predIncorrect = true; 299 toFetch->decodeInfo[tid].mispredictInst = inst; 300 toFetch->decodeInfo[tid].squash = true; 301 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 302 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 303 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 304 toFetch->decodeInfo[tid].squashInst = inst; 305 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 306 toFetch->decodeInfo[tid].branchTaken = true; 307 } 308 309 InstSeqNum squash_seq_num = inst->seqNum; 310 311 // Might have to tell fetch to unblock. 312 if (decodeStatus[tid] == Blocked || 313 decodeStatus[tid] == Unblocking) { 314 toFetch->decodeUnblock[tid] = 1; 315 } 316 317 // Set status to squashing. 318 decodeStatus[tid] = Squashing; 319 320 for (int i=0; i<fromFetch->size; i++) { 321 if (fromFetch->insts[i]->threadNumber == tid && 322 fromFetch->insts[i]->seqNum > squash_seq_num) { 323 fromFetch->insts[i]->setSquashed(); 324 } 325 } 326 327 // Clear the instruction list and skid buffer in case they have any 328 // insts in them. 329 while (!insts[tid].empty()) { 330 insts[tid].pop(); 331 } 332 333 while (!skidBuffer[tid].empty()) { 334 skidBuffer[tid].pop(); 335 } 336 337 // Squash instructions up until this one 338 cpu->removeInstsUntil(squash_seq_num, tid); 339} 340 341template<class Impl> 342unsigned 343DefaultDecode<Impl>::squash(ThreadID tid) 344{ 345 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 346 347 if (decodeStatus[tid] == Blocked || 348 decodeStatus[tid] == Unblocking) { 349 if (FullSystem) { 350 toFetch->decodeUnblock[tid] = 1; 351 } else { 352 // In syscall emulation, we can have both a block and a squash due 353 // to a syscall in the same cycle. This would cause both signals 354 // to be high. This shouldn't happen in full system. 355 // @todo: Determine if this still happens. 356 if (toFetch->decodeBlock[tid]) 357 toFetch->decodeBlock[tid] = 0; 358 else 359 toFetch->decodeUnblock[tid] = 1; 360 } 361 } 362 363 // Set status to squashing. 364 decodeStatus[tid] = Squashing; 365 366 // Go through incoming instructions from fetch and squash them. 367 unsigned squash_count = 0; 368 369 for (int i=0; i<fromFetch->size; i++) { 370 if (fromFetch->insts[i]->threadNumber == tid) { 371 fromFetch->insts[i]->setSquashed(); 372 squash_count++; 373 } 374 } 375 376 // Clear the instruction list and skid buffer in case they have any 377 // insts in them. 378 while (!insts[tid].empty()) { 379 insts[tid].pop(); 380 } 381 382 while (!skidBuffer[tid].empty()) { 383 skidBuffer[tid].pop(); 384 } 385 386 return squash_count; 387} 388 389template<class Impl> 390void 391DefaultDecode<Impl>::skidInsert(ThreadID tid) 392{ 393 DynInstPtr inst = NULL; 394 395 while (!insts[tid].empty()) { 396 inst = insts[tid].front(); 397 398 insts[tid].pop(); 399 400 assert(tid == inst->threadNumber); 401 402 skidBuffer[tid].push(inst); 403 404 DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n", 405 inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size()); 406 } 407 408 // @todo: Eventually need to enforce this by not letting a thread 409 // fetch past its skidbuffer 410 assert(skidBuffer[tid].size() <= skidBufferMax); 411} 412 413template<class Impl> 414bool 415DefaultDecode<Impl>::skidsEmpty() 416{ 417 list<ThreadID>::iterator threads = activeThreads->begin(); 418 list<ThreadID>::iterator end = activeThreads->end(); 419 420 while (threads != end) { 421 ThreadID tid = *threads++; 422 if (!skidBuffer[tid].empty()) 423 return false; 424 } 425 426 return true; 427} 428 429template<class Impl> 430void 431DefaultDecode<Impl>::updateStatus() 432{ 433 bool any_unblocking = false; 434 435 list<ThreadID>::iterator threads = activeThreads->begin(); 436 list<ThreadID>::iterator end = activeThreads->end(); 437 438 while (threads != end) { 439 ThreadID tid = *threads++; 440 441 if (decodeStatus[tid] == Unblocking) { 442 any_unblocking = true; 443 break; 444 } 445 } 446 447 // Decode will have activity if it's unblocking. 448 if (any_unblocking) { 449 if (_status == Inactive) { 450 _status = Active; 451 452 DPRINTF(Activity, "Activating stage.\n"); 453 454 cpu->activateStage(O3CPU::DecodeIdx); 455 } 456 } else { 457 // If it's not unblocking, then decode will not have any internal 458 // activity. Switch it to inactive. 459 if (_status == Active) { 460 _status = Inactive; 461 DPRINTF(Activity, "Deactivating stage.\n"); 462 463 cpu->deactivateStage(O3CPU::DecodeIdx); 464 } 465 } 466} 467 468template <class Impl> 469void 470DefaultDecode<Impl>::sortInsts() 471{ 472 int insts_from_fetch = fromFetch->size; 473 for (int i = 0; i < insts_from_fetch; ++i) { 474 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 475 } 476} 477 478template<class Impl> 479void 480DefaultDecode<Impl>::readStallSignals(ThreadID tid) 481{ 482 if (fromRename->renameBlock[tid]) { 483 stalls[tid].rename = true; 484 } 485 486 if (fromRename->renameUnblock[tid]) { 487 assert(stalls[tid].rename); 488 stalls[tid].rename = false; 489 } 490} 491 492template <class Impl> 493bool 494DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 495{ 496 // Check if there's a squash signal, squash if there is. 497 // Check stall signals, block if necessary. 498 // If status was blocked 499 // Check if stall conditions have passed 500 // if so then go to unblocking 501 // If status was Squashing 502 // check if squashing is not high. Switch to running this cycle. 503 504 // Update the per thread stall statuses. 505 readStallSignals(tid); 506 507 // Check squash signals from commit. 508 if (fromCommit->commitInfo[tid].squash) { 509 510 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 511 "from commit.\n", tid); 512 513 squash(tid); 514 515 return true; 516 } 517 518 if (checkStall(tid)) { 519 return block(tid); 520 } 521 522 if (decodeStatus[tid] == Blocked) { 523 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 524 tid); 525 526 decodeStatus[tid] = Unblocking; 527 528 unblock(tid); 529 530 return true; 531 } 532 533 if (decodeStatus[tid] == Squashing) { 534 // Switch status to running if decode isn't being told to block or 535 // squash this cycle. 536 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 537 tid); 538 539 decodeStatus[tid] = Running; 540 541 return false; 542 } 543 544 // If we've reached this point, we have not gotten any signals that 545 // cause decode to change its status. Decode remains the same as before. 546 return false; 547} 548 549template<class Impl> 550void 551DefaultDecode<Impl>::tick() 552{ 553 wroteToTimeBuffer = false; 554 555 bool status_change = false; 556 557 toRenameIndex = 0; 558 559 list<ThreadID>::iterator threads = activeThreads->begin(); 560 list<ThreadID>::iterator end = activeThreads->end(); 561 562 sortInsts(); 563 564 //Check stall and squash signals. 565 while (threads != end) { 566 ThreadID tid = *threads++; 567 568 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 569 status_change = checkSignalsAndUpdate(tid) || status_change; 570 571 decode(status_change, tid); 572 } 573 574 if (status_change) { 575 updateStatus(); 576 } 577 578 if (wroteToTimeBuffer) { 579 DPRINTF(Activity, "Activity this cycle.\n"); 580 581 cpu->activityThisCycle(); 582 } 583} 584 585template<class Impl> 586void 587DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 588{ 589 // If status is Running or idle, 590 // call decodeInsts() 591 // If status is Unblocking, 592 // buffer any instructions coming from fetch 593 // continue trying to empty skid buffer 594 // check if stall conditions have passed 595 596 if (decodeStatus[tid] == Blocked) { 597 ++decodeBlockedCycles; 598 } else if (decodeStatus[tid] == Squashing) { 599 ++decodeSquashCycles; 600 } 601 602 // Decode should try to decode as many instructions as its bandwidth 603 // will allow, as long as it is not currently blocked. 604 if (decodeStatus[tid] == Running || 605 decodeStatus[tid] == Idle) { 606 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 607 "stage.\n",tid); 608 609 decodeInsts(tid); 610 } else if (decodeStatus[tid] == Unblocking) { 611 // Make sure that the skid buffer has something in it if the 612 // status is unblocking. 613 assert(!skidsEmpty()); 614 615 // If the status was unblocking, then instructions from the skid 616 // buffer were used. Remove those instructions and handle 617 // the rest of unblocking. 618 decodeInsts(tid); 619 620 if (fetchInstsValid()) { 621 // Add the current inputs to the skid buffer so they can be 622 // reprocessed when this stage unblocks. 623 skidInsert(tid); 624 } 625 626 status_change = unblock(tid) || status_change; 627 } 628} 629 630template <class Impl> 631void 632DefaultDecode<Impl>::decodeInsts(ThreadID tid) 633{ 634 // Instructions can come either from the skid buffer or the list of 635 // instructions coming from fetch, depending on decode's status. 636 int insts_available = decodeStatus[tid] == Unblocking ? 637 skidBuffer[tid].size() : insts[tid].size(); 638 639 if (insts_available == 0) { 640 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 641 " early.\n",tid); 642 // Should I change the status to idle? 643 ++decodeIdleCycles; 644 return; 645 } else if (decodeStatus[tid] == Unblocking) { 646 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 647 "buffer.\n",tid); 648 ++decodeUnblockCycles; 649 } else if (decodeStatus[tid] == Running) { 650 ++decodeRunCycles; 651 } 652 653 DynInstPtr inst; 654 655 std::queue<DynInstPtr> 656 &insts_to_decode = decodeStatus[tid] == Unblocking ? 657 skidBuffer[tid] : insts[tid]; 658 659 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 660 661 while (insts_available > 0 && toRenameIndex < decodeWidth) { 662 assert(!insts_to_decode.empty()); 663 664 inst = insts_to_decode.front(); 665 666 insts_to_decode.pop(); 667 668 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 669 "PC %s\n", tid, inst->seqNum, inst->pcState()); 670 671 if (inst->isSquashed()) { 672 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 673 "squashed, skipping.\n", 674 tid, inst->seqNum, inst->pcState()); 675 676 ++decodeSquashedInsts; 677 678 --insts_available; 679 680 continue; 681 } 682 683 // Also check if instructions have no source registers. Mark 684 // them as ready to issue at any time. Not sure if this check 685 // should exist here or at a later stage; however it doesn't matter 686 // too much for function correctness. 687 if (inst->numSrcRegs() == 0) { 688 inst->setCanIssue(); 689 } 690 691 // This current instruction is valid, so add it into the decode 692 // queue. The next instruction may not be valid, so check to 693 // see if branches were predicted correctly. 694 toRename->insts[toRenameIndex] = inst; 695 696 ++(toRename->size); 697 ++toRenameIndex; 698 ++decodeDecodedInsts; 699 --insts_available; 700 701#if TRACING_ON 702 if (DTRACE(O3PipeView)) { 703 inst->decodeTick = curTick() - inst->fetchTick; 704 } 705#endif 706 707 // Ensure that if it was predicted as a branch, it really is a 708 // branch. 709 if (inst->readPredTaken() && !inst->isControl()) { 710 panic("Instruction predicted as a branch!"); 711 712 ++decodeControlMispred; 713 714 // Might want to set some sort of boolean and just do 715 // a check at the end 716 squash(inst, inst->threadNumber); 717 718 break; 719 } 720 721 // Go ahead and compute any PC-relative branches. 722 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 723 ++decodeBranchResolved; 724 725 if (!(inst->branchTarget() == inst->readPredTarg())) { 726 ++decodeBranchMispred; 727 728 // Might want to set some sort of boolean and just do 729 // a check at the end 730 squash(inst, inst->threadNumber); 731 TheISA::PCState target = inst->branchTarget(); 732 733 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 734 inst->seqNum, target); 735 //The micro pc after an instruction level branch should be 0 736 inst->setPredTarg(target); 737 break; 738 } 739 } 740 } 741 742 // If we didn't process all instructions, then we will need to block 743 // and put all those instructions into the skid buffer. 744 if (!insts_to_decode.empty()) { 745 block(tid); 746 } 747 748 // Record that decode has written to the time buffer for activity 749 // tracking. 750 if (toRenameIndex) { 751 wroteToTimeBuffer = true; 752 } 753} 754 755#endif//__CPU_O3_DECODE_IMPL_HH__ 756