decode_impl.hh revision 10172
113481Sgiacomo.travaglini@arm.com/* 213481Sgiacomo.travaglini@arm.com * Copyright (c) 2012 ARM Limited 313481Sgiacomo.travaglini@arm.com * All rights reserved 413481Sgiacomo.travaglini@arm.com * 513481Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 613481Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 713481Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 813481Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 913481Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1013481Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1113481Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1213481Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1313481Sgiacomo.travaglini@arm.com * 1413481Sgiacomo.travaglini@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1513481Sgiacomo.travaglini@arm.com * All rights reserved. 1613481Sgiacomo.travaglini@arm.com * 1713481Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1813481Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1913481Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 2013481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 2113481Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 2213481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2313481Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2413481Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2513481Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2613481Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2713481Sgiacomo.travaglini@arm.com * 2813481Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913481Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013481Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113481Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213481Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313481Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413481Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513481Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613481Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713481Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813481Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913481Sgiacomo.travaglini@arm.com * 4013481Sgiacomo.travaglini@arm.com * Authors: Kevin Lim 4113481Sgiacomo.travaglini@arm.com */ 4213481Sgiacomo.travaglini@arm.com 4313481Sgiacomo.travaglini@arm.com#ifndef __CPU_O3_DECODE_IMPL_HH__ 4413481Sgiacomo.travaglini@arm.com#define __CPU_O3_DECODE_IMPL_HH__ 4513481Sgiacomo.travaglini@arm.com 4613481Sgiacomo.travaglini@arm.com#include "arch/types.hh" 4713481Sgiacomo.travaglini@arm.com#include "base/trace.hh" 4813481Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 4913481Sgiacomo.travaglini@arm.com#include "cpu/o3/decode.hh" 5013481Sgiacomo.travaglini@arm.com#include "cpu/inst_seq.hh" 5113481Sgiacomo.travaglini@arm.com#include "debug/Activity.hh" 5213481Sgiacomo.travaglini@arm.com#include "debug/Decode.hh" 5313481Sgiacomo.travaglini@arm.com#include "debug/O3PipeView.hh" 5413481Sgiacomo.travaglini@arm.com#include "params/DerivO3CPU.hh" 5513481Sgiacomo.travaglini@arm.com#include "sim/full_system.hh" 5613481Sgiacomo.travaglini@arm.com 5713481Sgiacomo.travaglini@arm.com// clang complains about std::set being overloaded with Packet::set if 5813481Sgiacomo.travaglini@arm.com// we open up the entire namespace std 5913481Sgiacomo.travaglini@arm.comusing std::list; 6013481Sgiacomo.travaglini@arm.com 6113481Sgiacomo.travaglini@arm.comtemplate<class Impl> 6213481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 6313481Sgiacomo.travaglini@arm.com : cpu(_cpu), 6413481Sgiacomo.travaglini@arm.com renameToDecodeDelay(params->renameToDecodeDelay), 6513481Sgiacomo.travaglini@arm.com iewToDecodeDelay(params->iewToDecodeDelay), 6613481Sgiacomo.travaglini@arm.com commitToDecodeDelay(params->commitToDecodeDelay), 6713481Sgiacomo.travaglini@arm.com fetchToDecodeDelay(params->fetchToDecodeDelay), 6813481Sgiacomo.travaglini@arm.com decodeWidth(params->decodeWidth), 6913481Sgiacomo.travaglini@arm.com numThreads(params->numThreads) 7013481Sgiacomo.travaglini@arm.com{ 7113481Sgiacomo.travaglini@arm.com if (decodeWidth > Impl::MaxWidth) 7213481Sgiacomo.travaglini@arm.com fatal("decodeWidth (%d) is larger than compiled limit (%d),\n" 7313481Sgiacomo.travaglini@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7413481Sgiacomo.travaglini@arm.com decodeWidth, static_cast<int>(Impl::MaxWidth)); 7513481Sgiacomo.travaglini@arm.com 7613481Sgiacomo.travaglini@arm.com // @todo: Make into a parameter 7713481Sgiacomo.travaglini@arm.com skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 7813481Sgiacomo.travaglini@arm.com} 7913481Sgiacomo.travaglini@arm.com 8013481Sgiacomo.travaglini@arm.comtemplate<class Impl> 8113481Sgiacomo.travaglini@arm.comvoid 8213481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::startupStage() 8313481Sgiacomo.travaglini@arm.com{ 8413481Sgiacomo.travaglini@arm.com resetStage(); 8513481Sgiacomo.travaglini@arm.com} 8613481Sgiacomo.travaglini@arm.com 8713481Sgiacomo.travaglini@arm.comtemplate<class Impl> 8813481Sgiacomo.travaglini@arm.comvoid 8913481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::resetStage() 9013481Sgiacomo.travaglini@arm.com{ 9113481Sgiacomo.travaglini@arm.com _status = Inactive; 9213481Sgiacomo.travaglini@arm.com 9313481Sgiacomo.travaglini@arm.com // Setup status, make sure stall signals are clear. 9413481Sgiacomo.travaglini@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 9513481Sgiacomo.travaglini@arm.com decodeStatus[tid] = Idle; 9613481Sgiacomo.travaglini@arm.com 9713481Sgiacomo.travaglini@arm.com stalls[tid].rename = false; 9813481Sgiacomo.travaglini@arm.com stalls[tid].iew = false; 9913481Sgiacomo.travaglini@arm.com stalls[tid].commit = false; 10013481Sgiacomo.travaglini@arm.com } 10113481Sgiacomo.travaglini@arm.com} 10213481Sgiacomo.travaglini@arm.com 10313481Sgiacomo.travaglini@arm.comtemplate <class Impl> 10413481Sgiacomo.travaglini@arm.comstd::string 10513481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::name() const 10613481Sgiacomo.travaglini@arm.com{ 10713481Sgiacomo.travaglini@arm.com return cpu->name() + ".decode"; 10813481Sgiacomo.travaglini@arm.com} 10913481Sgiacomo.travaglini@arm.com 11013481Sgiacomo.travaglini@arm.comtemplate <class Impl> 11113481Sgiacomo.travaglini@arm.comvoid 11213481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::regStats() 11313481Sgiacomo.travaglini@arm.com{ 11413481Sgiacomo.travaglini@arm.com decodeIdleCycles 11513481Sgiacomo.travaglini@arm.com .name(name() + ".IdleCycles") 11613481Sgiacomo.travaglini@arm.com .desc("Number of cycles decode is idle") 11713481Sgiacomo.travaglini@arm.com .prereq(decodeIdleCycles); 11813481Sgiacomo.travaglini@arm.com decodeBlockedCycles 11913481Sgiacomo.travaglini@arm.com .name(name() + ".BlockedCycles") 12013481Sgiacomo.travaglini@arm.com .desc("Number of cycles decode is blocked") 12113481Sgiacomo.travaglini@arm.com .prereq(decodeBlockedCycles); 12213481Sgiacomo.travaglini@arm.com decodeRunCycles 12313481Sgiacomo.travaglini@arm.com .name(name() + ".RunCycles") 12413481Sgiacomo.travaglini@arm.com .desc("Number of cycles decode is running") 12513481Sgiacomo.travaglini@arm.com .prereq(decodeRunCycles); 12613481Sgiacomo.travaglini@arm.com decodeUnblockCycles 12713481Sgiacomo.travaglini@arm.com .name(name() + ".UnblockCycles") 12813481Sgiacomo.travaglini@arm.com .desc("Number of cycles decode is unblocking") 12913481Sgiacomo.travaglini@arm.com .prereq(decodeUnblockCycles); 13013481Sgiacomo.travaglini@arm.com decodeSquashCycles 13113481Sgiacomo.travaglini@arm.com .name(name() + ".SquashCycles") 13213481Sgiacomo.travaglini@arm.com .desc("Number of cycles decode is squashing") 13313481Sgiacomo.travaglini@arm.com .prereq(decodeSquashCycles); 13413481Sgiacomo.travaglini@arm.com decodeBranchResolved 13513481Sgiacomo.travaglini@arm.com .name(name() + ".BranchResolved") 13613481Sgiacomo.travaglini@arm.com .desc("Number of times decode resolved a branch") 13713481Sgiacomo.travaglini@arm.com .prereq(decodeBranchResolved); 13813481Sgiacomo.travaglini@arm.com decodeBranchMispred 13913481Sgiacomo.travaglini@arm.com .name(name() + ".BranchMispred") 14013481Sgiacomo.travaglini@arm.com .desc("Number of times decode detected a branch misprediction") 14113481Sgiacomo.travaglini@arm.com .prereq(decodeBranchMispred); 14213481Sgiacomo.travaglini@arm.com decodeControlMispred 14313481Sgiacomo.travaglini@arm.com .name(name() + ".ControlMispred") 14413481Sgiacomo.travaglini@arm.com .desc("Number of times decode detected an instruction incorrectly" 14513481Sgiacomo.travaglini@arm.com " predicted as a control") 14613481Sgiacomo.travaglini@arm.com .prereq(decodeControlMispred); 14713481Sgiacomo.travaglini@arm.com decodeDecodedInsts 14813481Sgiacomo.travaglini@arm.com .name(name() + ".DecodedInsts") 14913481Sgiacomo.travaglini@arm.com .desc("Number of instructions handled by decode") 15013481Sgiacomo.travaglini@arm.com .prereq(decodeDecodedInsts); 15113481Sgiacomo.travaglini@arm.com decodeSquashedInsts 15213481Sgiacomo.travaglini@arm.com .name(name() + ".SquashedInsts") 15313481Sgiacomo.travaglini@arm.com .desc("Number of squashed instructions handled by decode") 15413481Sgiacomo.travaglini@arm.com .prereq(decodeSquashedInsts); 15513481Sgiacomo.travaglini@arm.com} 15613481Sgiacomo.travaglini@arm.com 15713481Sgiacomo.travaglini@arm.comtemplate<class Impl> 15813481Sgiacomo.travaglini@arm.comvoid 15913481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 16013481Sgiacomo.travaglini@arm.com{ 16113481Sgiacomo.travaglini@arm.com timeBuffer = tb_ptr; 16213481Sgiacomo.travaglini@arm.com 16313481Sgiacomo.travaglini@arm.com // Setup wire to write information back to fetch. 16413481Sgiacomo.travaglini@arm.com toFetch = timeBuffer->getWire(0); 16513481Sgiacomo.travaglini@arm.com 16613481Sgiacomo.travaglini@arm.com // Create wires to get information from proper places in time buffer. 16713481Sgiacomo.travaglini@arm.com fromRename = timeBuffer->getWire(-renameToDecodeDelay); 16813481Sgiacomo.travaglini@arm.com fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 16913481Sgiacomo.travaglini@arm.com fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 17013481Sgiacomo.travaglini@arm.com} 17113481Sgiacomo.travaglini@arm.com 17213481Sgiacomo.travaglini@arm.comtemplate<class Impl> 17313481Sgiacomo.travaglini@arm.comvoid 17413481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 17513481Sgiacomo.travaglini@arm.com{ 17613481Sgiacomo.travaglini@arm.com decodeQueue = dq_ptr; 17713481Sgiacomo.travaglini@arm.com 17813481Sgiacomo.travaglini@arm.com // Setup wire to write information to proper place in decode queue. 17913481Sgiacomo.travaglini@arm.com toRename = decodeQueue->getWire(0); 18013481Sgiacomo.travaglini@arm.com} 18113481Sgiacomo.travaglini@arm.com 18213481Sgiacomo.travaglini@arm.comtemplate<class Impl> 18313481Sgiacomo.travaglini@arm.comvoid 18413481Sgiacomo.travaglini@arm.comDefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 18513481Sgiacomo.travaglini@arm.com{ 18613481Sgiacomo.travaglini@arm.com fetchQueue = fq_ptr; 18713481Sgiacomo.travaglini@arm.com 188 // Setup wire to read information from fetch queue. 189 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 190} 191 192template<class Impl> 193void 194DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 195{ 196 activeThreads = at_ptr; 197} 198 199template <class Impl> 200void 201DefaultDecode<Impl>::drainSanityCheck() const 202{ 203 for (ThreadID tid = 0; tid < numThreads; ++tid) { 204 assert(insts[tid].empty()); 205 assert(skidBuffer[tid].empty()); 206 } 207} 208 209template<class Impl> 210bool 211DefaultDecode<Impl>::checkStall(ThreadID tid) const 212{ 213 bool ret_val = false; 214 215 if (stalls[tid].rename) { 216 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 217 ret_val = true; 218 } else if (stalls[tid].iew) { 219 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 220 ret_val = true; 221 } else if (stalls[tid].commit) { 222 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 223 ret_val = true; 224 } 225 226 return ret_val; 227} 228 229template<class Impl> 230inline bool 231DefaultDecode<Impl>::fetchInstsValid() 232{ 233 return fromFetch->size > 0; 234} 235 236template<class Impl> 237bool 238DefaultDecode<Impl>::block(ThreadID tid) 239{ 240 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 241 242 // Add the current inputs to the skid buffer so they can be 243 // reprocessed when this stage unblocks. 244 skidInsert(tid); 245 246 // If the decode status is blocked or unblocking then decode has not yet 247 // signalled fetch to unblock. In that case, there is no need to tell 248 // fetch to block. 249 if (decodeStatus[tid] != Blocked) { 250 // Set the status to Blocked. 251 decodeStatus[tid] = Blocked; 252 253 if (toFetch->decodeUnblock[tid]) { 254 toFetch->decodeUnblock[tid] = false; 255 } else { 256 toFetch->decodeBlock[tid] = true; 257 wroteToTimeBuffer = true; 258 } 259 260 return true; 261 } 262 263 return false; 264} 265 266template<class Impl> 267bool 268DefaultDecode<Impl>::unblock(ThreadID tid) 269{ 270 // Decode is done unblocking only if the skid buffer is empty. 271 if (skidBuffer[tid].empty()) { 272 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 273 toFetch->decodeUnblock[tid] = true; 274 wroteToTimeBuffer = true; 275 276 decodeStatus[tid] = Running; 277 return true; 278 } 279 280 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 281 282 return false; 283} 284 285template<class Impl> 286void 287DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 288{ 289 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 290 "prediction detected at decode.\n", tid, inst->seqNum); 291 292 // Send back mispredict information. 293 toFetch->decodeInfo[tid].branchMispredict = true; 294 toFetch->decodeInfo[tid].predIncorrect = true; 295 toFetch->decodeInfo[tid].mispredictInst = inst; 296 toFetch->decodeInfo[tid].squash = true; 297 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 298 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 299 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 300 toFetch->decodeInfo[tid].squashInst = inst; 301 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 302 toFetch->decodeInfo[tid].branchTaken = true; 303 } 304 305 InstSeqNum squash_seq_num = inst->seqNum; 306 307 // Might have to tell fetch to unblock. 308 if (decodeStatus[tid] == Blocked || 309 decodeStatus[tid] == Unblocking) { 310 toFetch->decodeUnblock[tid] = 1; 311 } 312 313 // Set status to squashing. 314 decodeStatus[tid] = Squashing; 315 316 for (int i=0; i<fromFetch->size; i++) { 317 if (fromFetch->insts[i]->threadNumber == tid && 318 fromFetch->insts[i]->seqNum > squash_seq_num) { 319 fromFetch->insts[i]->setSquashed(); 320 } 321 } 322 323 // Clear the instruction list and skid buffer in case they have any 324 // insts in them. 325 while (!insts[tid].empty()) { 326 insts[tid].pop(); 327 } 328 329 while (!skidBuffer[tid].empty()) { 330 skidBuffer[tid].pop(); 331 } 332 333 // Squash instructions up until this one 334 cpu->removeInstsUntil(squash_seq_num, tid); 335} 336 337template<class Impl> 338unsigned 339DefaultDecode<Impl>::squash(ThreadID tid) 340{ 341 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 342 343 if (decodeStatus[tid] == Blocked || 344 decodeStatus[tid] == Unblocking) { 345 if (FullSystem) { 346 toFetch->decodeUnblock[tid] = 1; 347 } else { 348 // In syscall emulation, we can have both a block and a squash due 349 // to a syscall in the same cycle. This would cause both signals 350 // to be high. This shouldn't happen in full system. 351 // @todo: Determine if this still happens. 352 if (toFetch->decodeBlock[tid]) 353 toFetch->decodeBlock[tid] = 0; 354 else 355 toFetch->decodeUnblock[tid] = 1; 356 } 357 } 358 359 // Set status to squashing. 360 decodeStatus[tid] = Squashing; 361 362 // Go through incoming instructions from fetch and squash them. 363 unsigned squash_count = 0; 364 365 for (int i=0; i<fromFetch->size; i++) { 366 if (fromFetch->insts[i]->threadNumber == tid) { 367 fromFetch->insts[i]->setSquashed(); 368 squash_count++; 369 } 370 } 371 372 // Clear the instruction list and skid buffer in case they have any 373 // insts in them. 374 while (!insts[tid].empty()) { 375 insts[tid].pop(); 376 } 377 378 while (!skidBuffer[tid].empty()) { 379 skidBuffer[tid].pop(); 380 } 381 382 return squash_count; 383} 384 385template<class Impl> 386void 387DefaultDecode<Impl>::skidInsert(ThreadID tid) 388{ 389 DynInstPtr inst = NULL; 390 391 while (!insts[tid].empty()) { 392 inst = insts[tid].front(); 393 394 insts[tid].pop(); 395 396 assert(tid == inst->threadNumber); 397 398 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n", 399 inst->seqNum, inst->pcState(), inst->threadNumber); 400 401 skidBuffer[tid].push(inst); 402 } 403 404 // @todo: Eventually need to enforce this by not letting a thread 405 // fetch past its skidbuffer 406 assert(skidBuffer[tid].size() <= skidBufferMax); 407} 408 409template<class Impl> 410bool 411DefaultDecode<Impl>::skidsEmpty() 412{ 413 list<ThreadID>::iterator threads = activeThreads->begin(); 414 list<ThreadID>::iterator end = activeThreads->end(); 415 416 while (threads != end) { 417 ThreadID tid = *threads++; 418 if (!skidBuffer[tid].empty()) 419 return false; 420 } 421 422 return true; 423} 424 425template<class Impl> 426void 427DefaultDecode<Impl>::updateStatus() 428{ 429 bool any_unblocking = false; 430 431 list<ThreadID>::iterator threads = activeThreads->begin(); 432 list<ThreadID>::iterator end = activeThreads->end(); 433 434 while (threads != end) { 435 ThreadID tid = *threads++; 436 437 if (decodeStatus[tid] == Unblocking) { 438 any_unblocking = true; 439 break; 440 } 441 } 442 443 // Decode will have activity if it's unblocking. 444 if (any_unblocking) { 445 if (_status == Inactive) { 446 _status = Active; 447 448 DPRINTF(Activity, "Activating stage.\n"); 449 450 cpu->activateStage(O3CPU::DecodeIdx); 451 } 452 } else { 453 // If it's not unblocking, then decode will not have any internal 454 // activity. Switch it to inactive. 455 if (_status == Active) { 456 _status = Inactive; 457 DPRINTF(Activity, "Deactivating stage.\n"); 458 459 cpu->deactivateStage(O3CPU::DecodeIdx); 460 } 461 } 462} 463 464template <class Impl> 465void 466DefaultDecode<Impl>::sortInsts() 467{ 468 int insts_from_fetch = fromFetch->size; 469 for (int i = 0; i < insts_from_fetch; ++i) { 470 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 471 } 472} 473 474template<class Impl> 475void 476DefaultDecode<Impl>::readStallSignals(ThreadID tid) 477{ 478 if (fromRename->renameBlock[tid]) { 479 stalls[tid].rename = true; 480 } 481 482 if (fromRename->renameUnblock[tid]) { 483 assert(stalls[tid].rename); 484 stalls[tid].rename = false; 485 } 486 487 if (fromIEW->iewBlock[tid]) { 488 stalls[tid].iew = true; 489 } 490 491 if (fromIEW->iewUnblock[tid]) { 492 assert(stalls[tid].iew); 493 stalls[tid].iew = false; 494 } 495 496 if (fromCommit->commitBlock[tid]) { 497 stalls[tid].commit = true; 498 } 499 500 if (fromCommit->commitUnblock[tid]) { 501 assert(stalls[tid].commit); 502 stalls[tid].commit = false; 503 } 504} 505 506template <class Impl> 507bool 508DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 509{ 510 // Check if there's a squash signal, squash if there is. 511 // Check stall signals, block if necessary. 512 // If status was blocked 513 // Check if stall conditions have passed 514 // if so then go to unblocking 515 // If status was Squashing 516 // check if squashing is not high. Switch to running this cycle. 517 518 // Update the per thread stall statuses. 519 readStallSignals(tid); 520 521 // Check squash signals from commit. 522 if (fromCommit->commitInfo[tid].squash) { 523 524 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 525 "from commit.\n", tid); 526 527 squash(tid); 528 529 return true; 530 } 531 532 // Check ROB squash signals from commit. 533 if (fromCommit->commitInfo[tid].robSquashing) { 534 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 535 536 // Continue to squash. 537 decodeStatus[tid] = Squashing; 538 539 return true; 540 } 541 542 if (checkStall(tid)) { 543 return block(tid); 544 } 545 546 if (decodeStatus[tid] == Blocked) { 547 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 548 tid); 549 550 decodeStatus[tid] = Unblocking; 551 552 unblock(tid); 553 554 return true; 555 } 556 557 if (decodeStatus[tid] == Squashing) { 558 // Switch status to running if decode isn't being told to block or 559 // squash this cycle. 560 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 561 tid); 562 563 decodeStatus[tid] = Running; 564 565 return false; 566 } 567 568 // If we've reached this point, we have not gotten any signals that 569 // cause decode to change its status. Decode remains the same as before. 570 return false; 571} 572 573template<class Impl> 574void 575DefaultDecode<Impl>::tick() 576{ 577 wroteToTimeBuffer = false; 578 579 bool status_change = false; 580 581 toRenameIndex = 0; 582 583 list<ThreadID>::iterator threads = activeThreads->begin(); 584 list<ThreadID>::iterator end = activeThreads->end(); 585 586 sortInsts(); 587 588 //Check stall and squash signals. 589 while (threads != end) { 590 ThreadID tid = *threads++; 591 592 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 593 status_change = checkSignalsAndUpdate(tid) || status_change; 594 595 decode(status_change, tid); 596 } 597 598 if (status_change) { 599 updateStatus(); 600 } 601 602 if (wroteToTimeBuffer) { 603 DPRINTF(Activity, "Activity this cycle.\n"); 604 605 cpu->activityThisCycle(); 606 } 607} 608 609template<class Impl> 610void 611DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 612{ 613 // If status is Running or idle, 614 // call decodeInsts() 615 // If status is Unblocking, 616 // buffer any instructions coming from fetch 617 // continue trying to empty skid buffer 618 // check if stall conditions have passed 619 620 if (decodeStatus[tid] == Blocked) { 621 ++decodeBlockedCycles; 622 } else if (decodeStatus[tid] == Squashing) { 623 ++decodeSquashCycles; 624 } 625 626 // Decode should try to decode as many instructions as its bandwidth 627 // will allow, as long as it is not currently blocked. 628 if (decodeStatus[tid] == Running || 629 decodeStatus[tid] == Idle) { 630 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 631 "stage.\n",tid); 632 633 decodeInsts(tid); 634 } else if (decodeStatus[tid] == Unblocking) { 635 // Make sure that the skid buffer has something in it if the 636 // status is unblocking. 637 assert(!skidsEmpty()); 638 639 // If the status was unblocking, then instructions from the skid 640 // buffer were used. Remove those instructions and handle 641 // the rest of unblocking. 642 decodeInsts(tid); 643 644 if (fetchInstsValid()) { 645 // Add the current inputs to the skid buffer so they can be 646 // reprocessed when this stage unblocks. 647 skidInsert(tid); 648 } 649 650 status_change = unblock(tid) || status_change; 651 } 652} 653 654template <class Impl> 655void 656DefaultDecode<Impl>::decodeInsts(ThreadID tid) 657{ 658 // Instructions can come either from the skid buffer or the list of 659 // instructions coming from fetch, depending on decode's status. 660 int insts_available = decodeStatus[tid] == Unblocking ? 661 skidBuffer[tid].size() : insts[tid].size(); 662 663 if (insts_available == 0) { 664 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 665 " early.\n",tid); 666 // Should I change the status to idle? 667 ++decodeIdleCycles; 668 return; 669 } else if (decodeStatus[tid] == Unblocking) { 670 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 671 "buffer.\n",tid); 672 ++decodeUnblockCycles; 673 } else if (decodeStatus[tid] == Running) { 674 ++decodeRunCycles; 675 } 676 677 DynInstPtr inst; 678 679 std::queue<DynInstPtr> 680 &insts_to_decode = decodeStatus[tid] == Unblocking ? 681 skidBuffer[tid] : insts[tid]; 682 683 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 684 685 while (insts_available > 0 && toRenameIndex < decodeWidth) { 686 assert(!insts_to_decode.empty()); 687 688 inst = insts_to_decode.front(); 689 690 insts_to_decode.pop(); 691 692 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 693 "PC %s\n", tid, inst->seqNum, inst->pcState()); 694 695 if (inst->isSquashed()) { 696 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 697 "squashed, skipping.\n", 698 tid, inst->seqNum, inst->pcState()); 699 700 ++decodeSquashedInsts; 701 702 --insts_available; 703 704 continue; 705 } 706 707 // Also check if instructions have no source registers. Mark 708 // them as ready to issue at any time. Not sure if this check 709 // should exist here or at a later stage; however it doesn't matter 710 // too much for function correctness. 711 if (inst->numSrcRegs() == 0) { 712 inst->setCanIssue(); 713 } 714 715 // This current instruction is valid, so add it into the decode 716 // queue. The next instruction may not be valid, so check to 717 // see if branches were predicted correctly. 718 toRename->insts[toRenameIndex] = inst; 719 720 ++(toRename->size); 721 ++toRenameIndex; 722 ++decodeDecodedInsts; 723 --insts_available; 724 725#if TRACING_ON 726 if (DTRACE(O3PipeView)) { 727 inst->decodeTick = curTick() - inst->fetchTick; 728 } 729#endif 730 731 // Ensure that if it was predicted as a branch, it really is a 732 // branch. 733 if (inst->readPredTaken() && !inst->isControl()) { 734 panic("Instruction predicted as a branch!"); 735 736 ++decodeControlMispred; 737 738 // Might want to set some sort of boolean and just do 739 // a check at the end 740 squash(inst, inst->threadNumber); 741 742 break; 743 } 744 745 // Go ahead and compute any PC-relative branches. 746 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 747 ++decodeBranchResolved; 748 749 if (!(inst->branchTarget() == inst->readPredTarg())) { 750 ++decodeBranchMispred; 751 752 // Might want to set some sort of boolean and just do 753 // a check at the end 754 squash(inst, inst->threadNumber); 755 TheISA::PCState target = inst->branchTarget(); 756 757 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 758 inst->seqNum, target); 759 //The micro pc after an instruction level branch should be 0 760 inst->setPredTarg(target); 761 break; 762 } 763 } 764 } 765 766 // If we didn't process all instructions, then we will need to block 767 // and put all those instructions into the skid buffer. 768 if (!insts_to_decode.empty()) { 769 block(tid); 770 } 771 772 // Record that decode has written to the time buffer for activity 773 // tracking. 774 if (toRenameIndex) { 775 wroteToTimeBuffer = true; 776 } 777} 778 779#endif//__CPU_O3_DECODE_IMPL_HH__ 780