decode.hh revision 2665
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__ 32#define __CPU_O3_CPU_SIMPLE_DECODE_HH__ 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38 39template<class Impl> 40class SimpleDecode 41{ 42 private: 43 // Typedefs from the Impl. 44 typedef typename Impl::FullCPU FullCPU; 45 typedef typename Impl::DynInstPtr DynInstPtr; 46 typedef typename Impl::Params Params; 47 typedef typename Impl::CPUPol CPUPol; 48 49 // Typedefs from the CPU policy. 50 typedef typename CPUPol::FetchStruct FetchStruct; 51 typedef typename CPUPol::DecodeStruct DecodeStruct; 52 typedef typename CPUPol::TimeStruct TimeStruct; 53 54 public: 55 // The only time decode will become blocked is if dispatch becomes 56 // blocked, which means IQ or ROB is probably full. 57 enum Status { 58 Running, 59 Idle, 60 Squashing, 61 Blocked, 62 Unblocking 63 }; 64 65 private: 66 // May eventually need statuses on a per thread basis. 67 Status _status; 68 69 public: 70 SimpleDecode(Params ¶ms); 71 72 void regStats(); 73 74 void setCPU(FullCPU *cpu_ptr); 75 76 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 77 78 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 79 80 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 81 82 void tick(); 83 84 void decode(); 85 86 private: 87 inline bool fetchInstsValid(); 88 89 void block(); 90 91 inline void unblock(); 92 93 void squash(DynInstPtr &inst); 94 95 public: 96 // Might want to make squash a friend function. 97 void squash(); 98 99 private: 100 // Interfaces to objects outside of decode. 101 /** CPU interface. */ 102 FullCPU *cpu; 103 104 /** Time buffer interface. */ 105 TimeBuffer<TimeStruct> *timeBuffer; 106 107 /** Wire to get rename's output from backwards time buffer. */ 108 typename TimeBuffer<TimeStruct>::wire fromRename; 109 110 /** Wire to get iew's information from backwards time buffer. */ 111 typename TimeBuffer<TimeStruct>::wire fromIEW; 112 113 /** Wire to get commit's information from backwards time buffer. */ 114 typename TimeBuffer<TimeStruct>::wire fromCommit; 115 116 /** Wire to write information heading to previous stages. */ 117 // Might not be the best name as not only fetch will read it. 118 typename TimeBuffer<TimeStruct>::wire toFetch; 119 120 /** Decode instruction queue. */ 121 TimeBuffer<DecodeStruct> *decodeQueue; 122 123 /** Wire used to write any information heading to rename. */ 124 typename TimeBuffer<DecodeStruct>::wire toRename; 125 126 /** Fetch instruction queue interface. */ 127 TimeBuffer<FetchStruct> *fetchQueue; 128 129 /** Wire to get fetch's output from fetch queue. */ 130 typename TimeBuffer<FetchStruct>::wire fromFetch; 131 132 /** Skid buffer between fetch and decode. */ 133 std::queue<FetchStruct> skidBuffer; 134 135 //Consider making these unsigned to avoid any confusion. 136 /** Rename to decode delay, in ticks. */ 137 unsigned renameToDecodeDelay; 138 139 /** IEW to decode delay, in ticks. */ 140 unsigned iewToDecodeDelay; 141 142 /** Commit to decode delay, in ticks. */ 143 unsigned commitToDecodeDelay; 144 145 /** Fetch to decode delay, in ticks. */ 146 unsigned fetchToDecodeDelay; 147 148 /** The width of decode, in instructions. */ 149 unsigned decodeWidth; 150 151 /** The instruction that decode is currently on. It needs to have 152 * persistent state so that when a stall occurs in the middle of a 153 * group of instructions, it can restart at the proper instruction. 154 */ 155 unsigned numInst; 156 157 Stats::Scalar<> decodeIdleCycles; 158 Stats::Scalar<> decodeBlockedCycles; 159 Stats::Scalar<> decodeUnblockCycles; 160 Stats::Scalar<> decodeSquashCycles; 161 Stats::Scalar<> decodeBranchMispred; 162 Stats::Scalar<> decodeControlMispred; 163 Stats::Scalar<> decodeDecodedInsts; 164 Stats::Scalar<> decodeSquashedInsts; 165}; 166 167#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__ 168