decode.hh revision 1461
12SN/A// Todo:
21762SN/A// Add a couple of the branch fields to DynInst.  Figure out where DynInst
32SN/A// should try to compute the target of a PC-relative branch.  Try to avoid
42SN/A// having so many returns within the code.
52SN/A// Fix up squashing too, as it's too
62SN/A// dependent upon the iew stage continually telling it to squash.
72SN/A
82SN/A#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
92SN/A#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
102SN/A
112SN/A#include <queue>
122SN/A
132SN/A#include "base/statistics.hh"
142SN/A#include "base/timebuf.hh"
152SN/A
162SN/Atemplate<class Impl>
172SN/Aclass SimpleDecode
182SN/A{
192SN/A  private:
202SN/A    // Typedefs from the Impl.
212SN/A    typedef typename Impl::ISA ISA;
222SN/A    typedef typename Impl::FullCPU FullCPU;
232SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
242SN/A    typedef typename Impl::Params Params;
252SN/A    typedef typename Impl::CPUPol CPUPol;
262SN/A
272665Ssaidi@eecs.umich.edu    // Typedefs from the CPU policy.
282665Ssaidi@eecs.umich.edu    typedef typename CPUPol::FetchStruct FetchStruct;
292665Ssaidi@eecs.umich.edu    typedef typename CPUPol::DecodeStruct DecodeStruct;
302SN/A    typedef typename CPUPol::TimeStruct TimeStruct;
312SN/A
322SN/A    // Typedefs from the ISA.
332SN/A    typedef typename ISA::Addr Addr;
342SN/A
352520SN/A  public:
362207SN/A    // The only time decode will become blocked is if dispatch becomes
372207SN/A    // blocked, which means IQ or ROB is probably full.
3811389Sbrandon.potter@amd.com    enum Status {
396214Snate@binkert.org        Running,
402SN/A        Idle,
418706Sandreas.hansson@arm.com        Squashing,
422SN/A        Blocked,
432SN/A        Unblocking
442SN/A    };
452SN/A
46360SN/A  private:
47360SN/A    // May eventually need statuses on a per thread basis.
48360SN/A    Status _status;
49360SN/A
502207SN/A  public:
514111Sgblack@eecs.umich.edu    SimpleDecode(Params &params);
524111Sgblack@eecs.umich.edu
534155Sgblack@eecs.umich.edu    void regStats();
545874Sgblack@eecs.umich.edu
555874Sgblack@eecs.umich.edu    void setCPU(FullCPU *cpu_ptr);
5610037SARM gem5 Developers
576691Stjones1@inf.ed.ac.uk    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
587095Sgblack@eecs.umich.edu
596691Stjones1@inf.ed.ac.uk    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
60360SN/A
61360SN/A    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
62360SN/A
63360SN/A    void tick();
64360SN/A
652207SN/A    void decode();
666392Ssaidi@eecs.umich.edu
6710810Sbr@bsdpad.com    // Might want to make squash a friend function.
6810810Sbr@bsdpad.com    void squash();
69360SN/A
70360SN/A  private:
712SN/A    void block();
7212SN/A
7312SN/A    inline void unblock();
742SN/A
752SN/A    void squash(DynInstPtr &inst);
76360SN/A
77360SN/A    // Interfaces to objects outside of decode.
78360SN/A    /** CPU interface. */
7910880SCurtis.Dunham@arm.com    FullCPU *cpu;
80360SN/A
8112SN/A    /** Time buffer interface. */
822SN/A    TimeBuffer<TimeStruct> *timeBuffer;
832SN/A
842SN/A    /** Wire to get rename's output from backwards time buffer. */
8511392Sbrandon.potter@amd.com    typename TimeBuffer<TimeStruct>::wire fromRename;
8611392Sbrandon.potter@amd.com
8711392Sbrandon.potter@amd.com    /** Wire to get iew's information from backwards time buffer. */
8811392Sbrandon.potter@amd.com    typename TimeBuffer<TimeStruct>::wire fromIEW;
8911392Sbrandon.potter@amd.com
9011392Sbrandon.potter@amd.com    /** Wire to get commit's information from backwards time buffer. */
9111392Sbrandon.potter@amd.com    typename TimeBuffer<TimeStruct>::wire fromCommit;
9211392Sbrandon.potter@amd.com
9311392Sbrandon.potter@amd.com    /** Wire to write information heading to previous stages. */
9411392Sbrandon.potter@amd.com    // Might not be the best name as not only fetch will read it.
9511392Sbrandon.potter@amd.com    typename TimeBuffer<TimeStruct>::wire toFetch;
9611392Sbrandon.potter@amd.com
9711392Sbrandon.potter@amd.com    /** Decode instruction queue. */
989641Sguodeyuan@tsinghua.org.cn    TimeBuffer<DecodeStruct> *decodeQueue;
992SN/A
10011389Sbrandon.potter@amd.com    /** Wire used to write any information heading to rename. */
10111389Sbrandon.potter@amd.com    typename TimeBuffer<DecodeStruct>::wire toRename;
10211389Sbrandon.potter@amd.com
10311389Sbrandon.potter@amd.com    /** Fetch instruction queue interface. */
10411389Sbrandon.potter@amd.com    TimeBuffer<FetchStruct> *fetchQueue;
10511389Sbrandon.potter@amd.com
10611389Sbrandon.potter@amd.com    /** Wire to get fetch's output from fetch queue. */
10711389Sbrandon.potter@amd.com    typename TimeBuffer<FetchStruct>::wire fromFetch;
1085070Ssaidi@eecs.umich.edu
1093917Ssaidi@eecs.umich.edu    /** Skid buffer between fetch and decode. */
110360SN/A    std::queue<FetchStruct> skidBuffer;
111360SN/A
112360SN/A  private:
1132SN/A    //Consider making these unsigned to avoid any confusion.
1142SN/A    /** Rename to decode delay, in ticks. */
11512SN/A    unsigned renameToDecodeDelay;
1162420SN/A
1172420SN/A    /** IEW to decode delay, in ticks. */
1182420SN/A    unsigned iewToDecodeDelay;
11912SN/A
12012SN/A    /** Commit to decode delay, in ticks. */
12112SN/A    unsigned commitToDecodeDelay;
12212SN/A
12312SN/A    /** Fetch to decode delay, in ticks. */
12412SN/A    unsigned fetchToDecodeDelay;
12512SN/A
12612SN/A    /** The width of decode, in instructions. */
1272SN/A    unsigned decodeWidth;
12811392Sbrandon.potter@amd.com
12910037SARM gem5 Developers    /** The instruction that decode is currently on.  It needs to have
1302472SN/A     *  persistent state so that when a stall occurs in the middle of a
1312420SN/A     *  group of instructions, it can restart at the proper instruction.
1322SN/A     */
13312SN/A    unsigned numInst;
1342472SN/A
13512SN/A    Stats::Scalar<> decodeIdleCycles;
1362SN/A    Stats::Scalar<> decodeBlockedCycles;
13712SN/A    Stats::Scalar<> decodeUnblockCycles;
13812SN/A    Stats::Scalar<> decodeSquashCycles;
13912SN/A    Stats::Scalar<> decodeBranchMispred;
14012SN/A    Stats::Scalar<> decodeControlMispred;
14112SN/A    Stats::Scalar<> decodeDecodedInsts;
14212SN/A    Stats::Scalar<> decodeSquashedInsts;
14312SN/A};
1443584Ssaidi@eecs.umich.edu
1459261Sdam.sunwoo@arm.com#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
1469261Sdam.sunwoo@arm.com