decode.hh revision 10328:867b536a68be
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2012 ARM Limited 311308Santhony.gutierrez@amd.com * All rights reserved 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * The license below extends only to copyright in the software and shall 611308Santhony.gutierrez@amd.com * not be construed as granting a license to any other intellectual 711308Santhony.gutierrez@amd.com * property including but not limited to intellectual property relating 811308Santhony.gutierrez@amd.com * to a hardware implementation of the functionality of the software 911308Santhony.gutierrez@amd.com * licensed hereunder. You may use the software subject to the license 1011308Santhony.gutierrez@amd.com * terms below provided that you ensure that this notice is replicated 1111308Santhony.gutierrez@amd.com * unmodified and in its entirety in all distributions of the software, 1211308Santhony.gutierrez@amd.com * modified or unmodified, in source code or in binary form. 1311308Santhony.gutierrez@amd.com * 1411308Santhony.gutierrez@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1511308Santhony.gutierrez@amd.com * All rights reserved. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 1811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 1911308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 2011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 2111308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 2211308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 2311308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 2411308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 2511308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 2611308Santhony.gutierrez@amd.com * this software without specific prior written permission. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911308Santhony.gutierrez@amd.com * 4011308Santhony.gutierrez@amd.com * Authors: Kevin Lim 4111308Santhony.gutierrez@amd.com */ 4211308Santhony.gutierrez@amd.com 4311308Santhony.gutierrez@amd.com#ifndef __CPU_O3_DECODE_HH__ 4411308Santhony.gutierrez@amd.com#define __CPU_O3_DECODE_HH__ 4511308Santhony.gutierrez@amd.com 4611308Santhony.gutierrez@amd.com#include <queue> 4711308Santhony.gutierrez@amd.com 4811308Santhony.gutierrez@amd.com#include "base/statistics.hh" 4911308Santhony.gutierrez@amd.com#include "cpu/timebuf.hh" 5011308Santhony.gutierrez@amd.com 5111308Santhony.gutierrez@amd.comstruct DerivO3CPUParams; 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.com/** 5411308Santhony.gutierrez@amd.com * DefaultDecode class handles both single threaded and SMT 5511308Santhony.gutierrez@amd.com * decode. Its width is specified by the parameters; each cycles it 5611308Santhony.gutierrez@amd.com * tries to decode that many instructions. Because instructions are 5711308Santhony.gutierrez@amd.com * actually decoded when the StaticInst is created, this stage does 5811308Santhony.gutierrez@amd.com * not do much other than check any PC-relative branches. 5911308Santhony.gutierrez@amd.com */ 6011308Santhony.gutierrez@amd.comtemplate<class Impl> 6111308Santhony.gutierrez@amd.comclass DefaultDecode 6211308Santhony.gutierrez@amd.com{ 6311308Santhony.gutierrez@amd.com private: 6411308Santhony.gutierrez@amd.com // Typedefs from the Impl. 6511308Santhony.gutierrez@amd.com typedef typename Impl::O3CPU O3CPU; 6611308Santhony.gutierrez@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 6711308Santhony.gutierrez@amd.com typedef typename Impl::CPUPol CPUPol; 6811308Santhony.gutierrez@amd.com 6911308Santhony.gutierrez@amd.com // Typedefs from the CPU policy. 7011308Santhony.gutierrez@amd.com typedef typename CPUPol::FetchStruct FetchStruct; 7111308Santhony.gutierrez@amd.com typedef typename CPUPol::DecodeStruct DecodeStruct; 7211308Santhony.gutierrez@amd.com typedef typename CPUPol::TimeStruct TimeStruct; 7311308Santhony.gutierrez@amd.com 7411308Santhony.gutierrez@amd.com public: 7511308Santhony.gutierrez@amd.com /** Overall decode stage status. Used to determine if the CPU can 7611308Santhony.gutierrez@amd.com * deschedule itself due to a lack of activity. 7711308Santhony.gutierrez@amd.com */ 7811308Santhony.gutierrez@amd.com enum DecodeStatus { 7911308Santhony.gutierrez@amd.com Active, 8011308Santhony.gutierrez@amd.com Inactive 8111308Santhony.gutierrez@amd.com }; 8211308Santhony.gutierrez@amd.com 8311308Santhony.gutierrez@amd.com /** Individual thread status. */ 8411308Santhony.gutierrez@amd.com enum ThreadStatus { 8511308Santhony.gutierrez@amd.com Running, 8611308Santhony.gutierrez@amd.com Idle, 8711308Santhony.gutierrez@amd.com StartSquash, 8811308Santhony.gutierrez@amd.com Squashing, 8911308Santhony.gutierrez@amd.com Blocked, 9011308Santhony.gutierrez@amd.com Unblocking 9111308Santhony.gutierrez@amd.com }; 9211308Santhony.gutierrez@amd.com 9311308Santhony.gutierrez@amd.com private: 9411308Santhony.gutierrez@amd.com /** Decode status. */ 9511308Santhony.gutierrez@amd.com DecodeStatus _status; 9611308Santhony.gutierrez@amd.com 9711308Santhony.gutierrez@amd.com /** Per-thread status. */ 9811308Santhony.gutierrez@amd.com ThreadStatus decodeStatus[Impl::MaxThreads]; 9911308Santhony.gutierrez@amd.com 10011308Santhony.gutierrez@amd.com public: 10111308Santhony.gutierrez@amd.com /** DefaultDecode constructor. */ 10211308Santhony.gutierrez@amd.com DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params); 10311308Santhony.gutierrez@amd.com 10411308Santhony.gutierrez@amd.com void startupStage(); 10511308Santhony.gutierrez@amd.com void resetStage(); 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com /** Returns the name of decode. */ 10811308Santhony.gutierrez@amd.com std::string name() const; 10911308Santhony.gutierrez@amd.com 11011308Santhony.gutierrez@amd.com /** Registers statistics. */ 11111308Santhony.gutierrez@amd.com void regStats(); 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com /** Sets the main backwards communication time buffer pointer. */ 11411308Santhony.gutierrez@amd.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 11511308Santhony.gutierrez@amd.com 11611308Santhony.gutierrez@amd.com /** Sets pointer to time buffer used to communicate to the next stage. */ 11711308Santhony.gutierrez@amd.com void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 11811308Santhony.gutierrez@amd.com 11911308Santhony.gutierrez@amd.com /** Sets pointer to time buffer coming from fetch. */ 12011308Santhony.gutierrez@amd.com void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 12111308Santhony.gutierrez@amd.com 12211308Santhony.gutierrez@amd.com /** Sets pointer to list of active threads. */ 12311308Santhony.gutierrez@amd.com void setActiveThreads(std::list<ThreadID> *at_ptr); 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com /** Perform sanity checks after a drain. */ 12611308Santhony.gutierrez@amd.com void drainSanityCheck() const; 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.com /** Has the stage drained? */ 12911308Santhony.gutierrez@amd.com bool isDrained() const; 13011308Santhony.gutierrez@amd.com 13111308Santhony.gutierrez@amd.com /** Takes over from another CPU's thread. */ 13211308Santhony.gutierrez@amd.com void takeOverFrom() { resetStage(); } 13311308Santhony.gutierrez@amd.com 13411308Santhony.gutierrez@amd.com /** Ticks decode, processing all input signals and decoding as many 13511308Santhony.gutierrez@amd.com * instructions as possible. 13611308Santhony.gutierrez@amd.com */ 13711308Santhony.gutierrez@amd.com void tick(); 13811308Santhony.gutierrez@amd.com 13911308Santhony.gutierrez@amd.com /** Determines what to do based on decode's current status. 14011308Santhony.gutierrez@amd.com * @param status_change decode() sets this variable if there was a status 14111308Santhony.gutierrez@amd.com * change (ie switching from from blocking to unblocking). 14211308Santhony.gutierrez@amd.com * @param tid Thread id to decode instructions from. 14311308Santhony.gutierrez@amd.com */ 14411308Santhony.gutierrez@amd.com void decode(bool &status_change, ThreadID tid); 14511308Santhony.gutierrez@amd.com 14611308Santhony.gutierrez@amd.com /** Processes instructions from fetch and passes them on to rename. 14711308Santhony.gutierrez@amd.com * Decoding of instructions actually happens when they are created in 14811308Santhony.gutierrez@amd.com * fetch, so this function mostly checks if PC-relative branches are 14911308Santhony.gutierrez@amd.com * correct. 15011308Santhony.gutierrez@amd.com */ 15111308Santhony.gutierrez@amd.com void decodeInsts(ThreadID tid); 15211308Santhony.gutierrez@amd.com 15311308Santhony.gutierrez@amd.com private: 15411308Santhony.gutierrez@amd.com /** Inserts a thread's instructions into the skid buffer, to be decoded 15511308Santhony.gutierrez@amd.com * once decode unblocks. 15611308Santhony.gutierrez@amd.com */ 15711308Santhony.gutierrez@amd.com void skidInsert(ThreadID tid); 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.com /** Returns if all of the skid buffers are empty. */ 16011308Santhony.gutierrez@amd.com bool skidsEmpty(); 16111308Santhony.gutierrez@amd.com 16211308Santhony.gutierrez@amd.com /** Updates overall decode status based on all of the threads' statuses. */ 16311308Santhony.gutierrez@amd.com void updateStatus(); 16411308Santhony.gutierrez@amd.com 16511308Santhony.gutierrez@amd.com /** Separates instructions from fetch into individual lists of instructions 16611308Santhony.gutierrez@amd.com * sorted by thread. 16711308Santhony.gutierrez@amd.com */ 16811308Santhony.gutierrez@amd.com void sortInsts(); 16911308Santhony.gutierrez@amd.com 17011308Santhony.gutierrez@amd.com /** Reads all stall signals from the backwards communication timebuffer. */ 17111308Santhony.gutierrez@amd.com void readStallSignals(ThreadID tid); 17211308Santhony.gutierrez@amd.com 17311308Santhony.gutierrez@amd.com /** Checks all input signals and updates decode's status appropriately. */ 17411308Santhony.gutierrez@amd.com bool checkSignalsAndUpdate(ThreadID tid); 17511308Santhony.gutierrez@amd.com 17611308Santhony.gutierrez@amd.com /** Checks all stall signals, and returns if any are true. */ 17711308Santhony.gutierrez@amd.com bool checkStall(ThreadID tid) const; 17811308Santhony.gutierrez@amd.com 17911308Santhony.gutierrez@amd.com /** Returns if there any instructions from fetch on this cycle. */ 18011308Santhony.gutierrez@amd.com inline bool fetchInstsValid(); 18111308Santhony.gutierrez@amd.com 18211308Santhony.gutierrez@amd.com /** Switches decode to blocking, and signals back that decode has 18311308Santhony.gutierrez@amd.com * become blocked. 18411308Santhony.gutierrez@amd.com * @return Returns true if there is a status change. 18511308Santhony.gutierrez@amd.com */ 18611308Santhony.gutierrez@amd.com bool block(ThreadID tid); 18711308Santhony.gutierrez@amd.com 18811308Santhony.gutierrez@amd.com /** Switches decode to unblocking if the skid buffer is empty, and 18911308Santhony.gutierrez@amd.com * signals back that decode has unblocked. 19011308Santhony.gutierrez@amd.com * @return Returns true if there is a status change. 19111308Santhony.gutierrez@amd.com */ 19211308Santhony.gutierrez@amd.com bool unblock(ThreadID tid); 19311308Santhony.gutierrez@amd.com 19411308Santhony.gutierrez@amd.com /** Squashes if there is a PC-relative branch that was predicted 19511308Santhony.gutierrez@amd.com * incorrectly. Sends squash information back to fetch. 19611308Santhony.gutierrez@amd.com */ 19711308Santhony.gutierrez@amd.com void squash(DynInstPtr &inst, ThreadID tid); 19811308Santhony.gutierrez@amd.com 19911308Santhony.gutierrez@amd.com public: 20011308Santhony.gutierrez@amd.com /** Squashes due to commit signalling a squash. Changes status to 20111308Santhony.gutierrez@amd.com * squashing and clears block/unblock signals as needed. 20211308Santhony.gutierrez@amd.com */ 20311308Santhony.gutierrez@amd.com unsigned squash(ThreadID tid); 20411308Santhony.gutierrez@amd.com 20511308Santhony.gutierrez@amd.com private: 20611308Santhony.gutierrez@amd.com // Interfaces to objects outside of decode. 20711308Santhony.gutierrez@amd.com /** CPU interface. */ 20811308Santhony.gutierrez@amd.com O3CPU *cpu; 20911308Santhony.gutierrez@amd.com 21011308Santhony.gutierrez@amd.com /** Time buffer interface. */ 21111308Santhony.gutierrez@amd.com TimeBuffer<TimeStruct> *timeBuffer; 21211308Santhony.gutierrez@amd.com 21311308Santhony.gutierrez@amd.com /** Wire to get rename's output from backwards time buffer. */ 21411308Santhony.gutierrez@amd.com typename TimeBuffer<TimeStruct>::wire fromRename; 21511308Santhony.gutierrez@amd.com 21611308Santhony.gutierrez@amd.com /** Wire to get iew's information from backwards time buffer. */ 21711308Santhony.gutierrez@amd.com typename TimeBuffer<TimeStruct>::wire fromIEW; 21811308Santhony.gutierrez@amd.com 21911308Santhony.gutierrez@amd.com /** Wire to get commit's information from backwards time buffer. */ 22011308Santhony.gutierrez@amd.com typename TimeBuffer<TimeStruct>::wire fromCommit; 22111308Santhony.gutierrez@amd.com 22211308Santhony.gutierrez@amd.com /** Wire to write information heading to previous stages. */ 22311308Santhony.gutierrez@amd.com // Might not be the best name as not only fetch will read it. 22411308Santhony.gutierrez@amd.com typename TimeBuffer<TimeStruct>::wire toFetch; 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.com /** Decode instruction queue. */ 22711308Santhony.gutierrez@amd.com TimeBuffer<DecodeStruct> *decodeQueue; 22811308Santhony.gutierrez@amd.com 22911308Santhony.gutierrez@amd.com /** Wire used to write any information heading to rename. */ 23011308Santhony.gutierrez@amd.com typename TimeBuffer<DecodeStruct>::wire toRename; 23111308Santhony.gutierrez@amd.com 23211308Santhony.gutierrez@amd.com /** Fetch instruction queue interface. */ 23311308Santhony.gutierrez@amd.com TimeBuffer<FetchStruct> *fetchQueue; 23411308Santhony.gutierrez@amd.com 23511308Santhony.gutierrez@amd.com /** Wire to get fetch's output from fetch queue. */ 23611308Santhony.gutierrez@amd.com typename TimeBuffer<FetchStruct>::wire fromFetch; 23711308Santhony.gutierrez@amd.com 23811308Santhony.gutierrez@amd.com /** Queue of all instructions coming from fetch this cycle. */ 23911308Santhony.gutierrez@amd.com std::queue<DynInstPtr> insts[Impl::MaxThreads]; 24011308Santhony.gutierrez@amd.com 24111308Santhony.gutierrez@amd.com /** Skid buffer between fetch and decode. */ 24211308Santhony.gutierrez@amd.com std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 24311308Santhony.gutierrez@amd.com 24411308Santhony.gutierrez@amd.com /** Variable that tracks if decode has written to the time buffer this 24511308Santhony.gutierrez@amd.com * cycle. Used to tell CPU if there is activity this cycle. 24611308Santhony.gutierrez@amd.com */ 24711308Santhony.gutierrez@amd.com bool wroteToTimeBuffer; 24811308Santhony.gutierrez@amd.com 24911308Santhony.gutierrez@amd.com /** Source of possible stalls. */ 25011308Santhony.gutierrez@amd.com struct Stalls { 25111308Santhony.gutierrez@amd.com bool rename; 25211308Santhony.gutierrez@amd.com }; 25311308Santhony.gutierrez@amd.com 25411308Santhony.gutierrez@amd.com /** Tracks which stages are telling decode to stall. */ 25511308Santhony.gutierrez@amd.com Stalls stalls[Impl::MaxThreads]; 25611308Santhony.gutierrez@amd.com 25711308Santhony.gutierrez@amd.com /** Rename to decode delay. */ 25811308Santhony.gutierrez@amd.com Cycles renameToDecodeDelay; 25911308Santhony.gutierrez@amd.com 26011308Santhony.gutierrez@amd.com /** IEW to decode delay. */ 26111308Santhony.gutierrez@amd.com Cycles iewToDecodeDelay; 26211308Santhony.gutierrez@amd.com 26311308Santhony.gutierrez@amd.com /** Commit to decode delay. */ 26411308Santhony.gutierrez@amd.com Cycles commitToDecodeDelay; 26511308Santhony.gutierrez@amd.com 26611308Santhony.gutierrez@amd.com /** Fetch to decode delay. */ 26711308Santhony.gutierrez@amd.com Cycles fetchToDecodeDelay; 26811308Santhony.gutierrez@amd.com 26911308Santhony.gutierrez@amd.com /** The width of decode, in instructions. */ 27011308Santhony.gutierrez@amd.com unsigned decodeWidth; 27111308Santhony.gutierrez@amd.com 27211308Santhony.gutierrez@amd.com /** Index of instructions being sent to rename. */ 27311308Santhony.gutierrez@amd.com unsigned toRenameIndex; 27411308Santhony.gutierrez@amd.com 27511308Santhony.gutierrez@amd.com /** number of Active Threads*/ 27611308Santhony.gutierrez@amd.com ThreadID numThreads; 27711308Santhony.gutierrez@amd.com 27811308Santhony.gutierrez@amd.com /** List of active thread ids */ 27911308Santhony.gutierrez@amd.com std::list<ThreadID> *activeThreads; 28011308Santhony.gutierrez@amd.com 28111308Santhony.gutierrez@amd.com /** Maximum size of the skid buffer. */ 28211308Santhony.gutierrez@amd.com unsigned skidBufferMax; 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/ 28511308Santhony.gutierrez@amd.com Addr bdelayDoneSeqNum[Impl::MaxThreads]; 28611308Santhony.gutierrez@amd.com 28711308Santhony.gutierrez@amd.com /** Instruction used for squashing branch (used for MIPS)*/ 28811308Santhony.gutierrez@amd.com DynInstPtr squashInst[Impl::MaxThreads]; 28911308Santhony.gutierrez@amd.com 29011308Santhony.gutierrez@amd.com /** Tells when their is a pending delay slot inst. to send 29111308Santhony.gutierrez@amd.com * to rename. If there is, then wait squash after the next 29211308Santhony.gutierrez@amd.com * instruction (used for MIPS). 29311308Santhony.gutierrez@amd.com */ 29411308Santhony.gutierrez@amd.com bool squashAfterDelaySlot[Impl::MaxThreads]; 29511308Santhony.gutierrez@amd.com 29611308Santhony.gutierrez@amd.com 29711308Santhony.gutierrez@amd.com /** Stat for total number of idle cycles. */ 29811308Santhony.gutierrez@amd.com Stats::Scalar decodeIdleCycles; 29911308Santhony.gutierrez@amd.com /** Stat for total number of blocked cycles. */ 30011308Santhony.gutierrez@amd.com Stats::Scalar decodeBlockedCycles; 30111308Santhony.gutierrez@amd.com /** Stat for total number of normal running cycles. */ 30211308Santhony.gutierrez@amd.com Stats::Scalar decodeRunCycles; 30311308Santhony.gutierrez@amd.com /** Stat for total number of unblocking cycles. */ 30411308Santhony.gutierrez@amd.com Stats::Scalar decodeUnblockCycles; 30511308Santhony.gutierrez@amd.com /** Stat for total number of squashing cycles. */ 30611308Santhony.gutierrez@amd.com Stats::Scalar decodeSquashCycles; 30711308Santhony.gutierrez@amd.com /** Stat for number of times a branch is resolved at decode. */ 30811308Santhony.gutierrez@amd.com Stats::Scalar decodeBranchResolved; 30911308Santhony.gutierrez@amd.com /** Stat for number of times a branch mispredict is detected. */ 31011308Santhony.gutierrez@amd.com Stats::Scalar decodeBranchMispred; 31111308Santhony.gutierrez@amd.com /** Stat for number of times decode detected a non-control instruction 31211308Santhony.gutierrez@amd.com * incorrectly predicted as a branch. 31311308Santhony.gutierrez@amd.com */ 31411308Santhony.gutierrez@amd.com Stats::Scalar decodeControlMispred; 31511308Santhony.gutierrez@amd.com /** Stat for total number of decoded instructions. */ 31611308Santhony.gutierrez@amd.com Stats::Scalar decodeDecodedInsts; 31711308Santhony.gutierrez@amd.com /** Stat for total number of squashed instructions. */ 31811308Santhony.gutierrez@amd.com Stats::Scalar decodeSquashedInsts; 31911308Santhony.gutierrez@amd.com}; 32011308Santhony.gutierrez@amd.com 32111308Santhony.gutierrez@amd.com#endif // __CPU_O3_DECODE_HH__ 32211308Santhony.gutierrez@amd.com