decode.hh revision 2863
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301060SN/A 312292SN/A#ifndef __CPU_O3_DECODE_HH__ 322292SN/A#define __CPU_O3_DECODE_HH__ 331060SN/A 341060SN/A#include <queue> 351060SN/A 361461SN/A#include "base/statistics.hh" 371060SN/A#include "base/timebuf.hh" 381060SN/A 392292SN/A/** 402329SN/A * DefaultDecode class handles both single threaded and SMT 412329SN/A * decode. Its width is specified by the parameters; each cycles it 422329SN/A * tries to decode that many instructions. Because instructions are 432329SN/A * actually decoded when the StaticInst is created, this stage does 442329SN/A * not do much other than check any PC-relative branches. 452292SN/A */ 461060SN/Atemplate<class Impl> 472292SN/Aclass DefaultDecode 481060SN/A{ 491060SN/A private: 501060SN/A // Typedefs from the Impl. 512733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 521061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 531060SN/A typedef typename Impl::Params Params; 541061SN/A typedef typename Impl::CPUPol CPUPol; 551060SN/A 561061SN/A // Typedefs from the CPU policy. 571061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 581061SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 591061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 601060SN/A 611060SN/A public: 622292SN/A /** Overall decode stage status. Used to determine if the CPU can 632292SN/A * deschedule itself due to a lack of activity. 642292SN/A */ 652292SN/A enum DecodeStatus { 662292SN/A Active, 672292SN/A Inactive 682292SN/A }; 692292SN/A 702292SN/A /** Individual thread status. */ 712292SN/A enum ThreadStatus { 721060SN/A Running, 731060SN/A Idle, 742292SN/A StartSquash, 751060SN/A Squashing, 761060SN/A Blocked, 771060SN/A Unblocking 781060SN/A }; 791060SN/A 801060SN/A private: 812292SN/A /** Decode status. */ 822292SN/A DecodeStatus _status; 832292SN/A 842292SN/A /** Per-thread status. */ 852292SN/A ThreadStatus decodeStatus[Impl::MaxThreads]; 861060SN/A 871060SN/A public: 882292SN/A /** DefaultDecode constructor. */ 892292SN/A DefaultDecode(Params *params); 901060SN/A 912292SN/A /** Returns the name of decode. */ 922292SN/A std::string name() const; 932292SN/A 942292SN/A /** Registers statistics. */ 951062SN/A void regStats(); 961062SN/A 972292SN/A /** Sets CPU pointer. */ 982733Sktlim@umich.edu void setCPU(O3CPU *cpu_ptr); 991060SN/A 1002292SN/A /** Sets the main backwards communication time buffer pointer. */ 1011060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1021060SN/A 1032292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1041060SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 1051060SN/A 1062292SN/A /** Sets pointer to time buffer coming from fetch. */ 1071060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1081060SN/A 1092292SN/A /** Sets pointer to list of active threads. */ 1102292SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 1112292SN/A 1122843Sktlim@umich.edu /** Drains the decode stage. */ 1132863Sktlim@umich.edu bool drain(); 1142843Sktlim@umich.edu 1152843Sktlim@umich.edu /** Resumes execution after a drain. */ 1162843Sktlim@umich.edu void resume() { } 1172843Sktlim@umich.edu 1182348SN/A /** Switches out the decode stage. */ 1192843Sktlim@umich.edu void switchOut() { } 1202307SN/A 1212348SN/A /** Takes over from another CPU's thread. */ 1222307SN/A void takeOverFrom(); 1232348SN/A 1242292SN/A /** Ticks decode, processing all input signals and decoding as many 1252292SN/A * instructions as possible. 1262292SN/A */ 1271060SN/A void tick(); 1281060SN/A 1292292SN/A /** Determines what to do based on decode's current status. 1302292SN/A * @param status_change decode() sets this variable if there was a status 1312292SN/A * change (ie switching from from blocking to unblocking). 1322292SN/A * @param tid Thread id to decode instructions from. 1332292SN/A */ 1342292SN/A void decode(bool &status_change, unsigned tid); 1352292SN/A 1362292SN/A /** Processes instructions from fetch and passes them on to rename. 1372292SN/A * Decoding of instructions actually happens when they are created in 1382292SN/A * fetch, so this function mostly checks if PC-relative branches are 1392292SN/A * correct. 1402292SN/A */ 1412292SN/A void decodeInsts(unsigned tid); 1421060SN/A 1431060SN/A private: 1442292SN/A /** Inserts a thread's instructions into the skid buffer, to be decoded 1452292SN/A * once decode unblocks. 1462292SN/A */ 1472292SN/A void skidInsert(unsigned tid); 1482292SN/A 1492292SN/A /** Returns if all of the skid buffers are empty. */ 1502292SN/A bool skidsEmpty(); 1512292SN/A 1522292SN/A /** Updates overall decode status based on all of the threads' statuses. */ 1532292SN/A void updateStatus(); 1542292SN/A 1552292SN/A /** Separates instructions from fetch into individual lists of instructions 1562292SN/A * sorted by thread. 1572292SN/A */ 1582292SN/A void sortInsts(); 1592292SN/A 1602292SN/A /** Reads all stall signals from the backwards communication timebuffer. */ 1612292SN/A void readStallSignals(unsigned tid); 1622292SN/A 1632292SN/A /** Checks all input signals and updates decode's status appropriately. */ 1642292SN/A bool checkSignalsAndUpdate(unsigned tid); 1652292SN/A 1662292SN/A /** Checks all stall signals, and returns if any are true. */ 1672292SN/A bool checkStall(unsigned tid) const; 1682292SN/A 1692292SN/A /** Returns if there any instructions from fetch on this cycle. */ 1701681SN/A inline bool fetchInstsValid(); 1711681SN/A 1722292SN/A /** Switches decode to blocking, and signals back that decode has 1732292SN/A * become blocked. 1742292SN/A * @return Returns true if there is a status change. 1752292SN/A */ 1762292SN/A bool block(unsigned tid); 1771060SN/A 1782292SN/A /** Switches decode to unblocking if the skid buffer is empty, and 1792292SN/A * signals back that decode has unblocked. 1802292SN/A * @return Returns true if there is a status change. 1812292SN/A */ 1822292SN/A bool unblock(unsigned tid); 1831060SN/A 1842292SN/A /** Squashes if there is a PC-relative branch that was predicted 1852292SN/A * incorrectly. Sends squash information back to fetch. 1862292SN/A */ 1872292SN/A void squash(DynInstPtr &inst, unsigned tid); 1881060SN/A 1891684SN/A public: 1902292SN/A /** Squashes due to commit signalling a squash. Changes status to 1912292SN/A * squashing and clears block/unblock signals as needed. 1922292SN/A */ 1932292SN/A unsigned squash(unsigned tid); 1941681SN/A 1951684SN/A private: 1961060SN/A // Interfaces to objects outside of decode. 1971060SN/A /** CPU interface. */ 1982733Sktlim@umich.edu O3CPU *cpu; 1991060SN/A 2001060SN/A /** Time buffer interface. */ 2011060SN/A TimeBuffer<TimeStruct> *timeBuffer; 2021060SN/A 2031060SN/A /** Wire to get rename's output from backwards time buffer. */ 2041060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 2051060SN/A 2061060SN/A /** Wire to get iew's information from backwards time buffer. */ 2071060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 2081060SN/A 2091060SN/A /** Wire to get commit's information from backwards time buffer. */ 2101060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 2111060SN/A 2121060SN/A /** Wire to write information heading to previous stages. */ 2131060SN/A // Might not be the best name as not only fetch will read it. 2141060SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 2151060SN/A 2161060SN/A /** Decode instruction queue. */ 2171060SN/A TimeBuffer<DecodeStruct> *decodeQueue; 2181060SN/A 2191060SN/A /** Wire used to write any information heading to rename. */ 2201060SN/A typename TimeBuffer<DecodeStruct>::wire toRename; 2211060SN/A 2221060SN/A /** Fetch instruction queue interface. */ 2231060SN/A TimeBuffer<FetchStruct> *fetchQueue; 2241060SN/A 2251060SN/A /** Wire to get fetch's output from fetch queue. */ 2261060SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 2271060SN/A 2282292SN/A /** Queue of all instructions coming from fetch this cycle. */ 2292292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 2302292SN/A 2311060SN/A /** Skid buffer between fetch and decode. */ 2322292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 2331060SN/A 2342292SN/A /** Variable that tracks if decode has written to the time buffer this 2352292SN/A * cycle. Used to tell CPU if there is activity this cycle. 2362292SN/A */ 2372292SN/A bool wroteToTimeBuffer; 2382292SN/A 2392292SN/A /** Source of possible stalls. */ 2402292SN/A struct Stalls { 2412292SN/A bool rename; 2422292SN/A bool iew; 2432292SN/A bool commit; 2442292SN/A }; 2452292SN/A 2462292SN/A /** Tracks which stages are telling decode to stall. */ 2472292SN/A Stalls stalls[Impl::MaxThreads]; 2482292SN/A 2491060SN/A /** Rename to decode delay, in ticks. */ 2501060SN/A unsigned renameToDecodeDelay; 2511060SN/A 2521060SN/A /** IEW to decode delay, in ticks. */ 2531060SN/A unsigned iewToDecodeDelay; 2541060SN/A 2551060SN/A /** Commit to decode delay, in ticks. */ 2561060SN/A unsigned commitToDecodeDelay; 2571060SN/A 2581060SN/A /** Fetch to decode delay, in ticks. */ 2591060SN/A unsigned fetchToDecodeDelay; 2601060SN/A 2611060SN/A /** The width of decode, in instructions. */ 2621060SN/A unsigned decodeWidth; 2631061SN/A 2642292SN/A /** Index of instructions being sent to rename. */ 2652292SN/A unsigned toRenameIndex; 2662292SN/A 2672292SN/A /** number of Active Threads*/ 2682292SN/A unsigned numThreads; 2692292SN/A 2702292SN/A /** List of active thread ids */ 2712292SN/A std::list<unsigned> *activeThreads; 2722292SN/A 2732292SN/A /** Number of branches in flight. */ 2742292SN/A unsigned branchCount[Impl::MaxThreads]; 2752292SN/A 2762292SN/A /** Maximum size of the skid buffer. */ 2772292SN/A unsigned skidBufferMax; 2782292SN/A 2792292SN/A /** Stat for total number of idle cycles. */ 2802292SN/A Stats::Scalar<> decodeIdleCycles; 2812292SN/A /** Stat for total number of blocked cycles. */ 2822292SN/A Stats::Scalar<> decodeBlockedCycles; 2832292SN/A /** Stat for total number of normal running cycles. */ 2842292SN/A Stats::Scalar<> decodeRunCycles; 2852292SN/A /** Stat for total number of unblocking cycles. */ 2862292SN/A Stats::Scalar<> decodeUnblockCycles; 2872292SN/A /** Stat for total number of squashing cycles. */ 2882292SN/A Stats::Scalar<> decodeSquashCycles; 2892307SN/A /** Stat for number of times a branch is resolved at decode. */ 2902307SN/A Stats::Scalar<> decodeBranchResolved; 2912292SN/A /** Stat for number of times a branch mispredict is detected. */ 2922292SN/A Stats::Scalar<> decodeBranchMispred; 2932292SN/A /** Stat for number of times decode detected a non-control instruction 2942292SN/A * incorrectly predicted as a branch. 2951061SN/A */ 2961062SN/A Stats::Scalar<> decodeControlMispred; 2972292SN/A /** Stat for total number of decoded instructions. */ 2981062SN/A Stats::Scalar<> decodeDecodedInsts; 2992292SN/A /** Stat for total number of squashed instructions. */ 3001062SN/A Stats::Scalar<> decodeSquashedInsts; 3011060SN/A}; 3021060SN/A 3032292SN/A#endif // __CPU_O3_DECODE_HH__ 304