decode.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_DECODE_HH__
30#define __CPU_O3_DECODE_HH__
31
32#include <queue>
33
34#include "base/statistics.hh"
35#include "base/timebuf.hh"
36
37/**
38 * DefaultDecode class handles both single threaded and SMT
39 * decode. Its width is specified by the parameters; each cycles it
40 * tries to decode that many instructions. Because instructions are
41 * actually decoded when the StaticInst is created, this stage does
42 * not do much other than check any PC-relative branches.
43 */
44template<class Impl>
45class DefaultDecode
46{
47  private:
48    // Typedefs from the Impl.
49    typedef typename Impl::FullCPU FullCPU;
50    typedef typename Impl::DynInstPtr DynInstPtr;
51    typedef typename Impl::Params Params;
52    typedef typename Impl::CPUPol CPUPol;
53
54    // Typedefs from the CPU policy.
55    typedef typename CPUPol::FetchStruct FetchStruct;
56    typedef typename CPUPol::DecodeStruct DecodeStruct;
57    typedef typename CPUPol::TimeStruct TimeStruct;
58
59  public:
60    /** Overall decode stage status. Used to determine if the CPU can
61     * deschedule itself due to a lack of activity.
62     */
63    enum DecodeStatus {
64        Active,
65        Inactive
66    };
67
68    /** Individual thread status. */
69    enum ThreadStatus {
70        Running,
71        Idle,
72        StartSquash,
73        Squashing,
74        Blocked,
75        Unblocking
76    };
77
78  private:
79    /** Decode status. */
80    DecodeStatus _status;
81
82    /** Per-thread status. */
83    ThreadStatus decodeStatus[Impl::MaxThreads];
84
85  public:
86    /** DefaultDecode constructor. */
87    DefaultDecode(Params *params);
88
89    /** Returns the name of decode. */
90    std::string name() const;
91
92    /** Registers statistics. */
93    void regStats();
94
95    /** Sets CPU pointer. */
96    void setCPU(FullCPU *cpu_ptr);
97
98    /** Sets the main backwards communication time buffer pointer. */
99    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
100
101    /** Sets pointer to time buffer used to communicate to the next stage. */
102    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
103
104    /** Sets pointer to time buffer coming from fetch. */
105    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
106
107    /** Sets pointer to list of active threads. */
108    void setActiveThreads(std::list<unsigned> *at_ptr);
109
110    /** Switches out the decode stage. */
111    void switchOut();
112
113    /** Takes over from another CPU's thread. */
114    void takeOverFrom();
115
116    /** Ticks decode, processing all input signals and decoding as many
117     * instructions as possible.
118     */
119    void tick();
120
121    /** Determines what to do based on decode's current status.
122     * @param status_change decode() sets this variable if there was a status
123     * change (ie switching from from blocking to unblocking).
124     * @param tid Thread id to decode instructions from.
125     */
126    void decode(bool &status_change, unsigned tid);
127
128    /** Processes instructions from fetch and passes them on to rename.
129     * Decoding of instructions actually happens when they are created in
130     * fetch, so this function mostly checks if PC-relative branches are
131     * correct.
132     */
133    void decodeInsts(unsigned tid);
134
135  private:
136    /** Inserts a thread's instructions into the skid buffer, to be decoded
137     * once decode unblocks.
138     */
139    void skidInsert(unsigned tid);
140
141    /** Returns if all of the skid buffers are empty. */
142    bool skidsEmpty();
143
144    /** Updates overall decode status based on all of the threads' statuses. */
145    void updateStatus();
146
147    /** Separates instructions from fetch into individual lists of instructions
148     * sorted by thread.
149     */
150    void sortInsts();
151
152    /** Reads all stall signals from the backwards communication timebuffer. */
153    void readStallSignals(unsigned tid);
154
155    /** Checks all input signals and updates decode's status appropriately. */
156    bool checkSignalsAndUpdate(unsigned tid);
157
158    /** Checks all stall signals, and returns if any are true. */
159    bool checkStall(unsigned tid) const;
160
161    /** Returns if there any instructions from fetch on this cycle. */
162    inline bool fetchInstsValid();
163
164    /** Switches decode to blocking, and signals back that decode has
165     * become blocked.
166     * @return Returns true if there is a status change.
167     */
168    bool block(unsigned tid);
169
170    /** Switches decode to unblocking if the skid buffer is empty, and
171     * signals back that decode has unblocked.
172     * @return Returns true if there is a status change.
173     */
174    bool unblock(unsigned tid);
175
176    /** Squashes if there is a PC-relative branch that was predicted
177     * incorrectly. Sends squash information back to fetch.
178     */
179    void squash(DynInstPtr &inst, unsigned tid);
180
181  public:
182    /** Squashes due to commit signalling a squash. Changes status to
183     * squashing and clears block/unblock signals as needed.
184     */
185    unsigned squash(unsigned tid);
186
187  private:
188    // Interfaces to objects outside of decode.
189    /** CPU interface. */
190    FullCPU *cpu;
191
192    /** Time buffer interface. */
193    TimeBuffer<TimeStruct> *timeBuffer;
194
195    /** Wire to get rename's output from backwards time buffer. */
196    typename TimeBuffer<TimeStruct>::wire fromRename;
197
198    /** Wire to get iew's information from backwards time buffer. */
199    typename TimeBuffer<TimeStruct>::wire fromIEW;
200
201    /** Wire to get commit's information from backwards time buffer. */
202    typename TimeBuffer<TimeStruct>::wire fromCommit;
203
204    /** Wire to write information heading to previous stages. */
205    // Might not be the best name as not only fetch will read it.
206    typename TimeBuffer<TimeStruct>::wire toFetch;
207
208    /** Decode instruction queue. */
209    TimeBuffer<DecodeStruct> *decodeQueue;
210
211    /** Wire used to write any information heading to rename. */
212    typename TimeBuffer<DecodeStruct>::wire toRename;
213
214    /** Fetch instruction queue interface. */
215    TimeBuffer<FetchStruct> *fetchQueue;
216
217    /** Wire to get fetch's output from fetch queue. */
218    typename TimeBuffer<FetchStruct>::wire fromFetch;
219
220    /** Queue of all instructions coming from fetch this cycle. */
221    std::queue<DynInstPtr> insts[Impl::MaxThreads];
222
223    /** Skid buffer between fetch and decode. */
224    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
225
226    /** Variable that tracks if decode has written to the time buffer this
227     * cycle. Used to tell CPU if there is activity this cycle.
228     */
229    bool wroteToTimeBuffer;
230
231    /** Source of possible stalls. */
232    struct Stalls {
233        bool rename;
234        bool iew;
235        bool commit;
236    };
237
238    /** Tracks which stages are telling decode to stall. */
239    Stalls stalls[Impl::MaxThreads];
240
241    /** Rename to decode delay, in ticks. */
242    unsigned renameToDecodeDelay;
243
244    /** IEW to decode delay, in ticks. */
245    unsigned iewToDecodeDelay;
246
247    /** Commit to decode delay, in ticks. */
248    unsigned commitToDecodeDelay;
249
250    /** Fetch to decode delay, in ticks. */
251    unsigned fetchToDecodeDelay;
252
253    /** The width of decode, in instructions. */
254    unsigned decodeWidth;
255
256    /** Index of instructions being sent to rename. */
257    unsigned toRenameIndex;
258
259    /** number of Active Threads*/
260    unsigned numThreads;
261
262    /** List of active thread ids */
263    std::list<unsigned> *activeThreads;
264
265    /** Number of branches in flight. */
266    unsigned branchCount[Impl::MaxThreads];
267
268    /** Maximum size of the skid buffer. */
269    unsigned skidBufferMax;
270
271    /** Stat for total number of idle cycles. */
272    Stats::Scalar<> decodeIdleCycles;
273    /** Stat for total number of blocked cycles. */
274    Stats::Scalar<> decodeBlockedCycles;
275    /** Stat for total number of normal running cycles. */
276    Stats::Scalar<> decodeRunCycles;
277    /** Stat for total number of unblocking cycles. */
278    Stats::Scalar<> decodeUnblockCycles;
279    /** Stat for total number of squashing cycles. */
280    Stats::Scalar<> decodeSquashCycles;
281    /** Stat for number of times a branch is resolved at decode. */
282    Stats::Scalar<> decodeBranchResolved;
283    /** Stat for number of times a branch mispredict is detected. */
284    Stats::Scalar<> decodeBranchMispred;
285    /** Stat for number of times decode detected a non-control instruction
286     * incorrectly predicted as a branch.
287     */
288    Stats::Scalar<> decodeControlMispred;
289    /** Stat for total number of decoded instructions. */
290    Stats::Scalar<> decodeDecodedInsts;
291    /** Stat for total number of squashed instructions. */
292    Stats::Scalar<> decodeSquashedInsts;
293};
294
295#endif // __CPU_O3_DECODE_HH__
296