decode.hh revision 2292
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_DECODE_HH__ 30#define __CPU_O3_DECODE_HH__ 31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36 37/** 38 * DefaultDecode class handles both single threaded and SMT decode. Its width is 39 * specified by the parameters; each cycles it tries to decode that many 40 * instructions. Because instructions are actually decoded when the StaticInst 41 * is created, this stage does not do much other than check any PC-relative 42 * branches. 43 */ 44template<class Impl> 45class DefaultDecode 46{ 47 private: 48 // Typedefs from the Impl. 49 typedef typename Impl::FullCPU FullCPU; 50 typedef typename Impl::DynInstPtr DynInstPtr; 51 typedef typename Impl::Params Params; 52 typedef typename Impl::CPUPol CPUPol; 53 54 // Typedefs from the CPU policy. 55 typedef typename CPUPol::FetchStruct FetchStruct; 56 typedef typename CPUPol::DecodeStruct DecodeStruct; 57 typedef typename CPUPol::TimeStruct TimeStruct; 58 59 public: 60 /** Overall decode stage status. Used to determine if the CPU can 61 * deschedule itself due to a lack of activity. 62 */ 63 enum DecodeStatus { 64 Active, 65 Inactive 66 }; 67 68 /** Individual thread status. */ 69 enum ThreadStatus { 70 Running, 71 Idle, 72 StartSquash, 73 Squashing, 74 Blocked, 75 Unblocking 76 }; 77 78 private: 79 /** Decode status. */ 80 DecodeStatus _status; 81 82 /** Per-thread status. */ 83 ThreadStatus decodeStatus[Impl::MaxThreads]; 84 85 public: 86 /** DefaultDecode constructor. */ 87 DefaultDecode(Params *params); 88 89 /** Returns the name of decode. */ 90 std::string name() const; 91 92 /** Registers statistics. */ 93 void regStats(); 94 95 /** Sets CPU pointer. */ 96 void setCPU(FullCPU *cpu_ptr); 97 98 /** Sets the main backwards communication time buffer pointer. */ 99 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 100 101 /** Sets pointer to time buffer used to communicate to the next stage. */ 102 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 103 104 /** Sets pointer to time buffer coming from fetch. */ 105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 106 107 /** Sets pointer to list of active threads. */ 108 void setActiveThreads(std::list<unsigned> *at_ptr); 109 110 /** Ticks decode, processing all input signals and decoding as many 111 * instructions as possible. 112 */ 113 void tick(); 114 115 /** Determines what to do based on decode's current status. 116 * @param status_change decode() sets this variable if there was a status 117 * change (ie switching from from blocking to unblocking). 118 * @param tid Thread id to decode instructions from. 119 */ 120 void decode(bool &status_change, unsigned tid); 121 122 /** Processes instructions from fetch and passes them on to rename. 123 * Decoding of instructions actually happens when they are created in 124 * fetch, so this function mostly checks if PC-relative branches are 125 * correct. 126 */ 127 void decodeInsts(unsigned tid); 128 129 private: 130 /** Inserts a thread's instructions into the skid buffer, to be decoded 131 * once decode unblocks. 132 */ 133 void skidInsert(unsigned tid); 134 135 /** Returns if all of the skid buffers are empty. */ 136 bool skidsEmpty(); 137 138 /** Updates overall decode status based on all of the threads' statuses. */ 139 void updateStatus(); 140 141 /** Separates instructions from fetch into individual lists of instructions 142 * sorted by thread. 143 */ 144 void sortInsts(); 145 146 /** Reads all stall signals from the backwards communication timebuffer. */ 147 void readStallSignals(unsigned tid); 148 149 /** Checks all input signals and updates decode's status appropriately. */ 150 bool checkSignalsAndUpdate(unsigned tid); 151 152 /** Checks all stall signals, and returns if any are true. */ 153 bool checkStall(unsigned tid) const; 154 155 /** Returns if there any instructions from fetch on this cycle. */ 156 inline bool fetchInstsValid(); 157 158 /** Switches decode to blocking, and signals back that decode has 159 * become blocked. 160 * @return Returns true if there is a status change. 161 */ 162 bool block(unsigned tid); 163 164 /** Switches decode to unblocking if the skid buffer is empty, and 165 * signals back that decode has unblocked. 166 * @return Returns true if there is a status change. 167 */ 168 bool unblock(unsigned tid); 169 170 /** Squashes if there is a PC-relative branch that was predicted 171 * incorrectly. Sends squash information back to fetch. 172 */ 173 void squash(DynInstPtr &inst, unsigned tid); 174 175 public: 176 /** Squashes due to commit signalling a squash. Changes status to 177 * squashing and clears block/unblock signals as needed. 178 */ 179 unsigned squash(unsigned tid); 180 181 private: 182 // Interfaces to objects outside of decode. 183 /** CPU interface. */ 184 FullCPU *cpu; 185 186 /** Time buffer interface. */ 187 TimeBuffer<TimeStruct> *timeBuffer; 188 189 /** Wire to get rename's output from backwards time buffer. */ 190 typename TimeBuffer<TimeStruct>::wire fromRename; 191 192 /** Wire to get iew's information from backwards time buffer. */ 193 typename TimeBuffer<TimeStruct>::wire fromIEW; 194 195 /** Wire to get commit's information from backwards time buffer. */ 196 typename TimeBuffer<TimeStruct>::wire fromCommit; 197 198 /** Wire to write information heading to previous stages. */ 199 // Might not be the best name as not only fetch will read it. 200 typename TimeBuffer<TimeStruct>::wire toFetch; 201 202 /** Decode instruction queue. */ 203 TimeBuffer<DecodeStruct> *decodeQueue; 204 205 /** Wire used to write any information heading to rename. */ 206 typename TimeBuffer<DecodeStruct>::wire toRename; 207 208 /** Fetch instruction queue interface. */ 209 TimeBuffer<FetchStruct> *fetchQueue; 210 211 /** Wire to get fetch's output from fetch queue. */ 212 typename TimeBuffer<FetchStruct>::wire fromFetch; 213 214 /** Queue of all instructions coming from fetch this cycle. */ 215 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 216 217 /** Skid buffer between fetch and decode. */ 218 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 219 220 /** Variable that tracks if decode has written to the time buffer this 221 * cycle. Used to tell CPU if there is activity this cycle. 222 */ 223 bool wroteToTimeBuffer; 224 225 /** Source of possible stalls. */ 226 struct Stalls { 227 bool rename; 228 bool iew; 229 bool commit; 230 }; 231 232 /** Tracks which stages are telling decode to stall. */ 233 Stalls stalls[Impl::MaxThreads]; 234 235 /** Rename to decode delay, in ticks. */ 236 unsigned renameToDecodeDelay; 237 238 /** IEW to decode delay, in ticks. */ 239 unsigned iewToDecodeDelay; 240 241 /** Commit to decode delay, in ticks. */ 242 unsigned commitToDecodeDelay; 243 244 /** Fetch to decode delay, in ticks. */ 245 unsigned fetchToDecodeDelay; 246 247 /** The width of decode, in instructions. */ 248 unsigned decodeWidth; 249 250 /** Index of instructions being sent to rename. */ 251 unsigned toRenameIndex; 252 253 /** number of Active Threads*/ 254 unsigned numThreads; 255 256 /** List of active thread ids */ 257 std::list<unsigned> *activeThreads; 258 259 /** Number of branches in flight. */ 260 unsigned branchCount[Impl::MaxThreads]; 261 262 /** Maximum size of the skid buffer. */ 263 unsigned skidBufferMax; 264 265 /** Stat for total number of idle cycles. */ 266 Stats::Scalar<> decodeIdleCycles; 267 /** Stat for total number of blocked cycles. */ 268 Stats::Scalar<> decodeBlockedCycles; 269 /** Stat for total number of normal running cycles. */ 270 Stats::Scalar<> decodeRunCycles; 271 /** Stat for total number of unblocking cycles. */ 272 Stats::Scalar<> decodeUnblockCycles; 273 /** Stat for total number of squashing cycles. */ 274 Stats::Scalar<> decodeSquashCycles; 275 /** Stat for number of times a branch mispredict is detected. */ 276 Stats::Scalar<> decodeBranchMispred; 277 /** Stat for number of times decode detected a non-control instruction 278 * incorrectly predicted as a branch. 279 */ 280 Stats::Scalar<> decodeControlMispred; 281 /** Stat for total number of decoded instructions. */ 282 Stats::Scalar<> decodeDecodedInsts; 283 /** Stat for total number of squashed instructions. */ 284 Stats::Scalar<> decodeSquashedInsts; 285}; 286 287#endif // __CPU_O3_DECODE_HH__ 288