decode.hh revision 1689 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
30#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
31
32#include <queue>
33
34#include "base/statistics.hh"
35#include "base/timebuf.hh"
36
37template<class Impl>
38class SimpleDecode
39{
40  private:
41    // Typedefs from the Impl.
42    typedef typename Impl::ISA ISA;
43    typedef typename Impl::FullCPU FullCPU;
44    typedef typename Impl::DynInstPtr DynInstPtr;
45    typedef typename Impl::Params Params;
46    typedef typename Impl::CPUPol CPUPol;
47
48    // Typedefs from the CPU policy.
49    typedef typename CPUPol::FetchStruct FetchStruct;
50    typedef typename CPUPol::DecodeStruct DecodeStruct;
51    typedef typename CPUPol::TimeStruct TimeStruct;
52
53    // Typedefs from the ISA.
54    typedef typename ISA::Addr Addr;
55
56  public:
57    // The only time decode will become blocked is if dispatch becomes
58    // blocked, which means IQ or ROB is probably full.
59    enum Status {
60        Running,
61        Idle,
62        Squashing,
63        Blocked,
64        Unblocking
65    };
66
67  private:
68    // May eventually need statuses on a per thread basis.
69    Status _status;
70
71  public:
72    SimpleDecode(Params &params);
73
74    void regStats();
75
76    void setCPU(FullCPU *cpu_ptr);
77
78    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
79
80    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
81
82    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
83
84    void tick();
85
86    void decode();
87
88  private:
89    inline bool fetchInstsValid();
90
91    void block();
92
93    inline void unblock();
94
95    void squash(DynInstPtr &inst);
96
97  public:
98    // Might want to make squash a friend function.
99    void squash();
100
101  private:
102    // Interfaces to objects outside of decode.
103    /** CPU interface. */
104    FullCPU *cpu;
105
106    /** Time buffer interface. */
107    TimeBuffer<TimeStruct> *timeBuffer;
108
109    /** Wire to get rename's output from backwards time buffer. */
110    typename TimeBuffer<TimeStruct>::wire fromRename;
111
112    /** Wire to get iew's information from backwards time buffer. */
113    typename TimeBuffer<TimeStruct>::wire fromIEW;
114
115    /** Wire to get commit's information from backwards time buffer. */
116    typename TimeBuffer<TimeStruct>::wire fromCommit;
117
118    /** Wire to write information heading to previous stages. */
119    // Might not be the best name as not only fetch will read it.
120    typename TimeBuffer<TimeStruct>::wire toFetch;
121
122    /** Decode instruction queue. */
123    TimeBuffer<DecodeStruct> *decodeQueue;
124
125    /** Wire used to write any information heading to rename. */
126    typename TimeBuffer<DecodeStruct>::wire toRename;
127
128    /** Fetch instruction queue interface. */
129    TimeBuffer<FetchStruct> *fetchQueue;
130
131    /** Wire to get fetch's output from fetch queue. */
132    typename TimeBuffer<FetchStruct>::wire fromFetch;
133
134    /** Skid buffer between fetch and decode. */
135    std::queue<FetchStruct> skidBuffer;
136
137    //Consider making these unsigned to avoid any confusion.
138    /** Rename to decode delay, in ticks. */
139    unsigned renameToDecodeDelay;
140
141    /** IEW to decode delay, in ticks. */
142    unsigned iewToDecodeDelay;
143
144    /** Commit to decode delay, in ticks. */
145    unsigned commitToDecodeDelay;
146
147    /** Fetch to decode delay, in ticks. */
148    unsigned fetchToDecodeDelay;
149
150    /** The width of decode, in instructions. */
151    unsigned decodeWidth;
152
153    /** The instruction that decode is currently on.  It needs to have
154     *  persistent state so that when a stall occurs in the middle of a
155     *  group of instructions, it can restart at the proper instruction.
156     */
157    unsigned numInst;
158
159    Stats::Scalar<> decodeIdleCycles;
160    Stats::Scalar<> decodeBlockedCycles;
161    Stats::Scalar<> decodeUnblockCycles;
162    Stats::Scalar<> decodeSquashCycles;
163    Stats::Scalar<> decodeBranchMispred;
164    Stats::Scalar<> decodeControlMispred;
165    Stats::Scalar<> decodeDecodedInsts;
166    Stats::Scalar<> decodeSquashedInsts;
167};
168
169#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
170