decode.hh revision 1681 
1// Todo:
2// Add a couple of the branch fields to DynInst.  Figure out where DynInst
3// should try to compute the target of a PC-relative branch.  Try to avoid
4// having so many returns within the code.
5// Fix up squashing too, as it's too
6// dependent upon the iew stage continually telling it to squash.
7
8#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
9#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
10
11#include <queue>
12
13#include "base/statistics.hh"
14#include "base/timebuf.hh"
15
16template<class Impl>
17class SimpleDecode
18{
19  private:
20    // Typedefs from the Impl.
21    typedef typename Impl::ISA ISA;
22    typedef typename Impl::FullCPU FullCPU;
23    typedef typename Impl::DynInstPtr DynInstPtr;
24    typedef typename Impl::Params Params;
25    typedef typename Impl::CPUPol CPUPol;
26
27    // Typedefs from the CPU policy.
28    typedef typename CPUPol::FetchStruct FetchStruct;
29    typedef typename CPUPol::DecodeStruct DecodeStruct;
30    typedef typename CPUPol::TimeStruct TimeStruct;
31
32    // Typedefs from the ISA.
33    typedef typename ISA::Addr Addr;
34
35  public:
36    // The only time decode will become blocked is if dispatch becomes
37    // blocked, which means IQ or ROB is probably full.
38    enum Status {
39        Running,
40        Idle,
41        Squashing,
42        Blocked,
43        Unblocking
44    };
45
46  private:
47    // May eventually need statuses on a per thread basis.
48    Status _status;
49
50  public:
51    SimpleDecode(Params &params);
52
53    void regStats();
54
55    void setCPU(FullCPU *cpu_ptr);
56
57    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
58
59    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
60
61    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
62
63    void tick();
64
65    void decode();
66
67    // Might want to make squash a friend function.
68    void squash();
69
70  private:
71    inline bool fetchInstsValid();
72
73    void block();
74
75    inline void unblock();
76
77    void squash(DynInstPtr &inst);
78
79    void dumpFetchQueue();
80
81    // Interfaces to objects outside of decode.
82    /** CPU interface. */
83    FullCPU *cpu;
84
85    /** Time buffer interface. */
86    TimeBuffer<TimeStruct> *timeBuffer;
87
88    /** Wire to get rename's output from backwards time buffer. */
89    typename TimeBuffer<TimeStruct>::wire fromRename;
90
91    /** Wire to get iew's information from backwards time buffer. */
92    typename TimeBuffer<TimeStruct>::wire fromIEW;
93
94    /** Wire to get commit's information from backwards time buffer. */
95    typename TimeBuffer<TimeStruct>::wire fromCommit;
96
97    /** Wire to write information heading to previous stages. */
98    // Might not be the best name as not only fetch will read it.
99    typename TimeBuffer<TimeStruct>::wire toFetch;
100
101    /** Decode instruction queue. */
102    TimeBuffer<DecodeStruct> *decodeQueue;
103
104    /** Wire used to write any information heading to rename. */
105    typename TimeBuffer<DecodeStruct>::wire toRename;
106
107    /** Fetch instruction queue interface. */
108    TimeBuffer<FetchStruct> *fetchQueue;
109
110    /** Wire to get fetch's output from fetch queue. */
111    typename TimeBuffer<FetchStruct>::wire fromFetch;
112
113    /** Skid buffer between fetch and decode. */
114    std::queue<FetchStruct> skidBuffer;
115
116  private:
117    //Consider making these unsigned to avoid any confusion.
118    /** Rename to decode delay, in ticks. */
119    unsigned renameToDecodeDelay;
120
121    /** IEW to decode delay, in ticks. */
122    unsigned iewToDecodeDelay;
123
124    /** Commit to decode delay, in ticks. */
125    unsigned commitToDecodeDelay;
126
127    /** Fetch to decode delay, in ticks. */
128    unsigned fetchToDecodeDelay;
129
130    /** The width of decode, in instructions. */
131    unsigned decodeWidth;
132
133    /** The instruction that decode is currently on.  It needs to have
134     *  persistent state so that when a stall occurs in the middle of a
135     *  group of instructions, it can restart at the proper instruction.
136     */
137    unsigned numInst;
138
139    Stats::Scalar<> decodeIdleCycles;
140    Stats::Scalar<> decodeBlockedCycles;
141    Stats::Scalar<> decodeUnblockCycles;
142    Stats::Scalar<> decodeSquashCycles;
143    Stats::Scalar<> decodeBranchMispred;
144    Stats::Scalar<> decodeControlMispred;
145    Stats::Scalar<> decodeDecodedInsts;
146    Stats::Scalar<> decodeSquashedInsts;
147};
148
149#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
150