cpu.hh revision 9608:e2b6b86fda03
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#ifndef __CPU_O3_CPU_HH__ 47#define __CPU_O3_CPU_HH__ 48 49#include <iostream> 50#include <list> 51#include <queue> 52#include <set> 53#include <vector> 54 55#include "arch/types.hh" 56#include "base/statistics.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/o3/cpu_policy.hh" 60#include "cpu/o3/scoreboard.hh" 61#include "cpu/o3/thread_state.hh" 62#include "cpu/activity.hh" 63#include "cpu/base.hh" 64#include "cpu/simple_thread.hh" 65#include "cpu/timebuf.hh" 66//#include "cpu/o3/thread_context.hh" 67#include "params/DerivO3CPU.hh" 68#include "sim/process.hh" 69 70template <class> 71class Checker; 72class ThreadContext; 73template <class> 74class O3ThreadContext; 75 76class Checkpoint; 77class MemObject; 78class Process; 79 80struct BaseCPUParams; 81 82class BaseO3CPU : public BaseCPU 83{ 84 //Stuff that's pretty ISA independent will go here. 85 public: 86 BaseO3CPU(BaseCPUParams *params); 87 88 void regStats(); 89}; 90 91/** 92 * FullO3CPU class, has each of the stages (fetch through commit) 93 * within it, as well as all of the time buffers between stages. The 94 * tick() function for the CPU is defined here. 95 */ 96template <class Impl> 97class FullO3CPU : public BaseO3CPU 98{ 99 public: 100 // Typedefs from the Impl here. 101 typedef typename Impl::CPUPol CPUPolicy; 102 typedef typename Impl::DynInstPtr DynInstPtr; 103 typedef typename Impl::O3CPU O3CPU; 104 105 typedef O3ThreadState<Impl> ImplState; 106 typedef O3ThreadState<Impl> Thread; 107 108 typedef typename std::list<DynInstPtr>::iterator ListIt; 109 110 friend class O3ThreadContext<Impl>; 111 112 public: 113 enum Status { 114 Running, 115 Idle, 116 Halted, 117 Blocked, 118 SwitchedOut 119 }; 120 121 TheISA::TLB * itb; 122 TheISA::TLB * dtb; 123 124 /** Overall CPU status. */ 125 Status _status; 126 127 private: 128 129 /** 130 * IcachePort class for instruction fetch. 131 */ 132 class IcachePort : public MasterPort 133 { 134 protected: 135 /** Pointer to fetch. */ 136 DefaultFetch<Impl> *fetch; 137 138 public: 139 /** Default constructor. */ 140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 141 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 142 { } 143 144 protected: 145 146 /** Timing version of receive. Handles setting fetch to the 147 * proper status to start fetching. */ 148 virtual bool recvTimingResp(PacketPtr pkt); 149 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 150 151 /** Handles doing a retry of a failed fetch. */ 152 virtual void recvRetry(); 153 }; 154 155 /** 156 * DcachePort class for the load/store queue. 157 */ 158 class DcachePort : public MasterPort 159 { 160 protected: 161 162 /** Pointer to LSQ. */ 163 LSQ<Impl> *lsq; 164 165 public: 166 /** Default constructor. */ 167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 168 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 169 { } 170 171 protected: 172 173 /** Timing version of receive. Handles writing back and 174 * completing the load or store that has returned from 175 * memory. */ 176 virtual bool recvTimingResp(PacketPtr pkt); 177 virtual void recvTimingSnoopReq(PacketPtr pkt); 178 179 virtual void recvFunctionalSnoop(PacketPtr pkt) 180 { 181 // @todo: Is there a need for potential invalidation here? 182 } 183 184 /** Handles doing a retry of the previous send. */ 185 virtual void recvRetry(); 186 187 /** 188 * As this CPU requires snooping to maintain the load store queue 189 * change the behaviour from the base CPU port. 190 * 191 * @return true since we have to snoop 192 */ 193 virtual bool isSnooping() const { return true; } 194 }; 195 196 class TickEvent : public Event 197 { 198 private: 199 /** Pointer to the CPU. */ 200 FullO3CPU<Impl> *cpu; 201 202 public: 203 /** Constructs a tick event. */ 204 TickEvent(FullO3CPU<Impl> *c); 205 206 /** Processes a tick event, calling tick() on the CPU. */ 207 void process(); 208 /** Returns the description of the tick event. */ 209 const char *description() const; 210 }; 211 212 /** The tick event used for scheduling CPU ticks. */ 213 TickEvent tickEvent; 214 215 /** Schedule tick event, regardless of its current state. */ 216 void scheduleTickEvent(Cycles delay) 217 { 218 if (tickEvent.squashed()) 219 reschedule(tickEvent, clockEdge(delay)); 220 else if (!tickEvent.scheduled()) 221 schedule(tickEvent, clockEdge(delay)); 222 } 223 224 /** Unschedule tick event, regardless of its current state. */ 225 void unscheduleTickEvent() 226 { 227 if (tickEvent.scheduled()) 228 tickEvent.squash(); 229 } 230 231 class ActivateThreadEvent : public Event 232 { 233 private: 234 /** Number of Thread to Activate */ 235 ThreadID tid; 236 237 /** Pointer to the CPU. */ 238 FullO3CPU<Impl> *cpu; 239 240 public: 241 /** Constructs the event. */ 242 ActivateThreadEvent(); 243 244 /** Initialize Event */ 245 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 246 247 /** Processes the event, calling activateThread() on the CPU. */ 248 void process(); 249 250 /** Returns the description of the event. */ 251 const char *description() const; 252 }; 253 254 /** Schedule thread to activate , regardless of its current state. */ 255 void 256 scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 257 { 258 // Schedule thread to activate, regardless of its current state. 259 if (activateThreadEvent[tid].squashed()) 260 reschedule(activateThreadEvent[tid], 261 clockEdge(delay)); 262 else if (!activateThreadEvent[tid].scheduled()) { 263 Tick when = clockEdge(delay); 264 265 // Check if the deallocateEvent is also scheduled, and make 266 // sure they do not happen at same time causing a sleep that 267 // is never woken from. 268 if (deallocateContextEvent[tid].scheduled() && 269 deallocateContextEvent[tid].when() == when) { 270 when++; 271 } 272 273 schedule(activateThreadEvent[tid], when); 274 } 275 } 276 277 /** Unschedule actiavte thread event, regardless of its current state. */ 278 void 279 unscheduleActivateThreadEvent(ThreadID tid) 280 { 281 if (activateThreadEvent[tid].scheduled()) 282 activateThreadEvent[tid].squash(); 283 } 284 285 /** The tick event used for scheduling CPU ticks. */ 286 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 287 288 class DeallocateContextEvent : public Event 289 { 290 private: 291 /** Number of Thread to deactivate */ 292 ThreadID tid; 293 294 /** Should the thread be removed from the CPU? */ 295 bool remove; 296 297 /** Pointer to the CPU. */ 298 FullO3CPU<Impl> *cpu; 299 300 public: 301 /** Constructs the event. */ 302 DeallocateContextEvent(); 303 304 /** Initialize Event */ 305 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 306 307 /** Processes the event, calling activateThread() on the CPU. */ 308 void process(); 309 310 /** Sets whether the thread should also be removed from the CPU. */ 311 void setRemove(bool _remove) { remove = _remove; } 312 313 /** Returns the description of the event. */ 314 const char *description() const; 315 }; 316 317 /** Schedule cpu to deallocate thread context.*/ 318 void 319 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 320 { 321 // Schedule thread to activate, regardless of its current state. 322 if (deallocateContextEvent[tid].squashed()) 323 reschedule(deallocateContextEvent[tid], 324 clockEdge(delay)); 325 else if (!deallocateContextEvent[tid].scheduled()) 326 schedule(deallocateContextEvent[tid], 327 clockEdge(delay)); 328 } 329 330 /** Unschedule thread deallocation in CPU */ 331 void 332 unscheduleDeallocateContextEvent(ThreadID tid) 333 { 334 if (deallocateContextEvent[tid].scheduled()) 335 deallocateContextEvent[tid].squash(); 336 } 337 338 /** The tick event used for scheduling CPU ticks. */ 339 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 340 341 /** 342 * Check if the pipeline has drained and signal the DrainManager. 343 * 344 * This method checks if a drain has been requested and if the CPU 345 * has drained successfully (i.e., there are no instructions in 346 * the pipeline). If the CPU has drained, it deschedules the tick 347 * event and signals the drain manager. 348 * 349 * @return False if a drain hasn't been requested or the CPU 350 * hasn't drained, true otherwise. 351 */ 352 bool tryDrain(); 353 354 /** 355 * Perform sanity checks after a drain. 356 * 357 * This method is called from drain() when it has determined that 358 * the CPU is fully drained when gem5 is compiled with the NDEBUG 359 * macro undefined. The intention of this method is to do more 360 * extensive tests than the isDrained() method to weed out any 361 * draining bugs. 362 */ 363 void drainSanityCheck() const; 364 365 /** Check if a system is in a drained state. */ 366 bool isDrained() const; 367 368 public: 369 /** Constructs a CPU with the given parameters. */ 370 FullO3CPU(DerivO3CPUParams *params); 371 /** Destructor. */ 372 ~FullO3CPU(); 373 374 /** Registers statistics. */ 375 void regStats(); 376 377 void demapPage(Addr vaddr, uint64_t asn) 378 { 379 this->itb->demapPage(vaddr, asn); 380 this->dtb->demapPage(vaddr, asn); 381 } 382 383 void demapInstPage(Addr vaddr, uint64_t asn) 384 { 385 this->itb->demapPage(vaddr, asn); 386 } 387 388 void demapDataPage(Addr vaddr, uint64_t asn) 389 { 390 this->dtb->demapPage(vaddr, asn); 391 } 392 393 /** Ticks CPU, calling tick() on each stage, and checking the overall 394 * activity to see if the CPU should deschedule itself. 395 */ 396 void tick(); 397 398 /** Initialize the CPU */ 399 void init(); 400 401 void startup(); 402 403 /** Returns the Number of Active Threads in the CPU */ 404 int numActiveThreads() 405 { return activeThreads.size(); } 406 407 /** Add Thread to Active Threads List */ 408 void activateThread(ThreadID tid); 409 410 /** Remove Thread from Active Threads List */ 411 void deactivateThread(ThreadID tid); 412 413 /** Setup CPU to insert a thread's context */ 414 void insertThread(ThreadID tid); 415 416 /** Remove all of a thread's context from CPU */ 417 void removeThread(ThreadID tid); 418 419 /** Count the Total Instructions Committed in the CPU. */ 420 virtual Counter totalInsts() const; 421 422 /** Count the Total Ops (including micro ops) committed in the CPU. */ 423 virtual Counter totalOps() const; 424 425 /** Add Thread to Active Threads List. */ 426 void activateContext(ThreadID tid, Cycles delay); 427 428 /** Remove Thread from Active Threads List */ 429 void suspendContext(ThreadID tid); 430 431 /** Remove Thread from Active Threads List && 432 * Possibly Remove Thread Context from CPU. 433 */ 434 bool scheduleDeallocateContext(ThreadID tid, bool remove, 435 Cycles delay = Cycles(1)); 436 437 /** Remove Thread from Active Threads List && 438 * Remove Thread Context from CPU. 439 */ 440 void haltContext(ThreadID tid); 441 442 /** Activate a Thread When CPU Resources are Available. */ 443 void activateWhenReady(ThreadID tid); 444 445 /** Add or Remove a Thread Context in the CPU. */ 446 void doContextSwitch(); 447 448 /** Update The Order In Which We Process Threads. */ 449 void updateThreadPriority(); 450 451 /** Is the CPU draining? */ 452 bool isDraining() const { return getDrainState() == Drainable::Draining; } 453 454 void serializeThread(std::ostream &os, ThreadID tid); 455 456 void unserializeThread(Checkpoint *cp, const std::string §ion, 457 ThreadID tid); 458 459 public: 460 /** Executes a syscall. 461 * @todo: Determine if this needs to be virtual. 462 */ 463 void syscall(int64_t callnum, ThreadID tid); 464 465 /** Starts draining the CPU's pipeline of all instructions in 466 * order to stop all memory accesses. */ 467 unsigned int drain(DrainManager *drain_manager); 468 469 /** Resumes execution after a drain. */ 470 void drainResume(); 471 472 /** 473 * Commit has reached a safe point to drain a thread. 474 * 475 * Commit calls this method to inform the pipeline that it has 476 * reached a point where it is not executed microcode and is about 477 * to squash uncommitted instructions to fully drain the pipeline. 478 */ 479 void commitDrained(ThreadID tid); 480 481 /** Switches out this CPU. */ 482 virtual void switchOut(); 483 484 /** Takes over from another CPU. */ 485 virtual void takeOverFrom(BaseCPU *oldCPU); 486 487 void verifyMemoryMode() const; 488 489 /** Get the current instruction sequence number, and increment it. */ 490 InstSeqNum getAndIncrementInstSeq() 491 { return globalSeqNum++; } 492 493 /** Traps to handle given fault. */ 494 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 495 496 /** HW return from error interrupt. */ 497 Fault hwrei(ThreadID tid); 498 499 bool simPalCheck(int palFunc, ThreadID tid); 500 501 /** Returns the Fault for any valid interrupt. */ 502 Fault getInterrupts(); 503 504 /** Processes any an interrupt fault. */ 505 void processInterrupts(Fault interrupt); 506 507 /** Halts the CPU. */ 508 void halt() { panic("Halt not implemented!\n"); } 509 510 /** Check if this address is a valid instruction address. */ 511 bool validInstAddr(Addr addr) { return true; } 512 513 /** Check if this address is a valid data address. */ 514 bool validDataAddr(Addr addr) { return true; } 515 516 /** Register accessors. Index refers to the physical register index. */ 517 518 /** Reads a miscellaneous register. */ 519 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 520 521 /** Reads a misc. register, including any side effects the read 522 * might have as defined by the architecture. 523 */ 524 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 525 526 /** Sets a miscellaneous register. */ 527 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 528 ThreadID tid); 529 530 /** Sets a misc. register, including any side effects the write 531 * might have as defined by the architecture. 532 */ 533 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 534 ThreadID tid); 535 536 uint64_t readIntReg(int reg_idx); 537 538 TheISA::FloatReg readFloatReg(int reg_idx); 539 540 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 541 542 void setIntReg(int reg_idx, uint64_t val); 543 544 void setFloatReg(int reg_idx, TheISA::FloatReg val); 545 546 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 547 548 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 549 550 float readArchFloatReg(int reg_idx, ThreadID tid); 551 552 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 553 554 /** Architectural register accessors. Looks up in the commit 555 * rename table to obtain the true physical index of the 556 * architected register first, then accesses that physical 557 * register. 558 */ 559 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 560 561 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 562 563 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 564 565 /** Sets the commit PC state of a specific thread. */ 566 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 567 568 /** Reads the commit PC state of a specific thread. */ 569 TheISA::PCState pcState(ThreadID tid); 570 571 /** Reads the commit PC of a specific thread. */ 572 Addr instAddr(ThreadID tid); 573 574 /** Reads the commit micro PC of a specific thread. */ 575 MicroPC microPC(ThreadID tid); 576 577 /** Reads the next PC of a specific thread. */ 578 Addr nextInstAddr(ThreadID tid); 579 580 /** Initiates a squash of all in-flight instructions for a given 581 * thread. The source of the squash is an external update of 582 * state through the TC. 583 */ 584 void squashFromTC(ThreadID tid); 585 586 /** Function to add instruction onto the head of the list of the 587 * instructions. Used when new instructions are fetched. 588 */ 589 ListIt addInst(DynInstPtr &inst); 590 591 /** Function to tell the CPU that an instruction has completed. */ 592 void instDone(ThreadID tid, DynInstPtr &inst); 593 594 /** Remove an instruction from the front end of the list. There's 595 * no restriction on location of the instruction. 596 */ 597 void removeFrontInst(DynInstPtr &inst); 598 599 /** Remove all instructions that are not currently in the ROB. 600 * There's also an option to not squash delay slot instructions.*/ 601 void removeInstsNotInROB(ThreadID tid); 602 603 /** Remove all instructions younger than the given sequence number. */ 604 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 605 606 /** Removes the instruction pointed to by the iterator. */ 607 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 608 609 /** Cleans up all instructions on the remove list. */ 610 void cleanUpRemovedInsts(); 611 612 /** Debug function to print all instructions on the list. */ 613 void dumpInsts(); 614 615 public: 616#ifndef NDEBUG 617 /** Count of total number of dynamic instructions in flight. */ 618 int instcount; 619#endif 620 621 /** List of all the instructions in flight. */ 622 std::list<DynInstPtr> instList; 623 624 /** List of all the instructions that will be removed at the end of this 625 * cycle. 626 */ 627 std::queue<ListIt> removeList; 628 629#ifdef DEBUG 630 /** Debug structure to keep track of the sequence numbers still in 631 * flight. 632 */ 633 std::set<InstSeqNum> snList; 634#endif 635 636 /** Records if instructions need to be removed this cycle due to 637 * being retired or squashed. 638 */ 639 bool removeInstsThisCycle; 640 641 protected: 642 /** The fetch stage. */ 643 typename CPUPolicy::Fetch fetch; 644 645 /** The decode stage. */ 646 typename CPUPolicy::Decode decode; 647 648 /** The dispatch stage. */ 649 typename CPUPolicy::Rename rename; 650 651 /** The issue/execute/writeback stages. */ 652 typename CPUPolicy::IEW iew; 653 654 /** The commit stage. */ 655 typename CPUPolicy::Commit commit; 656 657 /** The register file. */ 658 typename CPUPolicy::RegFile regFile; 659 660 /** The free list. */ 661 typename CPUPolicy::FreeList freeList; 662 663 /** The rename map. */ 664 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 665 666 /** The commit rename map. */ 667 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 668 669 /** The re-order buffer. */ 670 typename CPUPolicy::ROB rob; 671 672 /** Active Threads List */ 673 std::list<ThreadID> activeThreads; 674 675 /** Integer Register Scoreboard */ 676 Scoreboard scoreboard; 677 678 std::vector<TheISA::ISA *> isa; 679 680 /** Instruction port. Note that it has to appear after the fetch stage. */ 681 IcachePort icachePort; 682 683 /** Data port. Note that it has to appear after the iew stages */ 684 DcachePort dcachePort; 685 686 public: 687 /** Enum to give each stage a specific index, so when calling 688 * activateStage() or deactivateStage(), they can specify which stage 689 * is being activated/deactivated. 690 */ 691 enum StageIdx { 692 FetchIdx, 693 DecodeIdx, 694 RenameIdx, 695 IEWIdx, 696 CommitIdx, 697 NumStages }; 698 699 /** Typedefs from the Impl to get the structs that each of the 700 * time buffers should use. 701 */ 702 typedef typename CPUPolicy::TimeStruct TimeStruct; 703 704 typedef typename CPUPolicy::FetchStruct FetchStruct; 705 706 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 707 708 typedef typename CPUPolicy::RenameStruct RenameStruct; 709 710 typedef typename CPUPolicy::IEWStruct IEWStruct; 711 712 /** The main time buffer to do backwards communication. */ 713 TimeBuffer<TimeStruct> timeBuffer; 714 715 /** The fetch stage's instruction queue. */ 716 TimeBuffer<FetchStruct> fetchQueue; 717 718 /** The decode stage's instruction queue. */ 719 TimeBuffer<DecodeStruct> decodeQueue; 720 721 /** The rename stage's instruction queue. */ 722 TimeBuffer<RenameStruct> renameQueue; 723 724 /** The IEW stage's instruction queue. */ 725 TimeBuffer<IEWStruct> iewQueue; 726 727 private: 728 /** The activity recorder; used to tell if the CPU has any 729 * activity remaining or if it can go to idle and deschedule 730 * itself. 731 */ 732 ActivityRecorder activityRec; 733 734 public: 735 /** Records that there was time buffer activity this cycle. */ 736 void activityThisCycle() { activityRec.activity(); } 737 738 /** Changes a stage's status to active within the activity recorder. */ 739 void activateStage(const StageIdx idx) 740 { activityRec.activateStage(idx); } 741 742 /** Changes a stage's status to inactive within the activity recorder. */ 743 void deactivateStage(const StageIdx idx) 744 { activityRec.deactivateStage(idx); } 745 746 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 747 void wakeCPU(); 748 749 virtual void wakeup(); 750 751 /** Gets a free thread id. Use if thread ids change across system. */ 752 ThreadID getFreeTid(); 753 754 public: 755 /** Returns a pointer to a thread context. */ 756 ThreadContext * 757 tcBase(ThreadID tid) 758 { 759 return thread[tid]->getTC(); 760 } 761 762 /** The global sequence number counter. */ 763 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 764 765 /** Pointer to the checker, which can dynamically verify 766 * instruction results at run time. This can be set to NULL if it 767 * is not being used. 768 */ 769 Checker<Impl> *checker; 770 771 /** Pointer to the system. */ 772 System *system; 773 774 /** DrainManager to notify when draining has completed. */ 775 DrainManager *drainManager; 776 777 /** Pointers to all of the threads in the CPU. */ 778 std::vector<Thread *> thread; 779 780 /** Is there a context switch pending? */ 781 bool contextSwitch; 782 783 /** Threads Scheduled to Enter CPU */ 784 std::list<int> cpuWaitList; 785 786 /** The cycle that the CPU was last running, used for statistics. */ 787 Cycles lastRunningCycle; 788 789 /** The cycle that the CPU was last activated by a new thread*/ 790 Tick lastActivatedCycle; 791 792 /** Mapping for system thread id to cpu id */ 793 std::map<ThreadID, unsigned> threadMap; 794 795 /** Available thread ids in the cpu*/ 796 std::vector<ThreadID> tids; 797 798 /** CPU read function, forwards read to LSQ. */ 799 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 800 uint8_t *data, int load_idx) 801 { 802 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 803 data, load_idx); 804 } 805 806 /** CPU write function, forwards write to LSQ. */ 807 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 808 uint8_t *data, int store_idx) 809 { 810 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 811 data, store_idx); 812 } 813 814 /** Used by the fetch unit to get a hold of the instruction port. */ 815 virtual MasterPort &getInstPort() { return icachePort; } 816 817 /** Get the dcache port (used to find block size for translations). */ 818 virtual MasterPort &getDataPort() { return dcachePort; } 819 820 /** Stat for total number of times the CPU is descheduled. */ 821 Stats::Scalar timesIdled; 822 /** Stat for total number of cycles the CPU spends descheduled. */ 823 Stats::Scalar idleCycles; 824 /** Stat for total number of cycles the CPU spends descheduled due to a 825 * quiesce operation or waiting for an interrupt. */ 826 Stats::Scalar quiesceCycles; 827 /** Stat for the number of committed instructions per thread. */ 828 Stats::Vector committedInsts; 829 /** Stat for the number of committed ops (including micro ops) per thread. */ 830 Stats::Vector committedOps; 831 /** Stat for the total number of committed instructions. */ 832 Stats::Scalar totalCommittedInsts; 833 /** Stat for the CPI per thread. */ 834 Stats::Formula cpi; 835 /** Stat for the total CPI. */ 836 Stats::Formula totalCpi; 837 /** Stat for the IPC per thread. */ 838 Stats::Formula ipc; 839 /** Stat for the total IPC. */ 840 Stats::Formula totalIpc; 841 842 //number of integer register file accesses 843 Stats::Scalar intRegfileReads; 844 Stats::Scalar intRegfileWrites; 845 //number of float register file accesses 846 Stats::Scalar fpRegfileReads; 847 Stats::Scalar fpRegfileWrites; 848 //number of misc 849 Stats::Scalar miscRegfileReads; 850 Stats::Scalar miscRegfileWrites; 851}; 852 853#endif // __CPU_O3_CPU_HH__ 854