cpu.hh revision 9523:b8c8437f71d9
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#ifndef __CPU_O3_CPU_HH__ 47#define __CPU_O3_CPU_HH__ 48 49#include <iostream> 50#include <list> 51#include <queue> 52#include <set> 53#include <vector> 54 55#include "arch/types.hh" 56#include "base/statistics.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/o3/cpu_policy.hh" 60#include "cpu/o3/scoreboard.hh" 61#include "cpu/o3/thread_state.hh" 62#include "cpu/activity.hh" 63#include "cpu/base.hh" 64#include "cpu/simple_thread.hh" 65#include "cpu/timebuf.hh" 66//#include "cpu/o3/thread_context.hh" 67#include "params/DerivO3CPU.hh" 68#include "sim/process.hh" 69 70template <class> 71class Checker; 72class ThreadContext; 73template <class> 74class O3ThreadContext; 75 76class Checkpoint; 77class MemObject; 78class Process; 79 80struct BaseCPUParams; 81 82class BaseO3CPU : public BaseCPU 83{ 84 //Stuff that's pretty ISA independent will go here. 85 public: 86 BaseO3CPU(BaseCPUParams *params); 87 88 void regStats(); 89}; 90 91/** 92 * FullO3CPU class, has each of the stages (fetch through commit) 93 * within it, as well as all of the time buffers between stages. The 94 * tick() function for the CPU is defined here. 95 */ 96template <class Impl> 97class FullO3CPU : public BaseO3CPU 98{ 99 public: 100 // Typedefs from the Impl here. 101 typedef typename Impl::CPUPol CPUPolicy; 102 typedef typename Impl::DynInstPtr DynInstPtr; 103 typedef typename Impl::O3CPU O3CPU; 104 105 typedef O3ThreadState<Impl> ImplState; 106 typedef O3ThreadState<Impl> Thread; 107 108 typedef typename std::list<DynInstPtr>::iterator ListIt; 109 110 friend class O3ThreadContext<Impl>; 111 112 public: 113 enum Status { 114 Running, 115 Idle, 116 Halted, 117 Blocked, 118 SwitchedOut 119 }; 120 121 TheISA::TLB * itb; 122 TheISA::TLB * dtb; 123 124 /** Overall CPU status. */ 125 Status _status; 126 127 private: 128 129 /** 130 * IcachePort class for instruction fetch. 131 */ 132 class IcachePort : public CpuPort 133 { 134 protected: 135 /** Pointer to fetch. */ 136 DefaultFetch<Impl> *fetch; 137 138 public: 139 /** Default constructor. */ 140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 141 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 142 { } 143 144 protected: 145 146 /** Timing version of receive. Handles setting fetch to the 147 * proper status to start fetching. */ 148 virtual bool recvTimingResp(PacketPtr pkt); 149 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 150 151 /** Handles doing a retry of a failed fetch. */ 152 virtual void recvRetry(); 153 }; 154 155 /** 156 * DcachePort class for the load/store queue. 157 */ 158 class DcachePort : public CpuPort 159 { 160 protected: 161 162 /** Pointer to LSQ. */ 163 LSQ<Impl> *lsq; 164 165 public: 166 /** Default constructor. */ 167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 168 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 169 { } 170 171 protected: 172 173 /** Timing version of receive. Handles writing back and 174 * completing the load or store that has returned from 175 * memory. */ 176 virtual bool recvTimingResp(PacketPtr pkt); 177 virtual void recvTimingSnoopReq(PacketPtr pkt); 178 179 /** Handles doing a retry of the previous send. */ 180 virtual void recvRetry(); 181 182 /** 183 * As this CPU requires snooping to maintain the load store queue 184 * change the behaviour from the base CPU port. 185 * 186 * @return true since we have to snoop 187 */ 188 virtual bool isSnooping() const { return true; } 189 }; 190 191 class TickEvent : public Event 192 { 193 private: 194 /** Pointer to the CPU. */ 195 FullO3CPU<Impl> *cpu; 196 197 public: 198 /** Constructs a tick event. */ 199 TickEvent(FullO3CPU<Impl> *c); 200 201 /** Processes a tick event, calling tick() on the CPU. */ 202 void process(); 203 /** Returns the description of the tick event. */ 204 const char *description() const; 205 }; 206 207 /** The tick event used for scheduling CPU ticks. */ 208 TickEvent tickEvent; 209 210 /** Schedule tick event, regardless of its current state. */ 211 void scheduleTickEvent(Cycles delay) 212 { 213 if (tickEvent.squashed()) 214 reschedule(tickEvent, clockEdge(delay)); 215 else if (!tickEvent.scheduled()) 216 schedule(tickEvent, clockEdge(delay)); 217 } 218 219 /** Unschedule tick event, regardless of its current state. */ 220 void unscheduleTickEvent() 221 { 222 if (tickEvent.scheduled()) 223 tickEvent.squash(); 224 } 225 226 class ActivateThreadEvent : public Event 227 { 228 private: 229 /** Number of Thread to Activate */ 230 ThreadID tid; 231 232 /** Pointer to the CPU. */ 233 FullO3CPU<Impl> *cpu; 234 235 public: 236 /** Constructs the event. */ 237 ActivateThreadEvent(); 238 239 /** Initialize Event */ 240 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 241 242 /** Processes the event, calling activateThread() on the CPU. */ 243 void process(); 244 245 /** Returns the description of the event. */ 246 const char *description() const; 247 }; 248 249 /** Schedule thread to activate , regardless of its current state. */ 250 void 251 scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 252 { 253 // Schedule thread to activate, regardless of its current state. 254 if (activateThreadEvent[tid].squashed()) 255 reschedule(activateThreadEvent[tid], 256 clockEdge(delay)); 257 else if (!activateThreadEvent[tid].scheduled()) { 258 Tick when = clockEdge(delay); 259 260 // Check if the deallocateEvent is also scheduled, and make 261 // sure they do not happen at same time causing a sleep that 262 // is never woken from. 263 if (deallocateContextEvent[tid].scheduled() && 264 deallocateContextEvent[tid].when() == when) { 265 when++; 266 } 267 268 schedule(activateThreadEvent[tid], when); 269 } 270 } 271 272 /** Unschedule actiavte thread event, regardless of its current state. */ 273 void 274 unscheduleActivateThreadEvent(ThreadID tid) 275 { 276 if (activateThreadEvent[tid].scheduled()) 277 activateThreadEvent[tid].squash(); 278 } 279 280 /** The tick event used for scheduling CPU ticks. */ 281 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 282 283 class DeallocateContextEvent : public Event 284 { 285 private: 286 /** Number of Thread to deactivate */ 287 ThreadID tid; 288 289 /** Should the thread be removed from the CPU? */ 290 bool remove; 291 292 /** Pointer to the CPU. */ 293 FullO3CPU<Impl> *cpu; 294 295 public: 296 /** Constructs the event. */ 297 DeallocateContextEvent(); 298 299 /** Initialize Event */ 300 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 301 302 /** Processes the event, calling activateThread() on the CPU. */ 303 void process(); 304 305 /** Sets whether the thread should also be removed from the CPU. */ 306 void setRemove(bool _remove) { remove = _remove; } 307 308 /** Returns the description of the event. */ 309 const char *description() const; 310 }; 311 312 /** Schedule cpu to deallocate thread context.*/ 313 void 314 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 315 { 316 // Schedule thread to activate, regardless of its current state. 317 if (deallocateContextEvent[tid].squashed()) 318 reschedule(deallocateContextEvent[tid], 319 clockEdge(delay)); 320 else if (!deallocateContextEvent[tid].scheduled()) 321 schedule(deallocateContextEvent[tid], 322 clockEdge(delay)); 323 } 324 325 /** Unschedule thread deallocation in CPU */ 326 void 327 unscheduleDeallocateContextEvent(ThreadID tid) 328 { 329 if (deallocateContextEvent[tid].scheduled()) 330 deallocateContextEvent[tid].squash(); 331 } 332 333 /** The tick event used for scheduling CPU ticks. */ 334 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 335 336 /** 337 * Check if the pipeline has drained and signal the DrainManager. 338 * 339 * This method checks if a drain has been requested and if the CPU 340 * has drained successfully (i.e., there are no instructions in 341 * the pipeline). If the CPU has drained, it deschedules the tick 342 * event and signals the drain manager. 343 * 344 * @return False if a drain hasn't been requested or the CPU 345 * hasn't drained, true otherwise. 346 */ 347 bool tryDrain(); 348 349 /** 350 * Perform sanity checks after a drain. 351 * 352 * This method is called from drain() when it has determined that 353 * the CPU is fully drained when gem5 is compiled with the NDEBUG 354 * macro undefined. The intention of this method is to do more 355 * extensive tests than the isDrained() method to weed out any 356 * draining bugs. 357 */ 358 void drainSanityCheck() const; 359 360 /** Check if a system is in a drained state. */ 361 bool isDrained() const; 362 363 public: 364 /** Constructs a CPU with the given parameters. */ 365 FullO3CPU(DerivO3CPUParams *params); 366 /** Destructor. */ 367 ~FullO3CPU(); 368 369 /** Registers statistics. */ 370 void regStats(); 371 372 void demapPage(Addr vaddr, uint64_t asn) 373 { 374 this->itb->demapPage(vaddr, asn); 375 this->dtb->demapPage(vaddr, asn); 376 } 377 378 void demapInstPage(Addr vaddr, uint64_t asn) 379 { 380 this->itb->demapPage(vaddr, asn); 381 } 382 383 void demapDataPage(Addr vaddr, uint64_t asn) 384 { 385 this->dtb->demapPage(vaddr, asn); 386 } 387 388 /** Ticks CPU, calling tick() on each stage, and checking the overall 389 * activity to see if the CPU should deschedule itself. 390 */ 391 void tick(); 392 393 /** Initialize the CPU */ 394 void init(); 395 396 void startup(); 397 398 /** Returns the Number of Active Threads in the CPU */ 399 int numActiveThreads() 400 { return activeThreads.size(); } 401 402 /** Add Thread to Active Threads List */ 403 void activateThread(ThreadID tid); 404 405 /** Remove Thread from Active Threads List */ 406 void deactivateThread(ThreadID tid); 407 408 /** Setup CPU to insert a thread's context */ 409 void insertThread(ThreadID tid); 410 411 /** Remove all of a thread's context from CPU */ 412 void removeThread(ThreadID tid); 413 414 /** Count the Total Instructions Committed in the CPU. */ 415 virtual Counter totalInsts() const; 416 417 /** Count the Total Ops (including micro ops) committed in the CPU. */ 418 virtual Counter totalOps() const; 419 420 /** Add Thread to Active Threads List. */ 421 void activateContext(ThreadID tid, Cycles delay); 422 423 /** Remove Thread from Active Threads List */ 424 void suspendContext(ThreadID tid); 425 426 /** Remove Thread from Active Threads List && 427 * Possibly Remove Thread Context from CPU. 428 */ 429 bool scheduleDeallocateContext(ThreadID tid, bool remove, 430 Cycles delay = Cycles(1)); 431 432 /** Remove Thread from Active Threads List && 433 * Remove Thread Context from CPU. 434 */ 435 void haltContext(ThreadID tid); 436 437 /** Activate a Thread When CPU Resources are Available. */ 438 void activateWhenReady(ThreadID tid); 439 440 /** Add or Remove a Thread Context in the CPU. */ 441 void doContextSwitch(); 442 443 /** Update The Order In Which We Process Threads. */ 444 void updateThreadPriority(); 445 446 /** Is the CPU draining? */ 447 bool isDraining() const { return getDrainState() == Drainable::Draining; } 448 449 void serializeThread(std::ostream &os, ThreadID tid); 450 451 void unserializeThread(Checkpoint *cp, const std::string §ion, 452 ThreadID tid); 453 454 public: 455 /** Executes a syscall. 456 * @todo: Determine if this needs to be virtual. 457 */ 458 void syscall(int64_t callnum, ThreadID tid); 459 460 /** Starts draining the CPU's pipeline of all instructions in 461 * order to stop all memory accesses. */ 462 unsigned int drain(DrainManager *drain_manager); 463 464 /** Resumes execution after a drain. */ 465 void drainResume(); 466 467 /** 468 * Commit has reached a safe point to drain a thread. 469 * 470 * Commit calls this method to inform the pipeline that it has 471 * reached a point where it is not executed microcode and is about 472 * to squash uncommitted instructions to fully drain the pipeline. 473 */ 474 void commitDrained(ThreadID tid); 475 476 /** Switches out this CPU. */ 477 virtual void switchOut(); 478 479 /** Takes over from another CPU. */ 480 virtual void takeOverFrom(BaseCPU *oldCPU); 481 482 void verifyMemoryMode() const; 483 484 /** Get the current instruction sequence number, and increment it. */ 485 InstSeqNum getAndIncrementInstSeq() 486 { return globalSeqNum++; } 487 488 /** Traps to handle given fault. */ 489 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 490 491 /** HW return from error interrupt. */ 492 Fault hwrei(ThreadID tid); 493 494 bool simPalCheck(int palFunc, ThreadID tid); 495 496 /** Returns the Fault for any valid interrupt. */ 497 Fault getInterrupts(); 498 499 /** Processes any an interrupt fault. */ 500 void processInterrupts(Fault interrupt); 501 502 /** Halts the CPU. */ 503 void halt() { panic("Halt not implemented!\n"); } 504 505 /** Check if this address is a valid instruction address. */ 506 bool validInstAddr(Addr addr) { return true; } 507 508 /** Check if this address is a valid data address. */ 509 bool validDataAddr(Addr addr) { return true; } 510 511 /** Register accessors. Index refers to the physical register index. */ 512 513 /** Reads a miscellaneous register. */ 514 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 515 516 /** Reads a misc. register, including any side effects the read 517 * might have as defined by the architecture. 518 */ 519 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 520 521 /** Sets a miscellaneous register. */ 522 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 523 ThreadID tid); 524 525 /** Sets a misc. register, including any side effects the write 526 * might have as defined by the architecture. 527 */ 528 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 529 ThreadID tid); 530 531 uint64_t readIntReg(int reg_idx); 532 533 TheISA::FloatReg readFloatReg(int reg_idx); 534 535 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 536 537 void setIntReg(int reg_idx, uint64_t val); 538 539 void setFloatReg(int reg_idx, TheISA::FloatReg val); 540 541 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 542 543 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 544 545 float readArchFloatReg(int reg_idx, ThreadID tid); 546 547 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 548 549 /** Architectural register accessors. Looks up in the commit 550 * rename table to obtain the true physical index of the 551 * architected register first, then accesses that physical 552 * register. 553 */ 554 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 555 556 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 557 558 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 559 560 /** Sets the commit PC state of a specific thread. */ 561 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 562 563 /** Reads the commit PC state of a specific thread. */ 564 TheISA::PCState pcState(ThreadID tid); 565 566 /** Reads the commit PC of a specific thread. */ 567 Addr instAddr(ThreadID tid); 568 569 /** Reads the commit micro PC of a specific thread. */ 570 MicroPC microPC(ThreadID tid); 571 572 /** Reads the next PC of a specific thread. */ 573 Addr nextInstAddr(ThreadID tid); 574 575 /** Initiates a squash of all in-flight instructions for a given 576 * thread. The source of the squash is an external update of 577 * state through the TC. 578 */ 579 void squashFromTC(ThreadID tid); 580 581 /** Function to add instruction onto the head of the list of the 582 * instructions. Used when new instructions are fetched. 583 */ 584 ListIt addInst(DynInstPtr &inst); 585 586 /** Function to tell the CPU that an instruction has completed. */ 587 void instDone(ThreadID tid, DynInstPtr &inst); 588 589 /** Remove an instruction from the front end of the list. There's 590 * no restriction on location of the instruction. 591 */ 592 void removeFrontInst(DynInstPtr &inst); 593 594 /** Remove all instructions that are not currently in the ROB. 595 * There's also an option to not squash delay slot instructions.*/ 596 void removeInstsNotInROB(ThreadID tid); 597 598 /** Remove all instructions younger than the given sequence number. */ 599 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 600 601 /** Removes the instruction pointed to by the iterator. */ 602 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 603 604 /** Cleans up all instructions on the remove list. */ 605 void cleanUpRemovedInsts(); 606 607 /** Debug function to print all instructions on the list. */ 608 void dumpInsts(); 609 610 public: 611#ifndef NDEBUG 612 /** Count of total number of dynamic instructions in flight. */ 613 int instcount; 614#endif 615 616 /** List of all the instructions in flight. */ 617 std::list<DynInstPtr> instList; 618 619 /** List of all the instructions that will be removed at the end of this 620 * cycle. 621 */ 622 std::queue<ListIt> removeList; 623 624#ifdef DEBUG 625 /** Debug structure to keep track of the sequence numbers still in 626 * flight. 627 */ 628 std::set<InstSeqNum> snList; 629#endif 630 631 /** Records if instructions need to be removed this cycle due to 632 * being retired or squashed. 633 */ 634 bool removeInstsThisCycle; 635 636 protected: 637 /** The fetch stage. */ 638 typename CPUPolicy::Fetch fetch; 639 640 /** The decode stage. */ 641 typename CPUPolicy::Decode decode; 642 643 /** The dispatch stage. */ 644 typename CPUPolicy::Rename rename; 645 646 /** The issue/execute/writeback stages. */ 647 typename CPUPolicy::IEW iew; 648 649 /** The commit stage. */ 650 typename CPUPolicy::Commit commit; 651 652 /** The register file. */ 653 typename CPUPolicy::RegFile regFile; 654 655 /** The free list. */ 656 typename CPUPolicy::FreeList freeList; 657 658 /** The rename map. */ 659 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 660 661 /** The commit rename map. */ 662 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 663 664 /** The re-order buffer. */ 665 typename CPUPolicy::ROB rob; 666 667 /** Active Threads List */ 668 std::list<ThreadID> activeThreads; 669 670 /** Integer Register Scoreboard */ 671 Scoreboard scoreboard; 672 673 std::vector<TheISA::ISA *> isa; 674 675 /** Instruction port. Note that it has to appear after the fetch stage. */ 676 IcachePort icachePort; 677 678 /** Data port. Note that it has to appear after the iew stages */ 679 DcachePort dcachePort; 680 681 public: 682 /** Enum to give each stage a specific index, so when calling 683 * activateStage() or deactivateStage(), they can specify which stage 684 * is being activated/deactivated. 685 */ 686 enum StageIdx { 687 FetchIdx, 688 DecodeIdx, 689 RenameIdx, 690 IEWIdx, 691 CommitIdx, 692 NumStages }; 693 694 /** Typedefs from the Impl to get the structs that each of the 695 * time buffers should use. 696 */ 697 typedef typename CPUPolicy::TimeStruct TimeStruct; 698 699 typedef typename CPUPolicy::FetchStruct FetchStruct; 700 701 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 702 703 typedef typename CPUPolicy::RenameStruct RenameStruct; 704 705 typedef typename CPUPolicy::IEWStruct IEWStruct; 706 707 /** The main time buffer to do backwards communication. */ 708 TimeBuffer<TimeStruct> timeBuffer; 709 710 /** The fetch stage's instruction queue. */ 711 TimeBuffer<FetchStruct> fetchQueue; 712 713 /** The decode stage's instruction queue. */ 714 TimeBuffer<DecodeStruct> decodeQueue; 715 716 /** The rename stage's instruction queue. */ 717 TimeBuffer<RenameStruct> renameQueue; 718 719 /** The IEW stage's instruction queue. */ 720 TimeBuffer<IEWStruct> iewQueue; 721 722 private: 723 /** The activity recorder; used to tell if the CPU has any 724 * activity remaining or if it can go to idle and deschedule 725 * itself. 726 */ 727 ActivityRecorder activityRec; 728 729 public: 730 /** Records that there was time buffer activity this cycle. */ 731 void activityThisCycle() { activityRec.activity(); } 732 733 /** Changes a stage's status to active within the activity recorder. */ 734 void activateStage(const StageIdx idx) 735 { activityRec.activateStage(idx); } 736 737 /** Changes a stage's status to inactive within the activity recorder. */ 738 void deactivateStage(const StageIdx idx) 739 { activityRec.deactivateStage(idx); } 740 741 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 742 void wakeCPU(); 743 744 virtual void wakeup(); 745 746 /** Gets a free thread id. Use if thread ids change across system. */ 747 ThreadID getFreeTid(); 748 749 public: 750 /** Returns a pointer to a thread context. */ 751 ThreadContext * 752 tcBase(ThreadID tid) 753 { 754 return thread[tid]->getTC(); 755 } 756 757 /** The global sequence number counter. */ 758 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 759 760 /** Pointer to the checker, which can dynamically verify 761 * instruction results at run time. This can be set to NULL if it 762 * is not being used. 763 */ 764 Checker<Impl> *checker; 765 766 /** Pointer to the system. */ 767 System *system; 768 769 /** DrainManager to notify when draining has completed. */ 770 DrainManager *drainManager; 771 772 /** Pointers to all of the threads in the CPU. */ 773 std::vector<Thread *> thread; 774 775 /** Is there a context switch pending? */ 776 bool contextSwitch; 777 778 /** Threads Scheduled to Enter CPU */ 779 std::list<int> cpuWaitList; 780 781 /** The cycle that the CPU was last running, used for statistics. */ 782 Cycles lastRunningCycle; 783 784 /** The cycle that the CPU was last activated by a new thread*/ 785 Tick lastActivatedCycle; 786 787 /** Mapping for system thread id to cpu id */ 788 std::map<ThreadID, unsigned> threadMap; 789 790 /** Available thread ids in the cpu*/ 791 std::vector<ThreadID> tids; 792 793 /** CPU read function, forwards read to LSQ. */ 794 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 795 uint8_t *data, int load_idx) 796 { 797 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 798 data, load_idx); 799 } 800 801 /** CPU write function, forwards write to LSQ. */ 802 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 803 uint8_t *data, int store_idx) 804 { 805 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 806 data, store_idx); 807 } 808 809 /** Used by the fetch unit to get a hold of the instruction port. */ 810 virtual CpuPort &getInstPort() { return icachePort; } 811 812 /** Get the dcache port (used to find block size for translations). */ 813 virtual CpuPort &getDataPort() { return dcachePort; } 814 815 /** Stat for total number of times the CPU is descheduled. */ 816 Stats::Scalar timesIdled; 817 /** Stat for total number of cycles the CPU spends descheduled. */ 818 Stats::Scalar idleCycles; 819 /** Stat for total number of cycles the CPU spends descheduled due to a 820 * quiesce operation or waiting for an interrupt. */ 821 Stats::Scalar quiesceCycles; 822 /** Stat for the number of committed instructions per thread. */ 823 Stats::Vector committedInsts; 824 /** Stat for the number of committed ops (including micro ops) per thread. */ 825 Stats::Vector committedOps; 826 /** Stat for the total number of committed instructions. */ 827 Stats::Scalar totalCommittedInsts; 828 /** Stat for the CPI per thread. */ 829 Stats::Formula cpi; 830 /** Stat for the total CPI. */ 831 Stats::Formula totalCpi; 832 /** Stat for the IPC per thread. */ 833 Stats::Formula ipc; 834 /** Stat for the total IPC. */ 835 Stats::Formula totalIpc; 836 837 //number of integer register file accesses 838 Stats::Scalar intRegfileReads; 839 Stats::Scalar intRegfileWrites; 840 //number of float register file accesses 841 Stats::Scalar fpRegfileReads; 842 Stats::Scalar fpRegfileWrites; 843 //number of misc 844 Stats::Scalar miscRegfileReads; 845 Stats::Scalar miscRegfileWrites; 846}; 847 848#endif // __CPU_O3_CPU_HH__ 849