cpu.hh revision 9436:4a0223da4924
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#ifndef __CPU_O3_CPU_HH__ 47#define __CPU_O3_CPU_HH__ 48 49#include <iostream> 50#include <list> 51#include <queue> 52#include <set> 53#include <vector> 54 55#include "arch/types.hh" 56#include "base/statistics.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/o3/cpu_policy.hh" 60#include "cpu/o3/scoreboard.hh" 61#include "cpu/o3/thread_state.hh" 62#include "cpu/activity.hh" 63#include "cpu/base.hh" 64#include "cpu/simple_thread.hh" 65#include "cpu/timebuf.hh" 66//#include "cpu/o3/thread_context.hh" 67#include "params/DerivO3CPU.hh" 68#include "sim/process.hh" 69 70template <class> 71class Checker; 72class ThreadContext; 73template <class> 74class O3ThreadContext; 75 76class Checkpoint; 77class MemObject; 78class Process; 79 80struct BaseCPUParams; 81 82class BaseO3CPU : public BaseCPU 83{ 84 //Stuff that's pretty ISA independent will go here. 85 public: 86 BaseO3CPU(BaseCPUParams *params); 87 88 void regStats(); 89}; 90 91/** 92 * FullO3CPU class, has each of the stages (fetch through commit) 93 * within it, as well as all of the time buffers between stages. The 94 * tick() function for the CPU is defined here. 95 */ 96template <class Impl> 97class FullO3CPU : public BaseO3CPU 98{ 99 public: 100 // Typedefs from the Impl here. 101 typedef typename Impl::CPUPol CPUPolicy; 102 typedef typename Impl::DynInstPtr DynInstPtr; 103 typedef typename Impl::O3CPU O3CPU; 104 105 typedef O3ThreadState<Impl> ImplState; 106 typedef O3ThreadState<Impl> Thread; 107 108 typedef typename std::list<DynInstPtr>::iterator ListIt; 109 110 friend class O3ThreadContext<Impl>; 111 112 public: 113 enum Status { 114 Running, 115 Idle, 116 Halted, 117 Blocked, 118 SwitchedOut 119 }; 120 121 TheISA::TLB * itb; 122 TheISA::TLB * dtb; 123 124 /** Overall CPU status. */ 125 Status _status; 126 127 private: 128 129 /** 130 * IcachePort class for instruction fetch. 131 */ 132 class IcachePort : public CpuPort 133 { 134 protected: 135 /** Pointer to fetch. */ 136 DefaultFetch<Impl> *fetch; 137 138 public: 139 /** Default constructor. */ 140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 141 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 142 { } 143 144 protected: 145 146 /** Timing version of receive. Handles setting fetch to the 147 * proper status to start fetching. */ 148 virtual bool recvTimingResp(PacketPtr pkt); 149 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 150 151 /** Handles doing a retry of a failed fetch. */ 152 virtual void recvRetry(); 153 }; 154 155 /** 156 * DcachePort class for the load/store queue. 157 */ 158 class DcachePort : public CpuPort 159 { 160 protected: 161 162 /** Pointer to LSQ. */ 163 LSQ<Impl> *lsq; 164 165 public: 166 /** Default constructor. */ 167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 168 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 169 { } 170 171 protected: 172 173 /** Timing version of receive. Handles writing back and 174 * completing the load or store that has returned from 175 * memory. */ 176 virtual bool recvTimingResp(PacketPtr pkt); 177 virtual void recvTimingSnoopReq(PacketPtr pkt); 178 179 /** Handles doing a retry of the previous send. */ 180 virtual void recvRetry(); 181 182 /** 183 * As this CPU requires snooping to maintain the load store queue 184 * change the behaviour from the base CPU port. 185 * 186 * @return true since we have to snoop 187 */ 188 virtual bool isSnooping() const { return true; } 189 }; 190 191 class TickEvent : public Event 192 { 193 private: 194 /** Pointer to the CPU. */ 195 FullO3CPU<Impl> *cpu; 196 197 public: 198 /** Constructs a tick event. */ 199 TickEvent(FullO3CPU<Impl> *c); 200 201 /** Processes a tick event, calling tick() on the CPU. */ 202 void process(); 203 /** Returns the description of the tick event. */ 204 const char *description() const; 205 }; 206 207 /** The tick event used for scheduling CPU ticks. */ 208 TickEvent tickEvent; 209 210 /** Schedule tick event, regardless of its current state. */ 211 void scheduleTickEvent(Cycles delay) 212 { 213 if (tickEvent.squashed()) 214 reschedule(tickEvent, clockEdge(delay)); 215 else if (!tickEvent.scheduled()) 216 schedule(tickEvent, clockEdge(delay)); 217 } 218 219 /** Unschedule tick event, regardless of its current state. */ 220 void unscheduleTickEvent() 221 { 222 if (tickEvent.scheduled()) 223 tickEvent.squash(); 224 } 225 226 class ActivateThreadEvent : public Event 227 { 228 private: 229 /** Number of Thread to Activate */ 230 ThreadID tid; 231 232 /** Pointer to the CPU. */ 233 FullO3CPU<Impl> *cpu; 234 235 public: 236 /** Constructs the event. */ 237 ActivateThreadEvent(); 238 239 /** Initialize Event */ 240 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 241 242 /** Processes the event, calling activateThread() on the CPU. */ 243 void process(); 244 245 /** Returns the description of the event. */ 246 const char *description() const; 247 }; 248 249 /** Schedule thread to activate , regardless of its current state. */ 250 void 251 scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 252 { 253 // Schedule thread to activate, regardless of its current state. 254 if (activateThreadEvent[tid].squashed()) 255 reschedule(activateThreadEvent[tid], 256 clockEdge(delay)); 257 else if (!activateThreadEvent[tid].scheduled()) { 258 Tick when = clockEdge(delay); 259 260 // Check if the deallocateEvent is also scheduled, and make 261 // sure they do not happen at same time causing a sleep that 262 // is never woken from. 263 if (deallocateContextEvent[tid].scheduled() && 264 deallocateContextEvent[tid].when() == when) { 265 when++; 266 } 267 268 schedule(activateThreadEvent[tid], when); 269 } 270 } 271 272 /** Unschedule actiavte thread event, regardless of its current state. */ 273 void 274 unscheduleActivateThreadEvent(ThreadID tid) 275 { 276 if (activateThreadEvent[tid].scheduled()) 277 activateThreadEvent[tid].squash(); 278 } 279 280 /** The tick event used for scheduling CPU ticks. */ 281 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 282 283 class DeallocateContextEvent : public Event 284 { 285 private: 286 /** Number of Thread to deactivate */ 287 ThreadID tid; 288 289 /** Should the thread be removed from the CPU? */ 290 bool remove; 291 292 /** Pointer to the CPU. */ 293 FullO3CPU<Impl> *cpu; 294 295 public: 296 /** Constructs the event. */ 297 DeallocateContextEvent(); 298 299 /** Initialize Event */ 300 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 301 302 /** Processes the event, calling activateThread() on the CPU. */ 303 void process(); 304 305 /** Sets whether the thread should also be removed from the CPU. */ 306 void setRemove(bool _remove) { remove = _remove; } 307 308 /** Returns the description of the event. */ 309 const char *description() const; 310 }; 311 312 /** Schedule cpu to deallocate thread context.*/ 313 void 314 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 315 { 316 // Schedule thread to activate, regardless of its current state. 317 if (deallocateContextEvent[tid].squashed()) 318 reschedule(deallocateContextEvent[tid], 319 clockEdge(delay)); 320 else if (!deallocateContextEvent[tid].scheduled()) 321 schedule(deallocateContextEvent[tid], 322 clockEdge(delay)); 323 } 324 325 /** Unschedule thread deallocation in CPU */ 326 void 327 unscheduleDeallocateContextEvent(ThreadID tid) 328 { 329 if (deallocateContextEvent[tid].scheduled()) 330 deallocateContextEvent[tid].squash(); 331 } 332 333 /** The tick event used for scheduling CPU ticks. */ 334 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 335 336 public: 337 /** Constructs a CPU with the given parameters. */ 338 FullO3CPU(DerivO3CPUParams *params); 339 /** Destructor. */ 340 ~FullO3CPU(); 341 342 /** Registers statistics. */ 343 void regStats(); 344 345 void demapPage(Addr vaddr, uint64_t asn) 346 { 347 this->itb->demapPage(vaddr, asn); 348 this->dtb->demapPage(vaddr, asn); 349 } 350 351 void demapInstPage(Addr vaddr, uint64_t asn) 352 { 353 this->itb->demapPage(vaddr, asn); 354 } 355 356 void demapDataPage(Addr vaddr, uint64_t asn) 357 { 358 this->dtb->demapPage(vaddr, asn); 359 } 360 361 /** Ticks CPU, calling tick() on each stage, and checking the overall 362 * activity to see if the CPU should deschedule itself. 363 */ 364 void tick(); 365 366 /** Initialize the CPU */ 367 void init(); 368 369 void startup(); 370 371 /** Returns the Number of Active Threads in the CPU */ 372 int numActiveThreads() 373 { return activeThreads.size(); } 374 375 /** Add Thread to Active Threads List */ 376 void activateThread(ThreadID tid); 377 378 /** Remove Thread from Active Threads List */ 379 void deactivateThread(ThreadID tid); 380 381 /** Setup CPU to insert a thread's context */ 382 void insertThread(ThreadID tid); 383 384 /** Remove all of a thread's context from CPU */ 385 void removeThread(ThreadID tid); 386 387 /** Count the Total Instructions Committed in the CPU. */ 388 virtual Counter totalInsts() const; 389 390 /** Count the Total Ops (including micro ops) committed in the CPU. */ 391 virtual Counter totalOps() const; 392 393 /** Add Thread to Active Threads List. */ 394 void activateContext(ThreadID tid, Cycles delay); 395 396 /** Remove Thread from Active Threads List */ 397 void suspendContext(ThreadID tid); 398 399 /** Remove Thread from Active Threads List && 400 * Possibly Remove Thread Context from CPU. 401 */ 402 bool scheduleDeallocateContext(ThreadID tid, bool remove, 403 Cycles delay = Cycles(1)); 404 405 /** Remove Thread from Active Threads List && 406 * Remove Thread Context from CPU. 407 */ 408 void haltContext(ThreadID tid); 409 410 /** Activate a Thread When CPU Resources are Available. */ 411 void activateWhenReady(ThreadID tid); 412 413 /** Add or Remove a Thread Context in the CPU. */ 414 void doContextSwitch(); 415 416 /** Update The Order In Which We Process Threads. */ 417 void updateThreadPriority(); 418 419 /** Serialize state. */ 420 virtual void serialize(std::ostream &os); 421 422 /** Unserialize from a checkpoint. */ 423 virtual void unserialize(Checkpoint *cp, const std::string §ion); 424 425 public: 426 /** Executes a syscall. 427 * @todo: Determine if this needs to be virtual. 428 */ 429 void syscall(int64_t callnum, ThreadID tid); 430 431 /** Starts draining the CPU's pipeline of all instructions in 432 * order to stop all memory accesses. */ 433 unsigned int drain(DrainManager *drain_manager); 434 435 /** Resumes execution after a drain. */ 436 void drainResume(); 437 438 /** Signals to this CPU that a stage has completed switching out. */ 439 void signalDrained(); 440 441 /** Switches out this CPU. */ 442 virtual void switchOut(); 443 444 /** Takes over from another CPU. */ 445 virtual void takeOverFrom(BaseCPU *oldCPU); 446 447 /** Get the current instruction sequence number, and increment it. */ 448 InstSeqNum getAndIncrementInstSeq() 449 { return globalSeqNum++; } 450 451 /** Traps to handle given fault. */ 452 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 453 454 /** HW return from error interrupt. */ 455 Fault hwrei(ThreadID tid); 456 457 bool simPalCheck(int palFunc, ThreadID tid); 458 459 /** Returns the Fault for any valid interrupt. */ 460 Fault getInterrupts(); 461 462 /** Processes any an interrupt fault. */ 463 void processInterrupts(Fault interrupt); 464 465 /** Halts the CPU. */ 466 void halt() { panic("Halt not implemented!\n"); } 467 468 /** Check if this address is a valid instruction address. */ 469 bool validInstAddr(Addr addr) { return true; } 470 471 /** Check if this address is a valid data address. */ 472 bool validDataAddr(Addr addr) { return true; } 473 474 /** Register accessors. Index refers to the physical register index. */ 475 476 /** Reads a miscellaneous register. */ 477 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 478 479 /** Reads a misc. register, including any side effects the read 480 * might have as defined by the architecture. 481 */ 482 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 483 484 /** Sets a miscellaneous register. */ 485 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 486 ThreadID tid); 487 488 /** Sets a misc. register, including any side effects the write 489 * might have as defined by the architecture. 490 */ 491 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 492 ThreadID tid); 493 494 uint64_t readIntReg(int reg_idx); 495 496 TheISA::FloatReg readFloatReg(int reg_idx); 497 498 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 499 500 void setIntReg(int reg_idx, uint64_t val); 501 502 void setFloatReg(int reg_idx, TheISA::FloatReg val); 503 504 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 505 506 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 507 508 float readArchFloatReg(int reg_idx, ThreadID tid); 509 510 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 511 512 /** Architectural register accessors. Looks up in the commit 513 * rename table to obtain the true physical index of the 514 * architected register first, then accesses that physical 515 * register. 516 */ 517 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 518 519 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 520 521 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 522 523 /** Sets the commit PC state of a specific thread. */ 524 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 525 526 /** Reads the commit PC state of a specific thread. */ 527 TheISA::PCState pcState(ThreadID tid); 528 529 /** Reads the commit PC of a specific thread. */ 530 Addr instAddr(ThreadID tid); 531 532 /** Reads the commit micro PC of a specific thread. */ 533 MicroPC microPC(ThreadID tid); 534 535 /** Reads the next PC of a specific thread. */ 536 Addr nextInstAddr(ThreadID tid); 537 538 /** Initiates a squash of all in-flight instructions for a given 539 * thread. The source of the squash is an external update of 540 * state through the TC. 541 */ 542 void squashFromTC(ThreadID tid); 543 544 /** Function to add instruction onto the head of the list of the 545 * instructions. Used when new instructions are fetched. 546 */ 547 ListIt addInst(DynInstPtr &inst); 548 549 /** Function to tell the CPU that an instruction has completed. */ 550 void instDone(ThreadID tid, DynInstPtr &inst); 551 552 /** Remove an instruction from the front end of the list. There's 553 * no restriction on location of the instruction. 554 */ 555 void removeFrontInst(DynInstPtr &inst); 556 557 /** Remove all instructions that are not currently in the ROB. 558 * There's also an option to not squash delay slot instructions.*/ 559 void removeInstsNotInROB(ThreadID tid); 560 561 /** Remove all instructions younger than the given sequence number. */ 562 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 563 564 /** Removes the instruction pointed to by the iterator. */ 565 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 566 567 /** Cleans up all instructions on the remove list. */ 568 void cleanUpRemovedInsts(); 569 570 /** Debug function to print all instructions on the list. */ 571 void dumpInsts(); 572 573 public: 574#ifndef NDEBUG 575 /** Count of total number of dynamic instructions in flight. */ 576 int instcount; 577#endif 578 579 /** List of all the instructions in flight. */ 580 std::list<DynInstPtr> instList; 581 582 /** List of all the instructions that will be removed at the end of this 583 * cycle. 584 */ 585 std::queue<ListIt> removeList; 586 587#ifdef DEBUG 588 /** Debug structure to keep track of the sequence numbers still in 589 * flight. 590 */ 591 std::set<InstSeqNum> snList; 592#endif 593 594 /** Records if instructions need to be removed this cycle due to 595 * being retired or squashed. 596 */ 597 bool removeInstsThisCycle; 598 599 protected: 600 /** The fetch stage. */ 601 typename CPUPolicy::Fetch fetch; 602 603 /** The decode stage. */ 604 typename CPUPolicy::Decode decode; 605 606 /** The dispatch stage. */ 607 typename CPUPolicy::Rename rename; 608 609 /** The issue/execute/writeback stages. */ 610 typename CPUPolicy::IEW iew; 611 612 /** The commit stage. */ 613 typename CPUPolicy::Commit commit; 614 615 /** The register file. */ 616 typename CPUPolicy::RegFile regFile; 617 618 /** The free list. */ 619 typename CPUPolicy::FreeList freeList; 620 621 /** The rename map. */ 622 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 623 624 /** The commit rename map. */ 625 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 626 627 /** The re-order buffer. */ 628 typename CPUPolicy::ROB rob; 629 630 /** Active Threads List */ 631 std::list<ThreadID> activeThreads; 632 633 /** Integer Register Scoreboard */ 634 Scoreboard scoreboard; 635 636 std::vector<TheISA::ISA *> isa; 637 638 /** Instruction port. Note that it has to appear after the fetch stage. */ 639 IcachePort icachePort; 640 641 /** Data port. Note that it has to appear after the iew stages */ 642 DcachePort dcachePort; 643 644 public: 645 /** Enum to give each stage a specific index, so when calling 646 * activateStage() or deactivateStage(), they can specify which stage 647 * is being activated/deactivated. 648 */ 649 enum StageIdx { 650 FetchIdx, 651 DecodeIdx, 652 RenameIdx, 653 IEWIdx, 654 CommitIdx, 655 NumStages }; 656 657 /** Typedefs from the Impl to get the structs that each of the 658 * time buffers should use. 659 */ 660 typedef typename CPUPolicy::TimeStruct TimeStruct; 661 662 typedef typename CPUPolicy::FetchStruct FetchStruct; 663 664 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 665 666 typedef typename CPUPolicy::RenameStruct RenameStruct; 667 668 typedef typename CPUPolicy::IEWStruct IEWStruct; 669 670 /** The main time buffer to do backwards communication. */ 671 TimeBuffer<TimeStruct> timeBuffer; 672 673 /** The fetch stage's instruction queue. */ 674 TimeBuffer<FetchStruct> fetchQueue; 675 676 /** The decode stage's instruction queue. */ 677 TimeBuffer<DecodeStruct> decodeQueue; 678 679 /** The rename stage's instruction queue. */ 680 TimeBuffer<RenameStruct> renameQueue; 681 682 /** The IEW stage's instruction queue. */ 683 TimeBuffer<IEWStruct> iewQueue; 684 685 private: 686 /** The activity recorder; used to tell if the CPU has any 687 * activity remaining or if it can go to idle and deschedule 688 * itself. 689 */ 690 ActivityRecorder activityRec; 691 692 public: 693 /** Records that there was time buffer activity this cycle. */ 694 void activityThisCycle() { activityRec.activity(); } 695 696 /** Changes a stage's status to active within the activity recorder. */ 697 void activateStage(const StageIdx idx) 698 { activityRec.activateStage(idx); } 699 700 /** Changes a stage's status to inactive within the activity recorder. */ 701 void deactivateStage(const StageIdx idx) 702 { activityRec.deactivateStage(idx); } 703 704 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 705 void wakeCPU(); 706 707 virtual void wakeup(); 708 709 /** Gets a free thread id. Use if thread ids change across system. */ 710 ThreadID getFreeTid(); 711 712 public: 713 /** Returns a pointer to a thread context. */ 714 ThreadContext * 715 tcBase(ThreadID tid) 716 { 717 return thread[tid]->getTC(); 718 } 719 720 /** The global sequence number counter. */ 721 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 722 723 /** Pointer to the checker, which can dynamically verify 724 * instruction results at run time. This can be set to NULL if it 725 * is not being used. 726 */ 727 Checker<Impl> *checker; 728 729 /** Pointer to the system. */ 730 System *system; 731 732 /** DrainManager to notify when draining has completed. */ 733 DrainManager *drainManager; 734 735 /** Counter of how many stages have completed draining. */ 736 int drainCount; 737 738 /** Pointers to all of the threads in the CPU. */ 739 std::vector<Thread *> thread; 740 741 /** Is there a context switch pending? */ 742 bool contextSwitch; 743 744 /** Threads Scheduled to Enter CPU */ 745 std::list<int> cpuWaitList; 746 747 /** The cycle that the CPU was last running, used for statistics. */ 748 Cycles lastRunningCycle; 749 750 /** The cycle that the CPU was last activated by a new thread*/ 751 Tick lastActivatedCycle; 752 753 /** Mapping for system thread id to cpu id */ 754 std::map<ThreadID, unsigned> threadMap; 755 756 /** Available thread ids in the cpu*/ 757 std::vector<ThreadID> tids; 758 759 /** CPU read function, forwards read to LSQ. */ 760 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 761 uint8_t *data, int load_idx) 762 { 763 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 764 data, load_idx); 765 } 766 767 /** CPU write function, forwards write to LSQ. */ 768 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 769 uint8_t *data, int store_idx) 770 { 771 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 772 data, store_idx); 773 } 774 775 /** Used by the fetch unit to get a hold of the instruction port. */ 776 virtual CpuPort &getInstPort() { return icachePort; } 777 778 /** Get the dcache port (used to find block size for translations). */ 779 virtual CpuPort &getDataPort() { return dcachePort; } 780 781 /** Stat for total number of times the CPU is descheduled. */ 782 Stats::Scalar timesIdled; 783 /** Stat for total number of cycles the CPU spends descheduled. */ 784 Stats::Scalar idleCycles; 785 /** Stat for total number of cycles the CPU spends descheduled due to a 786 * quiesce operation or waiting for an interrupt. */ 787 Stats::Scalar quiesceCycles; 788 /** Stat for the number of committed instructions per thread. */ 789 Stats::Vector committedInsts; 790 /** Stat for the number of committed ops (including micro ops) per thread. */ 791 Stats::Vector committedOps; 792 /** Stat for the total number of committed instructions. */ 793 Stats::Scalar totalCommittedInsts; 794 /** Stat for the CPI per thread. */ 795 Stats::Formula cpi; 796 /** Stat for the total CPI. */ 797 Stats::Formula totalCpi; 798 /** Stat for the IPC per thread. */ 799 Stats::Formula ipc; 800 /** Stat for the total IPC. */ 801 Stats::Formula totalIpc; 802 803 //number of integer register file accesses 804 Stats::Scalar intRegfileReads; 805 Stats::Scalar intRegfileWrites; 806 //number of float register file accesses 807 Stats::Scalar fpRegfileReads; 808 Stats::Scalar fpRegfileWrites; 809 //number of misc 810 Stats::Scalar miscRegfileReads; 811 Stats::Scalar miscRegfileWrites; 812}; 813 814#endif // __CPU_O3_CPU_HH__ 815