cpu.hh revision 8737
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#ifndef __CPU_O3_CPU_HH__ 47#define __CPU_O3_CPU_HH__ 48 49#include <iostream> 50#include <list> 51#include <queue> 52#include <set> 53#include <vector> 54 55#include "arch/types.hh" 56#include "base/statistics.hh" 57#include "config/full_system.hh" 58#include "config/the_isa.hh" 59#include "config/use_checker.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class MemObject; 80class Process; 81 82struct BaseCPUParams; 83 84class BaseO3CPU : public BaseCPU 85{ 86 //Stuff that's pretty ISA independent will go here. 87 public: 88 BaseO3CPU(BaseCPUParams *params); 89 90 void regStats(); 91}; 92 93/** 94 * FullO3CPU class, has each of the stages (fetch through commit) 95 * within it, as well as all of the time buffers between stages. The 96 * tick() function for the CPU is defined here. 97 */ 98template <class Impl> 99class FullO3CPU : public BaseO3CPU 100{ 101 public: 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 typedef O3ThreadState<Impl> ImplState; 108 typedef O3ThreadState<Impl> Thread; 109 110 typedef typename std::list<DynInstPtr>::iterator ListIt; 111 112 friend class O3ThreadContext<Impl>; 113 114 public: 115 enum Status { 116 Running, 117 Idle, 118 Halted, 119 Blocked, 120 SwitchedOut 121 }; 122 123 TheISA::TLB * itb; 124 TheISA::TLB * dtb; 125 126 /** Overall CPU status. */ 127 Status _status; 128 129 /** Per-thread status in CPU, used for SMT. */ 130 Status _threadStatus[Impl::MaxThreads]; 131 132 private: 133 134 /** 135 * IcachePort class for instruction fetch. 136 */ 137 class IcachePort : public CpuPort 138 { 139 protected: 140 /** Pointer to fetch. */ 141 DefaultFetch<Impl> *fetch; 142 143 public: 144 /** Default constructor. */ 145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 146 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) 147 { } 148 149 protected: 150 151 /** Timing version of receive. Handles setting fetch to the 152 * proper status to start fetching. */ 153 virtual bool recvTiming(PacketPtr pkt); 154 155 /** Handles doing a retry of a failed fetch. */ 156 virtual void recvRetry(); 157 }; 158 159 /** 160 * DcachePort class for the load/store queue. 161 */ 162 class DcachePort : public CpuPort 163 { 164 protected: 165 166 /** Pointer to LSQ. */ 167 LSQ<Impl> *lsq; 168 169 public: 170 /** Default constructor. */ 171 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 172 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq) 173 { } 174 175 protected: 176 177 /** Timing version of receive. Handles writing back and 178 * completing the load or store that has returned from 179 * memory. */ 180 virtual bool recvTiming(PacketPtr pkt); 181 182 /** Handles doing a retry of the previous send. */ 183 virtual void recvRetry(); 184 185 /** 186 * As this CPU requires snooping to maintain the load store queue 187 * change the behaviour from the base CPU port. 188 * 189 * @return true since we have to snoop 190 */ 191 virtual bool isSnooping() 192 { return true; } 193 }; 194 195 class TickEvent : public Event 196 { 197 private: 198 /** Pointer to the CPU. */ 199 FullO3CPU<Impl> *cpu; 200 201 public: 202 /** Constructs a tick event. */ 203 TickEvent(FullO3CPU<Impl> *c); 204 205 /** Processes a tick event, calling tick() on the CPU. */ 206 void process(); 207 /** Returns the description of the tick event. */ 208 const char *description() const; 209 }; 210 211 /** The tick event used for scheduling CPU ticks. */ 212 TickEvent tickEvent; 213 214 /** Schedule tick event, regardless of its current state. */ 215 void scheduleTickEvent(int delay) 216 { 217 if (tickEvent.squashed()) 218 reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 219 else if (!tickEvent.scheduled()) 220 schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 221 } 222 223 /** Unschedule tick event, regardless of its current state. */ 224 void unscheduleTickEvent() 225 { 226 if (tickEvent.scheduled()) 227 tickEvent.squash(); 228 } 229 230 class ActivateThreadEvent : public Event 231 { 232 private: 233 /** Number of Thread to Activate */ 234 ThreadID tid; 235 236 /** Pointer to the CPU. */ 237 FullO3CPU<Impl> *cpu; 238 239 public: 240 /** Constructs the event. */ 241 ActivateThreadEvent(); 242 243 /** Initialize Event */ 244 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 245 246 /** Processes the event, calling activateThread() on the CPU. */ 247 void process(); 248 249 /** Returns the description of the event. */ 250 const char *description() const; 251 }; 252 253 /** Schedule thread to activate , regardless of its current state. */ 254 void 255 scheduleActivateThreadEvent(ThreadID tid, int delay) 256 { 257 // Schedule thread to activate, regardless of its current state. 258 if (activateThreadEvent[tid].squashed()) 259 reschedule(activateThreadEvent[tid], 260 nextCycle(curTick() + ticks(delay))); 261 else if (!activateThreadEvent[tid].scheduled()) { 262 Tick when = nextCycle(curTick() + ticks(delay)); 263 264 // Check if the deallocateEvent is also scheduled, and make 265 // sure they do not happen at same time causing a sleep that 266 // is never woken from. 267 if (deallocateContextEvent[tid].scheduled() && 268 deallocateContextEvent[tid].when() == when) { 269 when++; 270 } 271 272 schedule(activateThreadEvent[tid], when); 273 } 274 } 275 276 /** Unschedule actiavte thread event, regardless of its current state. */ 277 void 278 unscheduleActivateThreadEvent(ThreadID tid) 279 { 280 if (activateThreadEvent[tid].scheduled()) 281 activateThreadEvent[tid].squash(); 282 } 283 284 /** The tick event used for scheduling CPU ticks. */ 285 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 286 287 class DeallocateContextEvent : public Event 288 { 289 private: 290 /** Number of Thread to deactivate */ 291 ThreadID tid; 292 293 /** Should the thread be removed from the CPU? */ 294 bool remove; 295 296 /** Pointer to the CPU. */ 297 FullO3CPU<Impl> *cpu; 298 299 public: 300 /** Constructs the event. */ 301 DeallocateContextEvent(); 302 303 /** Initialize Event */ 304 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 305 306 /** Processes the event, calling activateThread() on the CPU. */ 307 void process(); 308 309 /** Sets whether the thread should also be removed from the CPU. */ 310 void setRemove(bool _remove) { remove = _remove; } 311 312 /** Returns the description of the event. */ 313 const char *description() const; 314 }; 315 316 /** Schedule cpu to deallocate thread context.*/ 317 void 318 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 319 { 320 // Schedule thread to activate, regardless of its current state. 321 if (deallocateContextEvent[tid].squashed()) 322 reschedule(deallocateContextEvent[tid], 323 nextCycle(curTick() + ticks(delay))); 324 else if (!deallocateContextEvent[tid].scheduled()) 325 schedule(deallocateContextEvent[tid], 326 nextCycle(curTick() + ticks(delay))); 327 } 328 329 /** Unschedule thread deallocation in CPU */ 330 void 331 unscheduleDeallocateContextEvent(ThreadID tid) 332 { 333 if (deallocateContextEvent[tid].scheduled()) 334 deallocateContextEvent[tid].squash(); 335 } 336 337 /** The tick event used for scheduling CPU ticks. */ 338 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 339 340 public: 341 /** Constructs a CPU with the given parameters. */ 342 FullO3CPU(DerivO3CPUParams *params); 343 /** Destructor. */ 344 ~FullO3CPU(); 345 346 /** Registers statistics. */ 347 void regStats(); 348 349 void demapPage(Addr vaddr, uint64_t asn) 350 { 351 this->itb->demapPage(vaddr, asn); 352 this->dtb->demapPage(vaddr, asn); 353 } 354 355 void demapInstPage(Addr vaddr, uint64_t asn) 356 { 357 this->itb->demapPage(vaddr, asn); 358 } 359 360 void demapDataPage(Addr vaddr, uint64_t asn) 361 { 362 this->dtb->demapPage(vaddr, asn); 363 } 364 365 /** Returns a specific port. */ 366 Port *getPort(const std::string &if_name, int idx); 367 368 /** Ticks CPU, calling tick() on each stage, and checking the overall 369 * activity to see if the CPU should deschedule itself. 370 */ 371 void tick(); 372 373 /** Initialize the CPU */ 374 void init(); 375 376 /** Returns the Number of Active Threads in the CPU */ 377 int numActiveThreads() 378 { return activeThreads.size(); } 379 380 /** Add Thread to Active Threads List */ 381 void activateThread(ThreadID tid); 382 383 /** Remove Thread from Active Threads List */ 384 void deactivateThread(ThreadID tid); 385 386 /** Setup CPU to insert a thread's context */ 387 void insertThread(ThreadID tid); 388 389 /** Remove all of a thread's context from CPU */ 390 void removeThread(ThreadID tid); 391 392 /** Count the Total Instructions Committed in the CPU. */ 393 virtual Counter totalInstructions() const; 394 395 /** Add Thread to Active Threads List. */ 396 void activateContext(ThreadID tid, int delay); 397 398 /** Remove Thread from Active Threads List */ 399 void suspendContext(ThreadID tid); 400 401 /** Remove Thread from Active Threads List && 402 * Possibly Remove Thread Context from CPU. 403 */ 404 bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1); 405 406 /** Remove Thread from Active Threads List && 407 * Remove Thread Context from CPU. 408 */ 409 void haltContext(ThreadID tid); 410 411 /** Activate a Thread When CPU Resources are Available. */ 412 void activateWhenReady(ThreadID tid); 413 414 /** Add or Remove a Thread Context in the CPU. */ 415 void doContextSwitch(); 416 417 /** Update The Order In Which We Process Threads. */ 418 void updateThreadPriority(); 419 420 /** Serialize state. */ 421 virtual void serialize(std::ostream &os); 422 423 /** Unserialize from a checkpoint. */ 424 virtual void unserialize(Checkpoint *cp, const std::string §ion); 425 426 public: 427#if !FULL_SYSTEM 428 /** Executes a syscall. 429 * @todo: Determine if this needs to be virtual. 430 */ 431 void syscall(int64_t callnum, ThreadID tid); 432#endif 433 434 /** Starts draining the CPU's pipeline of all instructions in 435 * order to stop all memory accesses. */ 436 virtual unsigned int drain(Event *drain_event); 437 438 /** Resumes execution after a drain. */ 439 virtual void resume(); 440 441 /** Signals to this CPU that a stage has completed switching out. */ 442 void signalDrained(); 443 444 /** Switches out this CPU. */ 445 virtual void switchOut(); 446 447 /** Takes over from another CPU. */ 448 virtual void takeOverFrom(BaseCPU *oldCPU); 449 450 /** Get the current instruction sequence number, and increment it. */ 451 InstSeqNum getAndIncrementInstSeq() 452 { return globalSeqNum++; } 453 454 /** Traps to handle given fault. */ 455 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 456 457#if FULL_SYSTEM 458 /** HW return from error interrupt. */ 459 Fault hwrei(ThreadID tid); 460 461 bool simPalCheck(int palFunc, ThreadID tid); 462 463 /** Returns the Fault for any valid interrupt. */ 464 Fault getInterrupts(); 465 466 /** Processes any an interrupt fault. */ 467 void processInterrupts(Fault interrupt); 468 469 /** Halts the CPU. */ 470 void halt() { panic("Halt not implemented!\n"); } 471 472 /** Check if this address is a valid instruction address. */ 473 bool validInstAddr(Addr addr) { return true; } 474 475 /** Check if this address is a valid data address. */ 476 bool validDataAddr(Addr addr) { return true; } 477#endif 478 479 /** Register accessors. Index refers to the physical register index. */ 480 481 /** Reads a miscellaneous register. */ 482 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 483 484 /** Reads a misc. register, including any side effects the read 485 * might have as defined by the architecture. 486 */ 487 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 488 489 /** Sets a miscellaneous register. */ 490 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 491 ThreadID tid); 492 493 /** Sets a misc. register, including any side effects the write 494 * might have as defined by the architecture. 495 */ 496 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 497 ThreadID tid); 498 499 uint64_t readIntReg(int reg_idx); 500 501 TheISA::FloatReg readFloatReg(int reg_idx); 502 503 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 504 505 void setIntReg(int reg_idx, uint64_t val); 506 507 void setFloatReg(int reg_idx, TheISA::FloatReg val); 508 509 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 510 511 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 512 513 float readArchFloatReg(int reg_idx, ThreadID tid); 514 515 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 516 517 /** Architectural register accessors. Looks up in the commit 518 * rename table to obtain the true physical index of the 519 * architected register first, then accesses that physical 520 * register. 521 */ 522 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 523 524 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 525 526 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 527 528 /** Sets the commit PC state of a specific thread. */ 529 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 530 531 /** Reads the commit PC state of a specific thread. */ 532 TheISA::PCState pcState(ThreadID tid); 533 534 /** Reads the commit PC of a specific thread. */ 535 Addr instAddr(ThreadID tid); 536 537 /** Reads the commit micro PC of a specific thread. */ 538 MicroPC microPC(ThreadID tid); 539 540 /** Reads the next PC of a specific thread. */ 541 Addr nextInstAddr(ThreadID tid); 542 543 /** Initiates a squash of all in-flight instructions for a given 544 * thread. The source of the squash is an external update of 545 * state through the TC. 546 */ 547 void squashFromTC(ThreadID tid); 548 549 /** Function to add instruction onto the head of the list of the 550 * instructions. Used when new instructions are fetched. 551 */ 552 ListIt addInst(DynInstPtr &inst); 553 554 /** Function to tell the CPU that an instruction has completed. */ 555 void instDone(ThreadID tid); 556 557 /** Remove an instruction from the front end of the list. There's 558 * no restriction on location of the instruction. 559 */ 560 void removeFrontInst(DynInstPtr &inst); 561 562 /** Remove all instructions that are not currently in the ROB. 563 * There's also an option to not squash delay slot instructions.*/ 564 void removeInstsNotInROB(ThreadID tid); 565 566 /** Remove all instructions younger than the given sequence number. */ 567 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 568 569 /** Removes the instruction pointed to by the iterator. */ 570 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 571 572 /** Cleans up all instructions on the remove list. */ 573 void cleanUpRemovedInsts(); 574 575 /** Debug function to print all instructions on the list. */ 576 void dumpInsts(); 577 578 public: 579#ifndef NDEBUG 580 /** Count of total number of dynamic instructions in flight. */ 581 int instcount; 582#endif 583 584 /** List of all the instructions in flight. */ 585 std::list<DynInstPtr> instList; 586 587 /** List of all the instructions that will be removed at the end of this 588 * cycle. 589 */ 590 std::queue<ListIt> removeList; 591 592#ifdef DEBUG 593 /** Debug structure to keep track of the sequence numbers still in 594 * flight. 595 */ 596 std::set<InstSeqNum> snList; 597#endif 598 599 /** Records if instructions need to be removed this cycle due to 600 * being retired or squashed. 601 */ 602 bool removeInstsThisCycle; 603 604 protected: 605 /** The fetch stage. */ 606 typename CPUPolicy::Fetch fetch; 607 608 /** The decode stage. */ 609 typename CPUPolicy::Decode decode; 610 611 /** The dispatch stage. */ 612 typename CPUPolicy::Rename rename; 613 614 /** The issue/execute/writeback stages. */ 615 typename CPUPolicy::IEW iew; 616 617 /** The commit stage. */ 618 typename CPUPolicy::Commit commit; 619 620 /** The register file. */ 621 typename CPUPolicy::RegFile regFile; 622 623 /** The free list. */ 624 typename CPUPolicy::FreeList freeList; 625 626 /** The rename map. */ 627 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 628 629 /** The commit rename map. */ 630 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 631 632 /** The re-order buffer. */ 633 typename CPUPolicy::ROB rob; 634 635 /** Active Threads List */ 636 std::list<ThreadID> activeThreads; 637 638 /** Integer Register Scoreboard */ 639 Scoreboard scoreboard; 640 641 TheISA::ISA isa[Impl::MaxThreads]; 642 643 /** Instruction port. Note that it has to appear after the fetch stage. */ 644 IcachePort icachePort; 645 646 /** Data port. Note that it has to appear after the iew stages */ 647 DcachePort dcachePort; 648 649 public: 650 /** Enum to give each stage a specific index, so when calling 651 * activateStage() or deactivateStage(), they can specify which stage 652 * is being activated/deactivated. 653 */ 654 enum StageIdx { 655 FetchIdx, 656 DecodeIdx, 657 RenameIdx, 658 IEWIdx, 659 CommitIdx, 660 NumStages }; 661 662 /** Typedefs from the Impl to get the structs that each of the 663 * time buffers should use. 664 */ 665 typedef typename CPUPolicy::TimeStruct TimeStruct; 666 667 typedef typename CPUPolicy::FetchStruct FetchStruct; 668 669 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 670 671 typedef typename CPUPolicy::RenameStruct RenameStruct; 672 673 typedef typename CPUPolicy::IEWStruct IEWStruct; 674 675 /** The main time buffer to do backwards communication. */ 676 TimeBuffer<TimeStruct> timeBuffer; 677 678 /** The fetch stage's instruction queue. */ 679 TimeBuffer<FetchStruct> fetchQueue; 680 681 /** The decode stage's instruction queue. */ 682 TimeBuffer<DecodeStruct> decodeQueue; 683 684 /** The rename stage's instruction queue. */ 685 TimeBuffer<RenameStruct> renameQueue; 686 687 /** The IEW stage's instruction queue. */ 688 TimeBuffer<IEWStruct> iewQueue; 689 690 private: 691 /** The activity recorder; used to tell if the CPU has any 692 * activity remaining or if it can go to idle and deschedule 693 * itself. 694 */ 695 ActivityRecorder activityRec; 696 697 public: 698 /** Records that there was time buffer activity this cycle. */ 699 void activityThisCycle() { activityRec.activity(); } 700 701 /** Changes a stage's status to active within the activity recorder. */ 702 void activateStage(const StageIdx idx) 703 { activityRec.activateStage(idx); } 704 705 /** Changes a stage's status to inactive within the activity recorder. */ 706 void deactivateStage(const StageIdx idx) 707 { activityRec.deactivateStage(idx); } 708 709 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 710 void wakeCPU(); 711 712#if FULL_SYSTEM 713 virtual void wakeup(); 714#endif 715 716 /** Gets a free thread id. Use if thread ids change across system. */ 717 ThreadID getFreeTid(); 718 719 public: 720 /** Returns a pointer to a thread context. */ 721 ThreadContext * 722 tcBase(ThreadID tid) 723 { 724 return thread[tid]->getTC(); 725 } 726 727 /** The global sequence number counter. */ 728 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 729 730#if USE_CHECKER 731 /** Pointer to the checker, which can dynamically verify 732 * instruction results at run time. This can be set to NULL if it 733 * is not being used. 734 */ 735 Checker<Impl> *checker; 736#endif 737 738 /** Pointer to the system. */ 739 System *system; 740 741 /** Event to call process() on once draining has completed. */ 742 Event *drainEvent; 743 744 /** Counter of how many stages have completed draining. */ 745 int drainCount; 746 747 /** Pointers to all of the threads in the CPU. */ 748 std::vector<Thread *> thread; 749 750 /** Whether or not the CPU should defer its registration. */ 751 bool deferRegistration; 752 753 /** Is there a context switch pending? */ 754 bool contextSwitch; 755 756 /** Threads Scheduled to Enter CPU */ 757 std::list<int> cpuWaitList; 758 759 /** The cycle that the CPU was last running, used for statistics. */ 760 Tick lastRunningCycle; 761 762 /** The cycle that the CPU was last activated by a new thread*/ 763 Tick lastActivatedCycle; 764 765 /** Mapping for system thread id to cpu id */ 766 std::map<ThreadID, unsigned> threadMap; 767 768 /** Available thread ids in the cpu*/ 769 std::vector<ThreadID> tids; 770 771 /** CPU read function, forwards read to LSQ. */ 772 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 773 uint8_t *data, int load_idx) 774 { 775 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 776 data, load_idx); 777 } 778 779 /** CPU write function, forwards write to LSQ. */ 780 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 781 uint8_t *data, int store_idx) 782 { 783 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 784 data, store_idx); 785 } 786 787 /** Used by the fetch unit to get a hold of the instruction port. */ 788 Port* getIcachePort() { return &icachePort; } 789 790 /** Get the dcache port (used to find block size for translations). */ 791 Port* getDcachePort() { return &dcachePort; } 792 793 Addr lockAddr; 794 795 /** Temporary fix for the lock flag, works in the UP case. */ 796 bool lockFlag; 797 798 /** Stat for total number of times the CPU is descheduled. */ 799 Stats::Scalar timesIdled; 800 /** Stat for total number of cycles the CPU spends descheduled. */ 801 Stats::Scalar idleCycles; 802 /** Stat for total number of cycles the CPU spends descheduled due to a 803 * quiesce operation or waiting for an interrupt. */ 804 Stats::Scalar quiesceCycles; 805 /** Stat for the number of committed instructions per thread. */ 806 Stats::Vector committedInsts; 807 /** Stat for the total number of committed instructions. */ 808 Stats::Scalar totalCommittedInsts; 809 /** Stat for the CPI per thread. */ 810 Stats::Formula cpi; 811 /** Stat for the total CPI. */ 812 Stats::Formula totalCpi; 813 /** Stat for the IPC per thread. */ 814 Stats::Formula ipc; 815 /** Stat for the total IPC. */ 816 Stats::Formula totalIpc; 817 818 //number of integer register file accesses 819 Stats::Scalar intRegfileReads; 820 Stats::Scalar intRegfileWrites; 821 //number of float register file accesses 822 Stats::Scalar fpRegfileReads; 823 Stats::Scalar fpRegfileWrites; 824 //number of misc 825 Stats::Scalar miscRegfileReads; 826 Stats::Scalar miscRegfileWrites; 827}; 828 829#endif // __CPU_O3_CPU_HH__ 830