cpu.hh revision 6331:d947798df4a1
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/types.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "config/use_checker.hh" 46#include "cpu/activity.hh" 47#include "cpu/base.hh" 48#include "cpu/simple_thread.hh" 49#include "cpu/o3/comm.hh" 50#include "cpu/o3/cpu_policy.hh" 51#include "cpu/o3/scoreboard.hh" 52#include "cpu/o3/thread_state.hh" 53//#include "cpu/o3/thread_context.hh" 54#include "sim/process.hh" 55 56#include "params/DerivO3CPU.hh" 57 58template <class> 59class Checker; 60class ThreadContext; 61template <class> 62class O3ThreadContext; 63 64class Checkpoint; 65class MemObject; 66class Process; 67 68class BaseCPUParams; 69 70class BaseO3CPU : public BaseCPU 71{ 72 //Stuff that's pretty ISA independent will go here. 73 public: 74 BaseO3CPU(BaseCPUParams *params); 75 76 void regStats(); 77}; 78 79/** 80 * FullO3CPU class, has each of the stages (fetch through commit) 81 * within it, as well as all of the time buffers between stages. The 82 * tick() function for the CPU is defined here. 83 */ 84template <class Impl> 85class FullO3CPU : public BaseO3CPU 86{ 87 public: 88 // Typedefs from the Impl here. 89 typedef typename Impl::CPUPol CPUPolicy; 90 typedef typename Impl::DynInstPtr DynInstPtr; 91 typedef typename Impl::O3CPU O3CPU; 92 93 typedef O3ThreadState<Impl> ImplState; 94 typedef O3ThreadState<Impl> Thread; 95 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 friend class O3ThreadContext<Impl>; 99 100 public: 101 enum Status { 102 Running, 103 Idle, 104 Halted, 105 Blocked, 106 SwitchedOut 107 }; 108 109 TheISA::TLB * itb; 110 TheISA::TLB * dtb; 111 112 /** Overall CPU status. */ 113 Status _status; 114 115 /** Per-thread status in CPU, used for SMT. */ 116 Status _threadStatus[Impl::MaxThreads]; 117 118 private: 119 class TickEvent : public Event 120 { 121 private: 122 /** Pointer to the CPU. */ 123 FullO3CPU<Impl> *cpu; 124 125 public: 126 /** Constructs a tick event. */ 127 TickEvent(FullO3CPU<Impl> *c); 128 129 /** Processes a tick event, calling tick() on the CPU. */ 130 void process(); 131 /** Returns the description of the tick event. */ 132 const char *description() const; 133 }; 134 135 /** The tick event used for scheduling CPU ticks. */ 136 TickEvent tickEvent; 137 138 /** Schedule tick event, regardless of its current state. */ 139 void scheduleTickEvent(int delay) 140 { 141 if (tickEvent.squashed()) 142 reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 143 else if (!tickEvent.scheduled()) 144 schedule(tickEvent, nextCycle(curTick + ticks(delay))); 145 } 146 147 /** Unschedule tick event, regardless of its current state. */ 148 void unscheduleTickEvent() 149 { 150 if (tickEvent.scheduled()) 151 tickEvent.squash(); 152 } 153 154 class ActivateThreadEvent : public Event 155 { 156 private: 157 /** Number of Thread to Activate */ 158 ThreadID tid; 159 160 /** Pointer to the CPU. */ 161 FullO3CPU<Impl> *cpu; 162 163 public: 164 /** Constructs the event. */ 165 ActivateThreadEvent(); 166 167 /** Initialize Event */ 168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 169 170 /** Processes the event, calling activateThread() on the CPU. */ 171 void process(); 172 173 /** Returns the description of the event. */ 174 const char *description() const; 175 }; 176 177 /** Schedule thread to activate , regardless of its current state. */ 178 void 179 scheduleActivateThreadEvent(ThreadID tid, int delay) 180 { 181 // Schedule thread to activate, regardless of its current state. 182 if (activateThreadEvent[tid].squashed()) 183 reschedule(activateThreadEvent[tid], 184 nextCycle(curTick + ticks(delay))); 185 else if (!activateThreadEvent[tid].scheduled()) 186 schedule(activateThreadEvent[tid], 187 nextCycle(curTick + ticks(delay))); 188 } 189 190 /** Unschedule actiavte thread event, regardless of its current state. */ 191 void 192 unscheduleActivateThreadEvent(ThreadID tid) 193 { 194 if (activateThreadEvent[tid].scheduled()) 195 activateThreadEvent[tid].squash(); 196 } 197 198 /** The tick event used for scheduling CPU ticks. */ 199 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 200 201 class DeallocateContextEvent : public Event 202 { 203 private: 204 /** Number of Thread to deactivate */ 205 ThreadID tid; 206 207 /** Should the thread be removed from the CPU? */ 208 bool remove; 209 210 /** Pointer to the CPU. */ 211 FullO3CPU<Impl> *cpu; 212 213 public: 214 /** Constructs the event. */ 215 DeallocateContextEvent(); 216 217 /** Initialize Event */ 218 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 219 220 /** Processes the event, calling activateThread() on the CPU. */ 221 void process(); 222 223 /** Sets whether the thread should also be removed from the CPU. */ 224 void setRemove(bool _remove) { remove = _remove; } 225 226 /** Returns the description of the event. */ 227 const char *description() const; 228 }; 229 230 /** Schedule cpu to deallocate thread context.*/ 231 void 232 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 233 { 234 // Schedule thread to activate, regardless of its current state. 235 if (deallocateContextEvent[tid].squashed()) 236 reschedule(deallocateContextEvent[tid], 237 nextCycle(curTick + ticks(delay))); 238 else if (!deallocateContextEvent[tid].scheduled()) 239 schedule(deallocateContextEvent[tid], 240 nextCycle(curTick + ticks(delay))); 241 } 242 243 /** Unschedule thread deallocation in CPU */ 244 void 245 unscheduleDeallocateContextEvent(ThreadID tid) 246 { 247 if (deallocateContextEvent[tid].scheduled()) 248 deallocateContextEvent[tid].squash(); 249 } 250 251 /** The tick event used for scheduling CPU ticks. */ 252 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 253 254 public: 255 /** Constructs a CPU with the given parameters. */ 256 FullO3CPU(DerivO3CPUParams *params); 257 /** Destructor. */ 258 ~FullO3CPU(); 259 260 /** Registers statistics. */ 261 void regStats(); 262 263 void demapPage(Addr vaddr, uint64_t asn) 264 { 265 this->itb->demapPage(vaddr, asn); 266 this->dtb->demapPage(vaddr, asn); 267 } 268 269 void demapInstPage(Addr vaddr, uint64_t asn) 270 { 271 this->itb->demapPage(vaddr, asn); 272 } 273 274 void demapDataPage(Addr vaddr, uint64_t asn) 275 { 276 this->dtb->demapPage(vaddr, asn); 277 } 278 279 /** Returns a specific port. */ 280 Port *getPort(const std::string &if_name, int idx); 281 282 /** Ticks CPU, calling tick() on each stage, and checking the overall 283 * activity to see if the CPU should deschedule itself. 284 */ 285 void tick(); 286 287 /** Initialize the CPU */ 288 void init(); 289 290 /** Returns the Number of Active Threads in the CPU */ 291 int numActiveThreads() 292 { return activeThreads.size(); } 293 294 /** Add Thread to Active Threads List */ 295 void activateThread(ThreadID tid); 296 297 /** Remove Thread from Active Threads List */ 298 void deactivateThread(ThreadID tid); 299 300 /** Setup CPU to insert a thread's context */ 301 void insertThread(ThreadID tid); 302 303 /** Remove all of a thread's context from CPU */ 304 void removeThread(ThreadID tid); 305 306 /** Count the Total Instructions Committed in the CPU. */ 307 virtual Counter totalInstructions() const; 308 309 /** Add Thread to Active Threads List. */ 310 void activateContext(ThreadID tid, int delay); 311 312 /** Remove Thread from Active Threads List */ 313 void suspendContext(ThreadID tid); 314 315 /** Remove Thread from Active Threads List && 316 * Possibly Remove Thread Context from CPU. 317 */ 318 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 319 320 /** Remove Thread from Active Threads List && 321 * Remove Thread Context from CPU. 322 */ 323 void haltContext(ThreadID tid); 324 325 /** Activate a Thread When CPU Resources are Available. */ 326 void activateWhenReady(ThreadID tid); 327 328 /** Add or Remove a Thread Context in the CPU. */ 329 void doContextSwitch(); 330 331 /** Update The Order In Which We Process Threads. */ 332 void updateThreadPriority(); 333 334 /** Serialize state. */ 335 virtual void serialize(std::ostream &os); 336 337 /** Unserialize from a checkpoint. */ 338 virtual void unserialize(Checkpoint *cp, const std::string §ion); 339 340 public: 341#if !FULL_SYSTEM 342 /** Executes a syscall. 343 * @todo: Determine if this needs to be virtual. 344 */ 345 void syscall(int64_t callnum, ThreadID tid); 346#endif 347 348 /** Starts draining the CPU's pipeline of all instructions in 349 * order to stop all memory accesses. */ 350 virtual unsigned int drain(Event *drain_event); 351 352 /** Resumes execution after a drain. */ 353 virtual void resume(); 354 355 /** Signals to this CPU that a stage has completed switching out. */ 356 void signalDrained(); 357 358 /** Switches out this CPU. */ 359 virtual void switchOut(); 360 361 /** Takes over from another CPU. */ 362 virtual void takeOverFrom(BaseCPU *oldCPU); 363 364 /** Get the current instruction sequence number, and increment it. */ 365 InstSeqNum getAndIncrementInstSeq() 366 { return globalSeqNum++; } 367 368 /** Traps to handle given fault. */ 369 void trap(Fault fault, ThreadID tid); 370 371#if FULL_SYSTEM 372 /** HW return from error interrupt. */ 373 Fault hwrei(ThreadID tid); 374 375 bool simPalCheck(int palFunc, ThreadID tid); 376 377 /** Returns the Fault for any valid interrupt. */ 378 Fault getInterrupts(); 379 380 /** Processes any an interrupt fault. */ 381 void processInterrupts(Fault interrupt); 382 383 /** Halts the CPU. */ 384 void halt() { panic("Halt not implemented!\n"); } 385 386 /** Update the Virt and Phys ports of all ThreadContexts to 387 * reflect change in memory connections. */ 388 void updateMemPorts(); 389 390 /** Check if this address is a valid instruction address. */ 391 bool validInstAddr(Addr addr) { return true; } 392 393 /** Check if this address is a valid data address. */ 394 bool validDataAddr(Addr addr) { return true; } 395#endif 396 397 /** Register accessors. Index refers to the physical register index. */ 398 399 /** Reads a miscellaneous register. */ 400 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 401 402 /** Reads a misc. register, including any side effects the read 403 * might have as defined by the architecture. 404 */ 405 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 406 407 /** Sets a miscellaneous register. */ 408 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 409 ThreadID tid); 410 411 /** Sets a misc. register, including any side effects the write 412 * might have as defined by the architecture. 413 */ 414 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 415 ThreadID tid); 416 417 uint64_t readIntReg(int reg_idx); 418 419 TheISA::FloatReg readFloatReg(int reg_idx); 420 421 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 422 423 void setIntReg(int reg_idx, uint64_t val); 424 425 void setFloatReg(int reg_idx, TheISA::FloatReg val); 426 427 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 428 429 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 430 431 float readArchFloatReg(int reg_idx, ThreadID tid); 432 433 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 434 435 /** Architectural register accessors. Looks up in the commit 436 * rename table to obtain the true physical index of the 437 * architected register first, then accesses that physical 438 * register. 439 */ 440 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 441 442 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 443 444 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 445 446 /** Reads the commit PC of a specific thread. */ 447 Addr readPC(ThreadID tid); 448 449 /** Sets the commit PC of a specific thread. */ 450 void setPC(Addr new_PC, ThreadID tid); 451 452 /** Reads the commit micro PC of a specific thread. */ 453 Addr readMicroPC(ThreadID tid); 454 455 /** Sets the commmit micro PC of a specific thread. */ 456 void setMicroPC(Addr new_microPC, ThreadID tid); 457 458 /** Reads the next PC of a specific thread. */ 459 Addr readNextPC(ThreadID tid); 460 461 /** Sets the next PC of a specific thread. */ 462 void setNextPC(Addr val, ThreadID tid); 463 464 /** Reads the next NPC of a specific thread. */ 465 Addr readNextNPC(ThreadID tid); 466 467 /** Sets the next NPC of a specific thread. */ 468 void setNextNPC(Addr val, ThreadID tid); 469 470 /** Reads the commit next micro PC of a specific thread. */ 471 Addr readNextMicroPC(ThreadID tid); 472 473 /** Sets the commit next micro PC of a specific thread. */ 474 void setNextMicroPC(Addr val, ThreadID tid); 475 476 /** Initiates a squash of all in-flight instructions for a given 477 * thread. The source of the squash is an external update of 478 * state through the TC. 479 */ 480 void squashFromTC(ThreadID tid); 481 482 /** Function to add instruction onto the head of the list of the 483 * instructions. Used when new instructions are fetched. 484 */ 485 ListIt addInst(DynInstPtr &inst); 486 487 /** Function to tell the CPU that an instruction has completed. */ 488 void instDone(ThreadID tid); 489 490 /** Add Instructions to the CPU Remove List*/ 491 void addToRemoveList(DynInstPtr &inst); 492 493 /** Remove an instruction from the front end of the list. There's 494 * no restriction on location of the instruction. 495 */ 496 void removeFrontInst(DynInstPtr &inst); 497 498 /** Remove all instructions that are not currently in the ROB. 499 * There's also an option to not squash delay slot instructions.*/ 500 void removeInstsNotInROB(ThreadID tid); 501 502 /** Remove all instructions younger than the given sequence number. */ 503 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 504 505 /** Removes the instruction pointed to by the iterator. */ 506 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 507 508 /** Cleans up all instructions on the remove list. */ 509 void cleanUpRemovedInsts(); 510 511 /** Debug function to print all instructions on the list. */ 512 void dumpInsts(); 513 514 public: 515#ifndef NDEBUG 516 /** Count of total number of dynamic instructions in flight. */ 517 int instcount; 518#endif 519 520 /** List of all the instructions in flight. */ 521 std::list<DynInstPtr> instList; 522 523 /** List of all the instructions that will be removed at the end of this 524 * cycle. 525 */ 526 std::queue<ListIt> removeList; 527 528#ifdef DEBUG 529 /** Debug structure to keep track of the sequence numbers still in 530 * flight. 531 */ 532 std::set<InstSeqNum> snList; 533#endif 534 535 /** Records if instructions need to be removed this cycle due to 536 * being retired or squashed. 537 */ 538 bool removeInstsThisCycle; 539 540 protected: 541 /** The fetch stage. */ 542 typename CPUPolicy::Fetch fetch; 543 544 /** The decode stage. */ 545 typename CPUPolicy::Decode decode; 546 547 /** The dispatch stage. */ 548 typename CPUPolicy::Rename rename; 549 550 /** The issue/execute/writeback stages. */ 551 typename CPUPolicy::IEW iew; 552 553 /** The commit stage. */ 554 typename CPUPolicy::Commit commit; 555 556 /** The register file. */ 557 typename CPUPolicy::RegFile regFile; 558 559 /** The free list. */ 560 typename CPUPolicy::FreeList freeList; 561 562 /** The rename map. */ 563 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 564 565 /** The commit rename map. */ 566 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 567 568 /** The re-order buffer. */ 569 typename CPUPolicy::ROB rob; 570 571 /** Active Threads List */ 572 std::list<ThreadID> activeThreads; 573 574 /** Integer Register Scoreboard */ 575 Scoreboard scoreboard; 576 577 TheISA::ISA isa[Impl::MaxThreads]; 578 579 public: 580 /** Enum to give each stage a specific index, so when calling 581 * activateStage() or deactivateStage(), they can specify which stage 582 * is being activated/deactivated. 583 */ 584 enum StageIdx { 585 FetchIdx, 586 DecodeIdx, 587 RenameIdx, 588 IEWIdx, 589 CommitIdx, 590 NumStages }; 591 592 /** Typedefs from the Impl to get the structs that each of the 593 * time buffers should use. 594 */ 595 typedef typename CPUPolicy::TimeStruct TimeStruct; 596 597 typedef typename CPUPolicy::FetchStruct FetchStruct; 598 599 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 600 601 typedef typename CPUPolicy::RenameStruct RenameStruct; 602 603 typedef typename CPUPolicy::IEWStruct IEWStruct; 604 605 /** The main time buffer to do backwards communication. */ 606 TimeBuffer<TimeStruct> timeBuffer; 607 608 /** The fetch stage's instruction queue. */ 609 TimeBuffer<FetchStruct> fetchQueue; 610 611 /** The decode stage's instruction queue. */ 612 TimeBuffer<DecodeStruct> decodeQueue; 613 614 /** The rename stage's instruction queue. */ 615 TimeBuffer<RenameStruct> renameQueue; 616 617 /** The IEW stage's instruction queue. */ 618 TimeBuffer<IEWStruct> iewQueue; 619 620 private: 621 /** The activity recorder; used to tell if the CPU has any 622 * activity remaining or if it can go to idle and deschedule 623 * itself. 624 */ 625 ActivityRecorder activityRec; 626 627 public: 628 /** Records that there was time buffer activity this cycle. */ 629 void activityThisCycle() { activityRec.activity(); } 630 631 /** Changes a stage's status to active within the activity recorder. */ 632 void activateStage(const StageIdx idx) 633 { activityRec.activateStage(idx); } 634 635 /** Changes a stage's status to inactive within the activity recorder. */ 636 void deactivateStage(const StageIdx idx) 637 { activityRec.deactivateStage(idx); } 638 639 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 640 void wakeCPU(); 641 642#if FULL_SYSTEM 643 virtual void wakeup(); 644#endif 645 646 /** Gets a free thread id. Use if thread ids change across system. */ 647 ThreadID getFreeTid(); 648 649 public: 650 /** Returns a pointer to a thread context. */ 651 ThreadContext * 652 tcBase(ThreadID tid) 653 { 654 return thread[tid]->getTC(); 655 } 656 657 /** The global sequence number counter. */ 658 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 659 660#if USE_CHECKER 661 /** Pointer to the checker, which can dynamically verify 662 * instruction results at run time. This can be set to NULL if it 663 * is not being used. 664 */ 665 Checker<DynInstPtr> *checker; 666#endif 667 668#if FULL_SYSTEM 669 /** Pointer to the system. */ 670 System *system; 671 672 /** Pointer to physical memory. */ 673 PhysicalMemory *physmem; 674#endif 675 676 /** Event to call process() on once draining has completed. */ 677 Event *drainEvent; 678 679 /** Counter of how many stages have completed draining. */ 680 int drainCount; 681 682 /** Pointers to all of the threads in the CPU. */ 683 std::vector<Thread *> thread; 684 685 /** Whether or not the CPU should defer its registration. */ 686 bool deferRegistration; 687 688 /** Is there a context switch pending? */ 689 bool contextSwitch; 690 691 /** Threads Scheduled to Enter CPU */ 692 std::list<int> cpuWaitList; 693 694 /** The cycle that the CPU was last running, used for statistics. */ 695 Tick lastRunningCycle; 696 697 /** The cycle that the CPU was last activated by a new thread*/ 698 Tick lastActivatedCycle; 699 700 /** Mapping for system thread id to cpu id */ 701 std::map<ThreadID, unsigned> threadMap; 702 703 /** Available thread ids in the cpu*/ 704 std::vector<ThreadID> tids; 705 706 /** CPU read function, forwards read to LSQ. */ 707 template <class T> 708 Fault read(RequestPtr &req, T &data, int load_idx) 709 { 710 return this->iew.ldstQueue.read(req, data, load_idx); 711 } 712 713 /** CPU write function, forwards write to LSQ. */ 714 template <class T> 715 Fault write(RequestPtr &req, T &data, int store_idx) 716 { 717 return this->iew.ldstQueue.write(req, data, store_idx); 718 } 719 720 Addr lockAddr; 721 722 /** Temporary fix for the lock flag, works in the UP case. */ 723 bool lockFlag; 724 725 /** Stat for total number of times the CPU is descheduled. */ 726 Stats::Scalar timesIdled; 727 /** Stat for total number of cycles the CPU spends descheduled. */ 728 Stats::Scalar idleCycles; 729 /** Stat for the number of committed instructions per thread. */ 730 Stats::Vector committedInsts; 731 /** Stat for the total number of committed instructions. */ 732 Stats::Scalar totalCommittedInsts; 733 /** Stat for the CPI per thread. */ 734 Stats::Formula cpi; 735 /** Stat for the total CPI. */ 736 Stats::Formula totalCpi; 737 /** Stat for the IPC per thread. */ 738 Stats::Formula ipc; 739 /** Stat for the total IPC. */ 740 Stats::Formula totalIpc; 741}; 742 743#endif // __CPU_O3_CPU_HH__ 744