cpu.hh revision 6314:781969fbeca9
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/types.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "config/use_checker.hh" 46#include "cpu/activity.hh" 47#include "cpu/base.hh" 48#include "cpu/simple_thread.hh" 49#include "cpu/o3/comm.hh" 50#include "cpu/o3/cpu_policy.hh" 51#include "cpu/o3/scoreboard.hh" 52#include "cpu/o3/thread_state.hh" 53//#include "cpu/o3/thread_context.hh" 54#include "sim/process.hh" 55 56#include "params/DerivO3CPU.hh" 57 58template <class> 59class Checker; 60class ThreadContext; 61template <class> 62class O3ThreadContext; 63 64class Checkpoint; 65class MemObject; 66class Process; 67 68class BaseCPUParams; 69 70class BaseO3CPU : public BaseCPU 71{ 72 //Stuff that's pretty ISA independent will go here. 73 public: 74 BaseO3CPU(BaseCPUParams *params); 75 76 void regStats(); 77}; 78 79/** 80 * FullO3CPU class, has each of the stages (fetch through commit) 81 * within it, as well as all of the time buffers between stages. The 82 * tick() function for the CPU is defined here. 83 */ 84template <class Impl> 85class FullO3CPU : public BaseO3CPU 86{ 87 public: 88 // Typedefs from the Impl here. 89 typedef typename Impl::CPUPol CPUPolicy; 90 typedef typename Impl::DynInstPtr DynInstPtr; 91 typedef typename Impl::O3CPU O3CPU; 92 93 typedef O3ThreadState<Impl> ImplState; 94 typedef O3ThreadState<Impl> Thread; 95 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 friend class O3ThreadContext<Impl>; 99 100 public: 101 enum Status { 102 Running, 103 Idle, 104 Halted, 105 Blocked, 106 SwitchedOut 107 }; 108 109 TheISA::TLB * itb; 110 TheISA::TLB * dtb; 111 112 /** Overall CPU status. */ 113 Status _status; 114 115 /** Per-thread status in CPU, used for SMT. */ 116 Status _threadStatus[Impl::MaxThreads]; 117 118 private: 119 class TickEvent : public Event 120 { 121 private: 122 /** Pointer to the CPU. */ 123 FullO3CPU<Impl> *cpu; 124 125 public: 126 /** Constructs a tick event. */ 127 TickEvent(FullO3CPU<Impl> *c); 128 129 /** Processes a tick event, calling tick() on the CPU. */ 130 void process(); 131 /** Returns the description of the tick event. */ 132 const char *description() const; 133 }; 134 135 /** The tick event used for scheduling CPU ticks. */ 136 TickEvent tickEvent; 137 138 /** Schedule tick event, regardless of its current state. */ 139 void scheduleTickEvent(int delay) 140 { 141 if (tickEvent.squashed()) 142 reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 143 else if (!tickEvent.scheduled()) 144 schedule(tickEvent, nextCycle(curTick + ticks(delay))); 145 } 146 147 /** Unschedule tick event, regardless of its current state. */ 148 void unscheduleTickEvent() 149 { 150 if (tickEvent.scheduled()) 151 tickEvent.squash(); 152 } 153 154 class ActivateThreadEvent : public Event 155 { 156 private: 157 /** Number of Thread to Activate */ 158 ThreadID tid; 159 160 /** Pointer to the CPU. */ 161 FullO3CPU<Impl> *cpu; 162 163 public: 164 /** Constructs the event. */ 165 ActivateThreadEvent(); 166 167 /** Initialize Event */ 168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 169 170 /** Processes the event, calling activateThread() on the CPU. */ 171 void process(); 172 173 /** Returns the description of the event. */ 174 const char *description() const; 175 }; 176 177 /** Schedule thread to activate , regardless of its current state. */ 178 void 179 scheduleActivateThreadEvent(ThreadID tid, int delay) 180 { 181 // Schedule thread to activate, regardless of its current state. 182 if (activateThreadEvent[tid].squashed()) 183 reschedule(activateThreadEvent[tid], 184 nextCycle(curTick + ticks(delay))); 185 else if (!activateThreadEvent[tid].scheduled()) 186 schedule(activateThreadEvent[tid], 187 nextCycle(curTick + ticks(delay))); 188 } 189 190 /** Unschedule actiavte thread event, regardless of its current state. */ 191 void 192 unscheduleActivateThreadEvent(ThreadID tid) 193 { 194 if (activateThreadEvent[tid].scheduled()) 195 activateThreadEvent[tid].squash(); 196 } 197 198 /** The tick event used for scheduling CPU ticks. */ 199 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 200 201 class DeallocateContextEvent : public Event 202 { 203 private: 204 /** Number of Thread to deactivate */ 205 ThreadID tid; 206 207 /** Should the thread be removed from the CPU? */ 208 bool remove; 209 210 /** Pointer to the CPU. */ 211 FullO3CPU<Impl> *cpu; 212 213 public: 214 /** Constructs the event. */ 215 DeallocateContextEvent(); 216 217 /** Initialize Event */ 218 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 219 220 /** Processes the event, calling activateThread() on the CPU. */ 221 void process(); 222 223 /** Sets whether the thread should also be removed from the CPU. */ 224 void setRemove(bool _remove) { remove = _remove; } 225 226 /** Returns the description of the event. */ 227 const char *description() const; 228 }; 229 230 /** Schedule cpu to deallocate thread context.*/ 231 void 232 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 233 { 234 // Schedule thread to activate, regardless of its current state. 235 if (deallocateContextEvent[tid].squashed()) 236 reschedule(deallocateContextEvent[tid], 237 nextCycle(curTick + ticks(delay))); 238 else if (!deallocateContextEvent[tid].scheduled()) 239 schedule(deallocateContextEvent[tid], 240 nextCycle(curTick + ticks(delay))); 241 } 242 243 /** Unschedule thread deallocation in CPU */ 244 void 245 unscheduleDeallocateContextEvent(ThreadID tid) 246 { 247 if (deallocateContextEvent[tid].scheduled()) 248 deallocateContextEvent[tid].squash(); 249 } 250 251 /** The tick event used for scheduling CPU ticks. */ 252 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 253 254 public: 255 /** Constructs a CPU with the given parameters. */ 256 FullO3CPU(DerivO3CPUParams *params); 257 /** Destructor. */ 258 ~FullO3CPU(); 259 260 /** Registers statistics. */ 261 void regStats(); 262 263 void demapPage(Addr vaddr, uint64_t asn) 264 { 265 this->itb->demapPage(vaddr, asn); 266 this->dtb->demapPage(vaddr, asn); 267 } 268 269 void demapInstPage(Addr vaddr, uint64_t asn) 270 { 271 this->itb->demapPage(vaddr, asn); 272 } 273 274 void demapDataPage(Addr vaddr, uint64_t asn) 275 { 276 this->dtb->demapPage(vaddr, asn); 277 } 278 279 /** Returns a specific port. */ 280 Port *getPort(const std::string &if_name, int idx); 281 282 /** Ticks CPU, calling tick() on each stage, and checking the overall 283 * activity to see if the CPU should deschedule itself. 284 */ 285 void tick(); 286 287 /** Initialize the CPU */ 288 void init(); 289 290 /** Returns the Number of Active Threads in the CPU */ 291 int numActiveThreads() 292 { return activeThreads.size(); } 293 294 /** Add Thread to Active Threads List */ 295 void activateThread(ThreadID tid); 296 297 /** Remove Thread from Active Threads List */ 298 void deactivateThread(ThreadID tid); 299 300 /** Setup CPU to insert a thread's context */ 301 void insertThread(ThreadID tid); 302 303 /** Remove all of a thread's context from CPU */ 304 void removeThread(ThreadID tid); 305 306 /** Count the Total Instructions Committed in the CPU. */ 307 virtual Counter totalInstructions() const; 308 309 /** Add Thread to Active Threads List. */ 310 void activateContext(ThreadID tid, int delay); 311 312 /** Remove Thread from Active Threads List */ 313 void suspendContext(ThreadID tid); 314 315 /** Remove Thread from Active Threads List && 316 * Possibly Remove Thread Context from CPU. 317 */ 318 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 319 320 /** Remove Thread from Active Threads List && 321 * Remove Thread Context from CPU. 322 */ 323 void haltContext(ThreadID tid); 324 325 /** Activate a Thread When CPU Resources are Available. */ 326 void activateWhenReady(ThreadID tid); 327 328 /** Add or Remove a Thread Context in the CPU. */ 329 void doContextSwitch(); 330 331 /** Update The Order In Which We Process Threads. */ 332 void updateThreadPriority(); 333 334 /** Serialize state. */ 335 virtual void serialize(std::ostream &os); 336 337 /** Unserialize from a checkpoint. */ 338 virtual void unserialize(Checkpoint *cp, const std::string §ion); 339 340 public: 341#if !FULL_SYSTEM 342 /** Executes a syscall. 343 * @todo: Determine if this needs to be virtual. 344 */ 345 void syscall(int64_t callnum, ThreadID tid); 346#endif 347 348 /** Starts draining the CPU's pipeline of all instructions in 349 * order to stop all memory accesses. */ 350 virtual unsigned int drain(Event *drain_event); 351 352 /** Resumes execution after a drain. */ 353 virtual void resume(); 354 355 /** Signals to this CPU that a stage has completed switching out. */ 356 void signalDrained(); 357 358 /** Switches out this CPU. */ 359 virtual void switchOut(); 360 361 /** Takes over from another CPU. */ 362 virtual void takeOverFrom(BaseCPU *oldCPU); 363 364 /** Get the current instruction sequence number, and increment it. */ 365 InstSeqNum getAndIncrementInstSeq() 366 { return globalSeqNum++; } 367 368 /** Traps to handle given fault. */ 369 void trap(Fault fault, ThreadID tid); 370 371#if FULL_SYSTEM 372 /** HW return from error interrupt. */ 373 Fault hwrei(ThreadID tid); 374 375 bool simPalCheck(int palFunc, ThreadID tid); 376 377 /** Returns the Fault for any valid interrupt. */ 378 Fault getInterrupts(); 379 380 /** Processes any an interrupt fault. */ 381 void processInterrupts(Fault interrupt); 382 383 /** Halts the CPU. */ 384 void halt() { panic("Halt not implemented!\n"); } 385 386 /** Update the Virt and Phys ports of all ThreadContexts to 387 * reflect change in memory connections. */ 388 void updateMemPorts(); 389 390 /** Check if this address is a valid instruction address. */ 391 bool validInstAddr(Addr addr) { return true; } 392 393 /** Check if this address is a valid data address. */ 394 bool validDataAddr(Addr addr) { return true; } 395 396 /** Get instruction asid. */ 397 int getInstAsid(ThreadID tid) 398 { return isa[tid].instAsid(); } 399 400 /** Get data asid. */ 401 int getDataAsid(ThreadID tid) 402 { return isa[tid].dataAsid(); } 403#else 404 /** Get instruction asid. */ 405 int getInstAsid(ThreadID tid) 406 { return thread[tid]->getInstAsid(); } 407 408 /** Get data asid. */ 409 int getDataAsid(ThreadID tid) 410 { return thread[tid]->getDataAsid(); } 411 412#endif 413 414 /** Register accessors. Index refers to the physical register index. */ 415 416 /** Reads a miscellaneous register. */ 417 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 418 419 /** Reads a misc. register, including any side effects the read 420 * might have as defined by the architecture. 421 */ 422 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 423 424 /** Sets a miscellaneous register. */ 425 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 426 ThreadID tid); 427 428 /** Sets a misc. register, including any side effects the write 429 * might have as defined by the architecture. 430 */ 431 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 432 ThreadID tid); 433 434 uint64_t readIntReg(int reg_idx); 435 436 TheISA::FloatReg readFloatReg(int reg_idx); 437 438 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 439 440 void setIntReg(int reg_idx, uint64_t val); 441 442 void setFloatReg(int reg_idx, TheISA::FloatReg val); 443 444 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 445 446 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 447 448 float readArchFloatReg(int reg_idx, ThreadID tid); 449 450 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 451 452 /** Architectural register accessors. Looks up in the commit 453 * rename table to obtain the true physical index of the 454 * architected register first, then accesses that physical 455 * register. 456 */ 457 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 458 459 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 460 461 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 462 463 /** Reads the commit PC of a specific thread. */ 464 Addr readPC(ThreadID tid); 465 466 /** Sets the commit PC of a specific thread. */ 467 void setPC(Addr new_PC, ThreadID tid); 468 469 /** Reads the commit micro PC of a specific thread. */ 470 Addr readMicroPC(ThreadID tid); 471 472 /** Sets the commmit micro PC of a specific thread. */ 473 void setMicroPC(Addr new_microPC, ThreadID tid); 474 475 /** Reads the next PC of a specific thread. */ 476 Addr readNextPC(ThreadID tid); 477 478 /** Sets the next PC of a specific thread. */ 479 void setNextPC(Addr val, ThreadID tid); 480 481 /** Reads the next NPC of a specific thread. */ 482 Addr readNextNPC(ThreadID tid); 483 484 /** Sets the next NPC of a specific thread. */ 485 void setNextNPC(Addr val, ThreadID tid); 486 487 /** Reads the commit next micro PC of a specific thread. */ 488 Addr readNextMicroPC(ThreadID tid); 489 490 /** Sets the commit next micro PC of a specific thread. */ 491 void setNextMicroPC(Addr val, ThreadID tid); 492 493 /** Initiates a squash of all in-flight instructions for a given 494 * thread. The source of the squash is an external update of 495 * state through the TC. 496 */ 497 void squashFromTC(ThreadID tid); 498 499 /** Function to add instruction onto the head of the list of the 500 * instructions. Used when new instructions are fetched. 501 */ 502 ListIt addInst(DynInstPtr &inst); 503 504 /** Function to tell the CPU that an instruction has completed. */ 505 void instDone(ThreadID tid); 506 507 /** Add Instructions to the CPU Remove List*/ 508 void addToRemoveList(DynInstPtr &inst); 509 510 /** Remove an instruction from the front end of the list. There's 511 * no restriction on location of the instruction. 512 */ 513 void removeFrontInst(DynInstPtr &inst); 514 515 /** Remove all instructions that are not currently in the ROB. 516 * There's also an option to not squash delay slot instructions.*/ 517 void removeInstsNotInROB(ThreadID tid); 518 519 /** Remove all instructions younger than the given sequence number. */ 520 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 521 522 /** Removes the instruction pointed to by the iterator. */ 523 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 524 525 /** Cleans up all instructions on the remove list. */ 526 void cleanUpRemovedInsts(); 527 528 /** Debug function to print all instructions on the list. */ 529 void dumpInsts(); 530 531 public: 532#ifndef NDEBUG 533 /** Count of total number of dynamic instructions in flight. */ 534 int instcount; 535#endif 536 537 /** List of all the instructions in flight. */ 538 std::list<DynInstPtr> instList; 539 540 /** List of all the instructions that will be removed at the end of this 541 * cycle. 542 */ 543 std::queue<ListIt> removeList; 544 545#ifdef DEBUG 546 /** Debug structure to keep track of the sequence numbers still in 547 * flight. 548 */ 549 std::set<InstSeqNum> snList; 550#endif 551 552 /** Records if instructions need to be removed this cycle due to 553 * being retired or squashed. 554 */ 555 bool removeInstsThisCycle; 556 557 protected: 558 /** The fetch stage. */ 559 typename CPUPolicy::Fetch fetch; 560 561 /** The decode stage. */ 562 typename CPUPolicy::Decode decode; 563 564 /** The dispatch stage. */ 565 typename CPUPolicy::Rename rename; 566 567 /** The issue/execute/writeback stages. */ 568 typename CPUPolicy::IEW iew; 569 570 /** The commit stage. */ 571 typename CPUPolicy::Commit commit; 572 573 /** The register file. */ 574 typename CPUPolicy::RegFile regFile; 575 576 /** The free list. */ 577 typename CPUPolicy::FreeList freeList; 578 579 /** The rename map. */ 580 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 581 582 /** The commit rename map. */ 583 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 584 585 /** The re-order buffer. */ 586 typename CPUPolicy::ROB rob; 587 588 /** Active Threads List */ 589 std::list<ThreadID> activeThreads; 590 591 /** Integer Register Scoreboard */ 592 Scoreboard scoreboard; 593 594 TheISA::ISA isa[Impl::MaxThreads]; 595 596 public: 597 /** Enum to give each stage a specific index, so when calling 598 * activateStage() or deactivateStage(), they can specify which stage 599 * is being activated/deactivated. 600 */ 601 enum StageIdx { 602 FetchIdx, 603 DecodeIdx, 604 RenameIdx, 605 IEWIdx, 606 CommitIdx, 607 NumStages }; 608 609 /** Typedefs from the Impl to get the structs that each of the 610 * time buffers should use. 611 */ 612 typedef typename CPUPolicy::TimeStruct TimeStruct; 613 614 typedef typename CPUPolicy::FetchStruct FetchStruct; 615 616 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 617 618 typedef typename CPUPolicy::RenameStruct RenameStruct; 619 620 typedef typename CPUPolicy::IEWStruct IEWStruct; 621 622 /** The main time buffer to do backwards communication. */ 623 TimeBuffer<TimeStruct> timeBuffer; 624 625 /** The fetch stage's instruction queue. */ 626 TimeBuffer<FetchStruct> fetchQueue; 627 628 /** The decode stage's instruction queue. */ 629 TimeBuffer<DecodeStruct> decodeQueue; 630 631 /** The rename stage's instruction queue. */ 632 TimeBuffer<RenameStruct> renameQueue; 633 634 /** The IEW stage's instruction queue. */ 635 TimeBuffer<IEWStruct> iewQueue; 636 637 private: 638 /** The activity recorder; used to tell if the CPU has any 639 * activity remaining or if it can go to idle and deschedule 640 * itself. 641 */ 642 ActivityRecorder activityRec; 643 644 public: 645 /** Records that there was time buffer activity this cycle. */ 646 void activityThisCycle() { activityRec.activity(); } 647 648 /** Changes a stage's status to active within the activity recorder. */ 649 void activateStage(const StageIdx idx) 650 { activityRec.activateStage(idx); } 651 652 /** Changes a stage's status to inactive within the activity recorder. */ 653 void deactivateStage(const StageIdx idx) 654 { activityRec.deactivateStage(idx); } 655 656 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 657 void wakeCPU(); 658 659#if FULL_SYSTEM 660 virtual void wakeup(); 661#endif 662 663 /** Gets a free thread id. Use if thread ids change across system. */ 664 ThreadID getFreeTid(); 665 666 public: 667 /** Returns a pointer to a thread context. */ 668 ThreadContext * 669 tcBase(ThreadID tid) 670 { 671 return thread[tid]->getTC(); 672 } 673 674 /** The global sequence number counter. */ 675 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 676 677#if USE_CHECKER 678 /** Pointer to the checker, which can dynamically verify 679 * instruction results at run time. This can be set to NULL if it 680 * is not being used. 681 */ 682 Checker<DynInstPtr> *checker; 683#endif 684 685#if FULL_SYSTEM 686 /** Pointer to the system. */ 687 System *system; 688 689 /** Pointer to physical memory. */ 690 PhysicalMemory *physmem; 691#endif 692 693 /** Event to call process() on once draining has completed. */ 694 Event *drainEvent; 695 696 /** Counter of how many stages have completed draining. */ 697 int drainCount; 698 699 /** Pointers to all of the threads in the CPU. */ 700 std::vector<Thread *> thread; 701 702 /** Whether or not the CPU should defer its registration. */ 703 bool deferRegistration; 704 705 /** Is there a context switch pending? */ 706 bool contextSwitch; 707 708 /** Threads Scheduled to Enter CPU */ 709 std::list<int> cpuWaitList; 710 711 /** The cycle that the CPU was last running, used for statistics. */ 712 Tick lastRunningCycle; 713 714 /** The cycle that the CPU was last activated by a new thread*/ 715 Tick lastActivatedCycle; 716 717 /** Mapping for system thread id to cpu id */ 718 std::map<ThreadID, unsigned> threadMap; 719 720 /** Available thread ids in the cpu*/ 721 std::vector<ThreadID> tids; 722 723 /** CPU read function, forwards read to LSQ. */ 724 template <class T> 725 Fault read(RequestPtr &req, T &data, int load_idx) 726 { 727 return this->iew.ldstQueue.read(req, data, load_idx); 728 } 729 730 /** CPU write function, forwards write to LSQ. */ 731 template <class T> 732 Fault write(RequestPtr &req, T &data, int store_idx) 733 { 734 return this->iew.ldstQueue.write(req, data, store_idx); 735 } 736 737 Addr lockAddr; 738 739 /** Temporary fix for the lock flag, works in the UP case. */ 740 bool lockFlag; 741 742 /** Stat for total number of times the CPU is descheduled. */ 743 Stats::Scalar timesIdled; 744 /** Stat for total number of cycles the CPU spends descheduled. */ 745 Stats::Scalar idleCycles; 746 /** Stat for the number of committed instructions per thread. */ 747 Stats::Vector committedInsts; 748 /** Stat for the total number of committed instructions. */ 749 Stats::Scalar totalCommittedInsts; 750 /** Stat for the CPI per thread. */ 751 Stats::Formula cpi; 752 /** Stat for the total CPI. */ 753 Stats::Formula totalCpi; 754 /** Stat for the IPC per thread. */ 755 Stats::Formula ipc; 756 /** Stat for the total IPC. */ 757 Stats::Formula totalIpc; 758}; 759 760#endif // __CPU_O3_CPU_HH__ 761