cpu.hh revision 5737:f43dbc09fad3
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/types.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "config/use_checker.hh" 46#include "cpu/activity.hh" 47#include "cpu/base.hh" 48#include "cpu/simple_thread.hh" 49#include "cpu/o3/comm.hh" 50#include "cpu/o3/cpu_policy.hh" 51#include "cpu/o3/scoreboard.hh" 52#include "cpu/o3/thread_state.hh" 53//#include "cpu/o3/thread_context.hh" 54#include "sim/process.hh" 55 56#include "params/DerivO3CPU.hh" 57 58template <class> 59class Checker; 60class ThreadContext; 61template <class> 62class O3ThreadContext; 63 64class Checkpoint; 65class MemObject; 66class Process; 67 68class BaseCPUParams; 69 70class BaseO3CPU : public BaseCPU 71{ 72 //Stuff that's pretty ISA independent will go here. 73 public: 74 BaseO3CPU(BaseCPUParams *params); 75 76 void regStats(); 77}; 78 79/** 80 * FullO3CPU class, has each of the stages (fetch through commit) 81 * within it, as well as all of the time buffers between stages. The 82 * tick() function for the CPU is defined here. 83 */ 84template <class Impl> 85class FullO3CPU : public BaseO3CPU 86{ 87 public: 88 // Typedefs from the Impl here. 89 typedef typename Impl::CPUPol CPUPolicy; 90 typedef typename Impl::DynInstPtr DynInstPtr; 91 typedef typename Impl::O3CPU O3CPU; 92 93 typedef O3ThreadState<Impl> ImplState; 94 typedef O3ThreadState<Impl> Thread; 95 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 friend class O3ThreadContext<Impl>; 99 100 public: 101 enum Status { 102 Running, 103 Idle, 104 Halted, 105 Blocked, 106 SwitchedOut 107 }; 108 109 TheISA::ITB * itb; 110 TheISA::DTB * dtb; 111 112 /** Overall CPU status. */ 113 Status _status; 114 115 /** Per-thread status in CPU, used for SMT. */ 116 Status _threadStatus[Impl::MaxThreads]; 117 118 private: 119 class TickEvent : public Event 120 { 121 private: 122 /** Pointer to the CPU. */ 123 FullO3CPU<Impl> *cpu; 124 125 public: 126 /** Constructs a tick event. */ 127 TickEvent(FullO3CPU<Impl> *c); 128 129 /** Processes a tick event, calling tick() on the CPU. */ 130 void process(); 131 /** Returns the description of the tick event. */ 132 const char *description() const; 133 }; 134 135 /** The tick event used for scheduling CPU ticks. */ 136 TickEvent tickEvent; 137 138 /** Schedule tick event, regardless of its current state. */ 139 void scheduleTickEvent(int delay) 140 { 141 if (tickEvent.squashed()) 142 reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 143 else if (!tickEvent.scheduled()) 144 schedule(tickEvent, nextCycle(curTick + ticks(delay))); 145 } 146 147 /** Unschedule tick event, regardless of its current state. */ 148 void unscheduleTickEvent() 149 { 150 if (tickEvent.scheduled()) 151 tickEvent.squash(); 152 } 153 154 class ActivateThreadEvent : public Event 155 { 156 private: 157 /** Number of Thread to Activate */ 158 int tid; 159 160 /** Pointer to the CPU. */ 161 FullO3CPU<Impl> *cpu; 162 163 public: 164 /** Constructs the event. */ 165 ActivateThreadEvent(); 166 167 /** Initialize Event */ 168 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 169 170 /** Processes the event, calling activateThread() on the CPU. */ 171 void process(); 172 173 /** Returns the description of the event. */ 174 const char *description() const; 175 }; 176 177 /** Schedule thread to activate , regardless of its current state. */ 178 void scheduleActivateThreadEvent(int tid, int delay) 179 { 180 // Schedule thread to activate, regardless of its current state. 181 if (activateThreadEvent[tid].squashed()) 182 reschedule(activateThreadEvent[tid], 183 nextCycle(curTick + ticks(delay))); 184 else if (!activateThreadEvent[tid].scheduled()) 185 schedule(activateThreadEvent[tid], 186 nextCycle(curTick + ticks(delay))); 187 } 188 189 /** Unschedule actiavte thread event, regardless of its current state. */ 190 void unscheduleActivateThreadEvent(int tid) 191 { 192 if (activateThreadEvent[tid].scheduled()) 193 activateThreadEvent[tid].squash(); 194 } 195 196#if !FULL_SYSTEM 197 TheISA::IntReg getSyscallArg(int i, int tid); 198 199 /** Used to shift args for indirect syscall. */ 200 void setSyscallArg(int i, TheISA::IntReg val, int tid); 201#endif 202 203 /** The tick event used for scheduling CPU ticks. */ 204 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 205 206 class DeallocateContextEvent : public Event 207 { 208 private: 209 /** Number of Thread to deactivate */ 210 int tid; 211 212 /** Should the thread be removed from the CPU? */ 213 bool remove; 214 215 /** Pointer to the CPU. */ 216 FullO3CPU<Impl> *cpu; 217 218 public: 219 /** Constructs the event. */ 220 DeallocateContextEvent(); 221 222 /** Initialize Event */ 223 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 224 225 /** Processes the event, calling activateThread() on the CPU. */ 226 void process(); 227 228 /** Sets whether the thread should also be removed from the CPU. */ 229 void setRemove(bool _remove) { remove = _remove; } 230 231 /** Returns the description of the event. */ 232 const char *description() const; 233 }; 234 235 /** Schedule cpu to deallocate thread context.*/ 236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 237 { 238 // Schedule thread to activate, regardless of its current state. 239 if (deallocateContextEvent[tid].squashed()) 240 reschedule(deallocateContextEvent[tid], 241 nextCycle(curTick + ticks(delay))); 242 else if (!deallocateContextEvent[tid].scheduled()) 243 schedule(deallocateContextEvent[tid], 244 nextCycle(curTick + ticks(delay))); 245 } 246 247 /** Unschedule thread deallocation in CPU */ 248 void unscheduleDeallocateContextEvent(int tid) 249 { 250 if (deallocateContextEvent[tid].scheduled()) 251 deallocateContextEvent[tid].squash(); 252 } 253 254 /** The tick event used for scheduling CPU ticks. */ 255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 256 257 public: 258 /** Constructs a CPU with the given parameters. */ 259 FullO3CPU(DerivO3CPUParams *params); 260 /** Destructor. */ 261 ~FullO3CPU(); 262 263 /** Registers statistics. */ 264 void regStats(); 265 266 void demapPage(Addr vaddr, uint64_t asn) 267 { 268 this->itb->demapPage(vaddr, asn); 269 this->dtb->demapPage(vaddr, asn); 270 } 271 272 void demapInstPage(Addr vaddr, uint64_t asn) 273 { 274 this->itb->demapPage(vaddr, asn); 275 } 276 277 void demapDataPage(Addr vaddr, uint64_t asn) 278 { 279 this->dtb->demapPage(vaddr, asn); 280 } 281 282 /** Translates instruction requestion. */ 283 Fault translateInstReq(RequestPtr &req, Thread *thread) 284 { 285 return this->itb->translate(req, thread->getTC()); 286 } 287 288 /** Translates data read request. */ 289 Fault translateDataReadReq(RequestPtr &req, Thread *thread) 290 { 291 return this->dtb->translate(req, thread->getTC(), false); 292 } 293 294 /** Translates data write request. */ 295 Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 296 { 297 return this->dtb->translate(req, thread->getTC(), true); 298 } 299 300 /** Returns a specific port. */ 301 Port *getPort(const std::string &if_name, int idx); 302 303 /** Ticks CPU, calling tick() on each stage, and checking the overall 304 * activity to see if the CPU should deschedule itself. 305 */ 306 void tick(); 307 308 /** Initialize the CPU */ 309 void init(); 310 311 /** Returns the Number of Active Threads in the CPU */ 312 int numActiveThreads() 313 { return activeThreads.size(); } 314 315 /** Add Thread to Active Threads List */ 316 void activateThread(unsigned tid); 317 318 /** Remove Thread from Active Threads List */ 319 void deactivateThread(unsigned tid); 320 321 /** Setup CPU to insert a thread's context */ 322 void insertThread(unsigned tid); 323 324 /** Remove all of a thread's context from CPU */ 325 void removeThread(unsigned tid); 326 327 /** Count the Total Instructions Committed in the CPU. */ 328 virtual Counter totalInstructions() const 329 { 330 Counter total(0); 331 332 for (int i=0; i < thread.size(); i++) 333 total += thread[i]->numInst; 334 335 return total; 336 } 337 338 /** Add Thread to Active Threads List. */ 339 void activateContext(int tid, int delay); 340 341 /** Remove Thread from Active Threads List */ 342 void suspendContext(int tid); 343 344 /** Remove Thread from Active Threads List && 345 * Possibly Remove Thread Context from CPU. 346 */ 347 bool deallocateContext(int tid, bool remove, int delay = 1); 348 349 /** Remove Thread from Active Threads List && 350 * Remove Thread Context from CPU. 351 */ 352 void haltContext(int tid); 353 354 /** Activate a Thread When CPU Resources are Available. */ 355 void activateWhenReady(int tid); 356 357 /** Add or Remove a Thread Context in the CPU. */ 358 void doContextSwitch(); 359 360 /** Update The Order In Which We Process Threads. */ 361 void updateThreadPriority(); 362 363 /** Serialize state. */ 364 virtual void serialize(std::ostream &os); 365 366 /** Unserialize from a checkpoint. */ 367 virtual void unserialize(Checkpoint *cp, const std::string §ion); 368 369 public: 370#if !FULL_SYSTEM 371 /** Executes a syscall. 372 * @todo: Determine if this needs to be virtual. 373 */ 374 void syscall(int64_t callnum, int tid); 375 376 /** Sets the return value of a syscall. */ 377 void setSyscallReturn(SyscallReturn return_value, int tid); 378 379#endif 380 381 /** Starts draining the CPU's pipeline of all instructions in 382 * order to stop all memory accesses. */ 383 virtual unsigned int drain(Event *drain_event); 384 385 /** Resumes execution after a drain. */ 386 virtual void resume(); 387 388 /** Signals to this CPU that a stage has completed switching out. */ 389 void signalDrained(); 390 391 /** Switches out this CPU. */ 392 virtual void switchOut(); 393 394 /** Takes over from another CPU. */ 395 virtual void takeOverFrom(BaseCPU *oldCPU); 396 397 /** Get the current instruction sequence number, and increment it. */ 398 InstSeqNum getAndIncrementInstSeq() 399 { return globalSeqNum++; } 400 401 /** Traps to handle given fault. */ 402 void trap(Fault fault, unsigned tid); 403 404#if FULL_SYSTEM 405 /** Posts an interrupt. */ 406 void postInterrupt(int int_num, int index); 407 408 /** HW return from error interrupt. */ 409 Fault hwrei(unsigned tid); 410 411 bool simPalCheck(int palFunc, unsigned tid); 412 413 /** Returns the Fault for any valid interrupt. */ 414 Fault getInterrupts(); 415 416 /** Processes any an interrupt fault. */ 417 void processInterrupts(Fault interrupt); 418 419 /** Halts the CPU. */ 420 void halt() { panic("Halt not implemented!\n"); } 421 422 /** Update the Virt and Phys ports of all ThreadContexts to 423 * reflect change in memory connections. */ 424 void updateMemPorts(); 425 426 /** Check if this address is a valid instruction address. */ 427 bool validInstAddr(Addr addr) { return true; } 428 429 /** Check if this address is a valid data address. */ 430 bool validDataAddr(Addr addr) { return true; } 431 432 /** Get instruction asid. */ 433 int getInstAsid(unsigned tid) 434 { return regFile.miscRegs[tid].getInstAsid(); } 435 436 /** Get data asid. */ 437 int getDataAsid(unsigned tid) 438 { return regFile.miscRegs[tid].getDataAsid(); } 439#else 440 /** Get instruction asid. */ 441 int getInstAsid(unsigned tid) 442 { return thread[tid]->getInstAsid(); } 443 444 /** Get data asid. */ 445 int getDataAsid(unsigned tid) 446 { return thread[tid]->getDataAsid(); } 447 448#endif 449 450 /** Register accessors. Index refers to the physical register index. */ 451 452 /** Reads a miscellaneous register. */ 453 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); 454 455 /** Reads a misc. register, including any side effects the read 456 * might have as defined by the architecture. 457 */ 458 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); 459 460 /** Sets a miscellaneous register. */ 461 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); 462 463 /** Sets a misc. register, including any side effects the write 464 * might have as defined by the architecture. 465 */ 466 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 467 unsigned tid); 468 469 uint64_t readIntReg(int reg_idx); 470 471 TheISA::FloatReg readFloatReg(int reg_idx); 472 473 TheISA::FloatReg readFloatReg(int reg_idx, int width); 474 475 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 476 477 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 478 479 void setIntReg(int reg_idx, uint64_t val); 480 481 void setFloatReg(int reg_idx, TheISA::FloatReg val); 482 483 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 484 485 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 486 487 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 488 489 uint64_t readArchIntReg(int reg_idx, unsigned tid); 490 491 float readArchFloatRegSingle(int reg_idx, unsigned tid); 492 493 double readArchFloatRegDouble(int reg_idx, unsigned tid); 494 495 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 496 497 /** Architectural register accessors. Looks up in the commit 498 * rename table to obtain the true physical index of the 499 * architected register first, then accesses that physical 500 * register. 501 */ 502 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 503 504 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 505 506 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 507 508 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 509 510 /** Reads the commit PC of a specific thread. */ 511 Addr readPC(unsigned tid); 512 513 /** Sets the commit PC of a specific thread. */ 514 void setPC(Addr new_PC, unsigned tid); 515 516 /** Reads the commit micro PC of a specific thread. */ 517 Addr readMicroPC(unsigned tid); 518 519 /** Sets the commmit micro PC of a specific thread. */ 520 void setMicroPC(Addr new_microPC, unsigned tid); 521 522 /** Reads the next PC of a specific thread. */ 523 Addr readNextPC(unsigned tid); 524 525 /** Sets the next PC of a specific thread. */ 526 void setNextPC(Addr val, unsigned tid); 527 528 /** Reads the next NPC of a specific thread. */ 529 Addr readNextNPC(unsigned tid); 530 531 /** Sets the next NPC of a specific thread. */ 532 void setNextNPC(Addr val, unsigned tid); 533 534 /** Reads the commit next micro PC of a specific thread. */ 535 Addr readNextMicroPC(unsigned tid); 536 537 /** Sets the commit next micro PC of a specific thread. */ 538 void setNextMicroPC(Addr val, unsigned tid); 539 540 /** Initiates a squash of all in-flight instructions for a given 541 * thread. The source of the squash is an external update of 542 * state through the TC. 543 */ 544 void squashFromTC(unsigned tid); 545 546 /** Function to add instruction onto the head of the list of the 547 * instructions. Used when new instructions are fetched. 548 */ 549 ListIt addInst(DynInstPtr &inst); 550 551 /** Function to tell the CPU that an instruction has completed. */ 552 void instDone(unsigned tid); 553 554 /** Add Instructions to the CPU Remove List*/ 555 void addToRemoveList(DynInstPtr &inst); 556 557 /** Remove an instruction from the front end of the list. There's 558 * no restriction on location of the instruction. 559 */ 560 void removeFrontInst(DynInstPtr &inst); 561 562 /** Remove all instructions that are not currently in the ROB. 563 * There's also an option to not squash delay slot instructions.*/ 564 void removeInstsNotInROB(unsigned tid); 565 566 /** Remove all instructions younger than the given sequence number. */ 567 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 568 569 /** Removes the instruction pointed to by the iterator. */ 570 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 571 572 /** Cleans up all instructions on the remove list. */ 573 void cleanUpRemovedInsts(); 574 575 /** Debug function to print all instructions on the list. */ 576 void dumpInsts(); 577 578 public: 579#ifndef NDEBUG 580 /** Count of total number of dynamic instructions in flight. */ 581 int instcount; 582#endif 583 584 /** List of all the instructions in flight. */ 585 std::list<DynInstPtr> instList; 586 587 /** List of all the instructions that will be removed at the end of this 588 * cycle. 589 */ 590 std::queue<ListIt> removeList; 591 592#ifdef DEBUG 593 /** Debug structure to keep track of the sequence numbers still in 594 * flight. 595 */ 596 std::set<InstSeqNum> snList; 597#endif 598 599 /** Records if instructions need to be removed this cycle due to 600 * being retired or squashed. 601 */ 602 bool removeInstsThisCycle; 603 604 protected: 605 /** The fetch stage. */ 606 typename CPUPolicy::Fetch fetch; 607 608 /** The decode stage. */ 609 typename CPUPolicy::Decode decode; 610 611 /** The dispatch stage. */ 612 typename CPUPolicy::Rename rename; 613 614 /** The issue/execute/writeback stages. */ 615 typename CPUPolicy::IEW iew; 616 617 /** The commit stage. */ 618 typename CPUPolicy::Commit commit; 619 620 /** The register file. */ 621 typename CPUPolicy::RegFile regFile; 622 623 /** The free list. */ 624 typename CPUPolicy::FreeList freeList; 625 626 /** The rename map. */ 627 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 628 629 /** The commit rename map. */ 630 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 631 632 /** The re-order buffer. */ 633 typename CPUPolicy::ROB rob; 634 635 /** Active Threads List */ 636 std::list<unsigned> activeThreads; 637 638 /** Integer Register Scoreboard */ 639 Scoreboard scoreboard; 640 641 public: 642 /** Enum to give each stage a specific index, so when calling 643 * activateStage() or deactivateStage(), they can specify which stage 644 * is being activated/deactivated. 645 */ 646 enum StageIdx { 647 FetchIdx, 648 DecodeIdx, 649 RenameIdx, 650 IEWIdx, 651 CommitIdx, 652 NumStages }; 653 654 /** Typedefs from the Impl to get the structs that each of the 655 * time buffers should use. 656 */ 657 typedef typename CPUPolicy::TimeStruct TimeStruct; 658 659 typedef typename CPUPolicy::FetchStruct FetchStruct; 660 661 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 662 663 typedef typename CPUPolicy::RenameStruct RenameStruct; 664 665 typedef typename CPUPolicy::IEWStruct IEWStruct; 666 667 /** The main time buffer to do backwards communication. */ 668 TimeBuffer<TimeStruct> timeBuffer; 669 670 /** The fetch stage's instruction queue. */ 671 TimeBuffer<FetchStruct> fetchQueue; 672 673 /** The decode stage's instruction queue. */ 674 TimeBuffer<DecodeStruct> decodeQueue; 675 676 /** The rename stage's instruction queue. */ 677 TimeBuffer<RenameStruct> renameQueue; 678 679 /** The IEW stage's instruction queue. */ 680 TimeBuffer<IEWStruct> iewQueue; 681 682 private: 683 /** The activity recorder; used to tell if the CPU has any 684 * activity remaining or if it can go to idle and deschedule 685 * itself. 686 */ 687 ActivityRecorder activityRec; 688 689 public: 690 /** Records that there was time buffer activity this cycle. */ 691 void activityThisCycle() { activityRec.activity(); } 692 693 /** Changes a stage's status to active within the activity recorder. */ 694 void activateStage(const StageIdx idx) 695 { activityRec.activateStage(idx); } 696 697 /** Changes a stage's status to inactive within the activity recorder. */ 698 void deactivateStage(const StageIdx idx) 699 { activityRec.deactivateStage(idx); } 700 701 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 702 void wakeCPU(); 703 704 /** Gets a free thread id. Use if thread ids change across system. */ 705 int getFreeTid(); 706 707 public: 708 /** Returns a pointer to a thread context. */ 709 ThreadContext *tcBase(unsigned tid) 710 { 711 return thread[tid]->getTC(); 712 } 713 714 /** The global sequence number counter. */ 715 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 716 717#if USE_CHECKER 718 /** Pointer to the checker, which can dynamically verify 719 * instruction results at run time. This can be set to NULL if it 720 * is not being used. 721 */ 722 Checker<DynInstPtr> *checker; 723#endif 724 725#if FULL_SYSTEM 726 /** Pointer to the system. */ 727 System *system; 728 729 /** Pointer to physical memory. */ 730 PhysicalMemory *physmem; 731#endif 732 733 /** Event to call process() on once draining has completed. */ 734 Event *drainEvent; 735 736 /** Counter of how many stages have completed draining. */ 737 int drainCount; 738 739 /** Pointers to all of the threads in the CPU. */ 740 std::vector<Thread *> thread; 741 742 /** Whether or not the CPU should defer its registration. */ 743 bool deferRegistration; 744 745 /** Is there a context switch pending? */ 746 bool contextSwitch; 747 748 /** Threads Scheduled to Enter CPU */ 749 std::list<int> cpuWaitList; 750 751 /** The cycle that the CPU was last running, used for statistics. */ 752 Tick lastRunningCycle; 753 754 /** The cycle that the CPU was last activated by a new thread*/ 755 Tick lastActivatedCycle; 756 757 /** Number of Threads CPU can process */ 758 unsigned numThreads; 759 760 /** Mapping for system thread id to cpu id */ 761 std::map<unsigned,unsigned> threadMap; 762 763 /** Available thread ids in the cpu*/ 764 std::vector<unsigned> tids; 765 766 /** CPU read function, forwards read to LSQ. */ 767 template <class T> 768 Fault read(RequestPtr &req, T &data, int load_idx) 769 { 770 return this->iew.ldstQueue.read(req, data, load_idx); 771 } 772 773 /** CPU write function, forwards write to LSQ. */ 774 template <class T> 775 Fault write(RequestPtr &req, T &data, int store_idx) 776 { 777 return this->iew.ldstQueue.write(req, data, store_idx); 778 } 779 780 Addr lockAddr; 781 782 /** Temporary fix for the lock flag, works in the UP case. */ 783 bool lockFlag; 784 785 /** Stat for total number of times the CPU is descheduled. */ 786 Stats::Scalar<> timesIdled; 787 /** Stat for total number of cycles the CPU spends descheduled. */ 788 Stats::Scalar<> idleCycles; 789 /** Stat for the number of committed instructions per thread. */ 790 Stats::Vector<> committedInsts; 791 /** Stat for the total number of committed instructions. */ 792 Stats::Scalar<> totalCommittedInsts; 793 /** Stat for the CPI per thread. */ 794 Stats::Formula cpi; 795 /** Stat for the total CPI. */ 796 Stats::Formula totalCpi; 797 /** Stat for the IPC per thread. */ 798 Stats::Formula ipc; 799 /** Stat for the total IPC. */ 800 Stats::Formula totalIpc; 801}; 802 803#endif // __CPU_O3_CPU_HH__ 804