cpu.hh revision 4636:afc8da9f526e
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/types.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "cpu/activity.hh" 46#include "cpu/base.hh" 47#include "cpu/simple_thread.hh" 48#include "cpu/o3/comm.hh" 49#include "cpu/o3/cpu_policy.hh" 50#include "cpu/o3/scoreboard.hh" 51#include "cpu/o3/thread_state.hh" 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext; 60 61class Checkpoint; 62class MemObject; 63class Process; 64 65class BaseO3CPU : public BaseCPU 66{ 67 //Stuff that's pretty ISA independent will go here. 68 public: 69 typedef BaseCPU::Params Params; 70 71 BaseO3CPU(Params *params); 72 73 void regStats(); 74 75 /** Sets this CPU's ID. */ 76 void setCpuId(int id) { cpu_id = id; } 77 78 /** Reads this CPU's ID. */ 79 int readCpuId() { return cpu_id; } 80 81 protected: 82 int cpu_id; 83}; 84 85/** 86 * FullO3CPU class, has each of the stages (fetch through commit) 87 * within it, as well as all of the time buffers between stages. The 88 * tick() function for the CPU is defined here. 89 */ 90template <class Impl> 91class FullO3CPU : public BaseO3CPU 92{ 93 public: 94 // Typedefs from the Impl here. 95 typedef typename Impl::CPUPol CPUPolicy; 96 typedef typename Impl::Params Params; 97 typedef typename Impl::DynInstPtr DynInstPtr; 98 typedef typename Impl::O3CPU O3CPU; 99 100 typedef O3ThreadState<Impl> Thread; 101 102 typedef typename std::list<DynInstPtr>::iterator ListIt; 103 104 friend class O3ThreadContext<Impl>; 105 106 public: 107 enum Status { 108 Running, 109 Idle, 110 Halted, 111 Blocked, 112 SwitchedOut 113 }; 114 115#if FULL_SYSTEM 116 TheISA::ITB * itb; 117 TheISA::DTB * dtb; 118#endif 119 120 /** Overall CPU status. */ 121 Status _status; 122 123 /** Per-thread status in CPU, used for SMT. */ 124 Status _threadStatus[Impl::MaxThreads]; 125 126 private: 127 class TickEvent : public Event 128 { 129 private: 130 /** Pointer to the CPU. */ 131 FullO3CPU<Impl> *cpu; 132 133 public: 134 /** Constructs a tick event. */ 135 TickEvent(FullO3CPU<Impl> *c); 136 137 /** Processes a tick event, calling tick() on the CPU. */ 138 void process(); 139 /** Returns the description of the tick event. */ 140 const char *description(); 141 }; 142 143 /** The tick event used for scheduling CPU ticks. */ 144 TickEvent tickEvent; 145 146 /** Schedule tick event, regardless of its current state. */ 147 void scheduleTickEvent(int delay) 148 { 149 if (tickEvent.squashed()) 150 tickEvent.reschedule(nextCycle(curTick + cycles(delay))); 151 else if (!tickEvent.scheduled()) 152 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 153 } 154 155 /** Unschedule tick event, regardless of its current state. */ 156 void unscheduleTickEvent() 157 { 158 if (tickEvent.scheduled()) 159 tickEvent.squash(); 160 } 161 162 class ActivateThreadEvent : public Event 163 { 164 private: 165 /** Number of Thread to Activate */ 166 int tid; 167 168 /** Pointer to the CPU. */ 169 FullO3CPU<Impl> *cpu; 170 171 public: 172 /** Constructs the event. */ 173 ActivateThreadEvent(); 174 175 /** Initialize Event */ 176 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 177 178 /** Processes the event, calling activateThread() on the CPU. */ 179 void process(); 180 181 /** Returns the description of the event. */ 182 const char *description(); 183 }; 184 185 /** Schedule thread to activate , regardless of its current state. */ 186 void scheduleActivateThreadEvent(int tid, int delay) 187 { 188 // Schedule thread to activate, regardless of its current state. 189 if (activateThreadEvent[tid].squashed()) 190 activateThreadEvent[tid]. 191 reschedule(nextCycle(curTick + cycles(delay))); 192 else if (!activateThreadEvent[tid].scheduled()) 193 activateThreadEvent[tid]. 194 schedule(nextCycle(curTick + cycles(delay))); 195 } 196 197 /** Unschedule actiavte thread event, regardless of its current state. */ 198 void unscheduleActivateThreadEvent(int tid) 199 { 200 if (activateThreadEvent[tid].scheduled()) 201 activateThreadEvent[tid].squash(); 202 } 203 204 /** The tick event used for scheduling CPU ticks. */ 205 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 206 207 class DeallocateContextEvent : public Event 208 { 209 private: 210 /** Number of Thread to deactivate */ 211 int tid; 212 213 /** Should the thread be removed from the CPU? */ 214 bool remove; 215 216 /** Pointer to the CPU. */ 217 FullO3CPU<Impl> *cpu; 218 219 public: 220 /** Constructs the event. */ 221 DeallocateContextEvent(); 222 223 /** Initialize Event */ 224 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 225 226 /** Processes the event, calling activateThread() on the CPU. */ 227 void process(); 228 229 /** Sets whether the thread should also be removed from the CPU. */ 230 void setRemove(bool _remove) { remove = _remove; } 231 232 /** Returns the description of the event. */ 233 const char *description(); 234 }; 235 236 /** Schedule cpu to deallocate thread context.*/ 237 void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 238 { 239 // Schedule thread to activate, regardless of its current state. 240 if (deallocateContextEvent[tid].squashed()) 241 deallocateContextEvent[tid]. 242 reschedule(nextCycle(curTick + cycles(delay))); 243 else if (!deallocateContextEvent[tid].scheduled()) 244 deallocateContextEvent[tid]. 245 schedule(nextCycle(curTick + cycles(delay))); 246 } 247 248 /** Unschedule thread deallocation in CPU */ 249 void unscheduleDeallocateContextEvent(int tid) 250 { 251 if (deallocateContextEvent[tid].scheduled()) 252 deallocateContextEvent[tid].squash(); 253 } 254 255 /** The tick event used for scheduling CPU ticks. */ 256 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 257 258 public: 259 /** Constructs a CPU with the given parameters. */ 260 FullO3CPU(O3CPU *o3_cpu, Params *params); 261 /** Destructor. */ 262 ~FullO3CPU(); 263 264 /** Registers statistics. */ 265 void fullCPURegStats(); 266 267 /** Returns a specific port. */ 268 Port *getPort(const std::string &if_name, int idx); 269 270 /** Ticks CPU, calling tick() on each stage, and checking the overall 271 * activity to see if the CPU should deschedule itself. 272 */ 273 void tick(); 274 275 /** Initialize the CPU */ 276 void init(); 277 278 /** Returns the Number of Active Threads in the CPU */ 279 int numActiveThreads() 280 { return activeThreads.size(); } 281 282 /** Add Thread to Active Threads List */ 283 void activateThread(unsigned tid); 284 285 /** Remove Thread from Active Threads List */ 286 void deactivateThread(unsigned tid); 287 288 /** Setup CPU to insert a thread's context */ 289 void insertThread(unsigned tid); 290 291 /** Remove all of a thread's context from CPU */ 292 void removeThread(unsigned tid); 293 294 /** Count the Total Instructions Committed in the CPU. */ 295 virtual Counter totalInstructions() const 296 { 297 Counter total(0); 298 299 for (int i=0; i < thread.size(); i++) 300 total += thread[i]->numInst; 301 302 return total; 303 } 304 305 /** Add Thread to Active Threads List. */ 306 void activateContext(int tid, int delay); 307 308 /** Remove Thread from Active Threads List */ 309 void suspendContext(int tid); 310 311 /** Remove Thread from Active Threads List && 312 * Possibly Remove Thread Context from CPU. 313 */ 314 bool deallocateContext(int tid, bool remove, int delay = 1); 315 316 /** Remove Thread from Active Threads List && 317 * Remove Thread Context from CPU. 318 */ 319 void haltContext(int tid); 320 321 /** Activate a Thread When CPU Resources are Available. */ 322 void activateWhenReady(int tid); 323 324 /** Add or Remove a Thread Context in the CPU. */ 325 void doContextSwitch(); 326 327 /** Update The Order In Which We Process Threads. */ 328 void updateThreadPriority(); 329 330 /** Serialize state. */ 331 virtual void serialize(std::ostream &os); 332 333 /** Unserialize from a checkpoint. */ 334 virtual void unserialize(Checkpoint *cp, const std::string §ion); 335 336 public: 337 /** Executes a syscall on this cycle. 338 * --------------------------------------- 339 * Note: this is a virtual function. CPU-Specific 340 * functionality defined in derived classes 341 */ 342 virtual void syscall(int tid) { panic("Unimplemented!"); } 343 344 /** Starts draining the CPU's pipeline of all instructions in 345 * order to stop all memory accesses. */ 346 virtual unsigned int drain(Event *drain_event); 347 348 /** Resumes execution after a drain. */ 349 virtual void resume(); 350 351 /** Signals to this CPU that a stage has completed switching out. */ 352 void signalDrained(); 353 354 /** Switches out this CPU. */ 355 virtual void switchOut(); 356 357 /** Takes over from another CPU. */ 358 virtual void takeOverFrom(BaseCPU *oldCPU); 359 360 /** Get the current instruction sequence number, and increment it. */ 361 InstSeqNum getAndIncrementInstSeq() 362 { return globalSeqNum++; } 363 364#if FULL_SYSTEM 365 /** Update the Virt and Phys ports of all ThreadContexts to 366 * reflect change in memory connections. */ 367 void updateMemPorts(); 368 369 /** Check if this address is a valid instruction address. */ 370 bool validInstAddr(Addr addr) { return true; } 371 372 /** Check if this address is a valid data address. */ 373 bool validDataAddr(Addr addr) { return true; } 374 375 /** Get instruction asid. */ 376 int getInstAsid(unsigned tid) 377 { return regFile.miscRegs[tid].getInstAsid(); } 378 379 /** Get data asid. */ 380 int getDataAsid(unsigned tid) 381 { return regFile.miscRegs[tid].getDataAsid(); } 382#else 383 /** Get instruction asid. */ 384 int getInstAsid(unsigned tid) 385 { return thread[tid]->getInstAsid(); } 386 387 /** Get data asid. */ 388 int getDataAsid(unsigned tid) 389 { return thread[tid]->getDataAsid(); } 390 391#endif 392 393 /** Register accessors. Index refers to the physical register index. */ 394 uint64_t readIntReg(int reg_idx); 395 396 TheISA::FloatReg readFloatReg(int reg_idx); 397 398 TheISA::FloatReg readFloatReg(int reg_idx, int width); 399 400 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 401 402 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 403 404 void setIntReg(int reg_idx, uint64_t val); 405 406 void setFloatReg(int reg_idx, TheISA::FloatReg val); 407 408 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 409 410 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 411 412 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 413 414 uint64_t readArchIntReg(int reg_idx, unsigned tid); 415 416 float readArchFloatRegSingle(int reg_idx, unsigned tid); 417 418 double readArchFloatRegDouble(int reg_idx, unsigned tid); 419 420 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 421 422 /** Architectural register accessors. Looks up in the commit 423 * rename table to obtain the true physical index of the 424 * architected register first, then accesses that physical 425 * register. 426 */ 427 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 428 429 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 430 431 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 432 433 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 434 435 /** Reads the commit PC of a specific thread. */ 436 Addr readPC(unsigned tid); 437 438 /** Sets the commit PC of a specific thread. */ 439 void setPC(Addr new_PC, unsigned tid); 440 441 /** Reads the commit micro PC of a specific thread. */ 442 Addr readMicroPC(unsigned tid); 443 444 /** Sets the commmit micro PC of a specific thread. */ 445 void setMicroPC(Addr new_microPC, unsigned tid); 446 447 /** Reads the next PC of a specific thread. */ 448 Addr readNextPC(unsigned tid); 449 450 /** Sets the next PC of a specific thread. */ 451 void setNextPC(Addr val, unsigned tid); 452 453 /** Reads the next NPC of a specific thread. */ 454 Addr readNextNPC(unsigned tid); 455 456 /** Sets the next NPC of a specific thread. */ 457 void setNextNPC(Addr val, unsigned tid); 458 459 /** Reads the commit next micro PC of a specific thread. */ 460 Addr readNextMicroPC(unsigned tid); 461 462 /** Sets the commit next micro PC of a specific thread. */ 463 void setNextMicroPC(Addr val, unsigned tid); 464 465 /** Function to add instruction onto the head of the list of the 466 * instructions. Used when new instructions are fetched. 467 */ 468 ListIt addInst(DynInstPtr &inst); 469 470 /** Function to tell the CPU that an instruction has completed. */ 471 void instDone(unsigned tid); 472 473 /** Add Instructions to the CPU Remove List*/ 474 void addToRemoveList(DynInstPtr &inst); 475 476 /** Remove an instruction from the front end of the list. There's 477 * no restriction on location of the instruction. 478 */ 479 void removeFrontInst(DynInstPtr &inst); 480 481 /** Remove all instructions that are not currently in the ROB. 482 * There's also an option to not squash delay slot instructions.*/ 483 void removeInstsNotInROB(unsigned tid); 484 485 /** Remove all instructions younger than the given sequence number. */ 486 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 487 488 /** Removes the instruction pointed to by the iterator. */ 489 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 490 491 /** Cleans up all instructions on the remove list. */ 492 void cleanUpRemovedInsts(); 493 494 /** Debug function to print all instructions on the list. */ 495 void dumpInsts(); 496 497 public: 498 /** List of all the instructions in flight. */ 499 std::list<DynInstPtr> instList; 500 501 /** List of all the instructions that will be removed at the end of this 502 * cycle. 503 */ 504 std::queue<ListIt> removeList; 505 506#ifdef DEBUG 507 /** Debug structure to keep track of the sequence numbers still in 508 * flight. 509 */ 510 std::set<InstSeqNum> snList; 511#endif 512 513 /** Records if instructions need to be removed this cycle due to 514 * being retired or squashed. 515 */ 516 bool removeInstsThisCycle; 517 518 protected: 519 /** The fetch stage. */ 520 typename CPUPolicy::Fetch fetch; 521 522 /** The decode stage. */ 523 typename CPUPolicy::Decode decode; 524 525 /** The dispatch stage. */ 526 typename CPUPolicy::Rename rename; 527 528 /** The issue/execute/writeback stages. */ 529 typename CPUPolicy::IEW iew; 530 531 /** The commit stage. */ 532 typename CPUPolicy::Commit commit; 533 534 /** The register file. */ 535 typename CPUPolicy::RegFile regFile; 536 537 /** The free list. */ 538 typename CPUPolicy::FreeList freeList; 539 540 /** The rename map. */ 541 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 542 543 /** The commit rename map. */ 544 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 545 546 /** The re-order buffer. */ 547 typename CPUPolicy::ROB rob; 548 549 /** Active Threads List */ 550 std::list<unsigned> activeThreads; 551 552 /** Integer Register Scoreboard */ 553 Scoreboard scoreboard; 554 555 public: 556 /** Enum to give each stage a specific index, so when calling 557 * activateStage() or deactivateStage(), they can specify which stage 558 * is being activated/deactivated. 559 */ 560 enum StageIdx { 561 FetchIdx, 562 DecodeIdx, 563 RenameIdx, 564 IEWIdx, 565 CommitIdx, 566 NumStages }; 567 568 /** Typedefs from the Impl to get the structs that each of the 569 * time buffers should use. 570 */ 571 typedef typename CPUPolicy::TimeStruct TimeStruct; 572 573 typedef typename CPUPolicy::FetchStruct FetchStruct; 574 575 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 576 577 typedef typename CPUPolicy::RenameStruct RenameStruct; 578 579 typedef typename CPUPolicy::IEWStruct IEWStruct; 580 581 /** The main time buffer to do backwards communication. */ 582 TimeBuffer<TimeStruct> timeBuffer; 583 584 /** The fetch stage's instruction queue. */ 585 TimeBuffer<FetchStruct> fetchQueue; 586 587 /** The decode stage's instruction queue. */ 588 TimeBuffer<DecodeStruct> decodeQueue; 589 590 /** The rename stage's instruction queue. */ 591 TimeBuffer<RenameStruct> renameQueue; 592 593 /** The IEW stage's instruction queue. */ 594 TimeBuffer<IEWStruct> iewQueue; 595 596 private: 597 /** The activity recorder; used to tell if the CPU has any 598 * activity remaining or if it can go to idle and deschedule 599 * itself. 600 */ 601 ActivityRecorder activityRec; 602 603 public: 604 /** Records that there was time buffer activity this cycle. */ 605 void activityThisCycle() { activityRec.activity(); } 606 607 /** Changes a stage's status to active within the activity recorder. */ 608 void activateStage(const StageIdx idx) 609 { activityRec.activateStage(idx); } 610 611 /** Changes a stage's status to inactive within the activity recorder. */ 612 void deactivateStage(const StageIdx idx) 613 { activityRec.deactivateStage(idx); } 614 615 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 616 void wakeCPU(); 617 618 /** Gets a free thread id. Use if thread ids change across system. */ 619 int getFreeTid(); 620 621 public: 622 /** Returns a pointer to a thread context. */ 623 ThreadContext *tcBase(unsigned tid) 624 { 625 return thread[tid]->getTC(); 626 } 627 628 /** The global sequence number counter. */ 629 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 630 631 /** Pointer to the checker, which can dynamically verify 632 * instruction results at run time. This can be set to NULL if it 633 * is not being used. 634 */ 635 Checker<DynInstPtr> *checker; 636 637#if FULL_SYSTEM 638 /** Pointer to the system. */ 639 System *system; 640 641 /** Pointer to physical memory. */ 642 PhysicalMemory *physmem; 643#endif 644 645 /** Event to call process() on once draining has completed. */ 646 Event *drainEvent; 647 648 /** Counter of how many stages have completed draining. */ 649 int drainCount; 650 651 /** Pointers to all of the threads in the CPU. */ 652 std::vector<Thread *> thread; 653 654 /** Whether or not the CPU should defer its registration. */ 655 bool deferRegistration; 656 657 /** Is there a context switch pending? */ 658 bool contextSwitch; 659 660 /** Threads Scheduled to Enter CPU */ 661 std::list<int> cpuWaitList; 662 663 /** The cycle that the CPU was last running, used for statistics. */ 664 Tick lastRunningCycle; 665 666 /** The cycle that the CPU was last activated by a new thread*/ 667 Tick lastActivatedCycle; 668 669 /** Number of Threads CPU can process */ 670 unsigned numThreads; 671 672 /** Mapping for system thread id to cpu id */ 673 std::map<unsigned,unsigned> threadMap; 674 675 /** Available thread ids in the cpu*/ 676 std::vector<unsigned> tids; 677 678 /** Stat for total number of times the CPU is descheduled. */ 679 Stats::Scalar<> timesIdled; 680 /** Stat for total number of cycles the CPU spends descheduled. */ 681 Stats::Scalar<> idleCycles; 682 /** Stat for the number of committed instructions per thread. */ 683 Stats::Vector<> committedInsts; 684 /** Stat for the total number of committed instructions. */ 685 Stats::Scalar<> totalCommittedInsts; 686 /** Stat for the CPI per thread. */ 687 Stats::Formula cpi; 688 /** Stat for the total CPI. */ 689 Stats::Formula totalCpi; 690 /** Stat for the IPC per thread. */ 691 Stats::Formula ipc; 692 /** Stat for the total IPC. */ 693 Stats::Formula totalIpc; 694}; 695 696#endif // __CPU_O3_CPU_HH__ 697