cpu.hh revision 4030:4046b2213995
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/types.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "cpu/activity.hh" 46#include "cpu/base.hh" 47#include "cpu/simple_thread.hh" 48#include "cpu/o3/comm.hh" 49#include "cpu/o3/cpu_policy.hh" 50#include "cpu/o3/scoreboard.hh" 51#include "cpu/o3/thread_state.hh" 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext; 60 61class Checkpoint; 62class MemObject; 63class Process; 64 65class BaseO3CPU : public BaseCPU 66{ 67 //Stuff that's pretty ISA independent will go here. 68 public: 69 typedef BaseCPU::Params Params; 70 71 BaseO3CPU(Params *params); 72 73 void regStats(); 74 75 /** Sets this CPU's ID. */ 76 void setCpuId(int id) { cpu_id = id; } 77 78 /** Reads this CPU's ID. */ 79 int readCpuId() { return cpu_id; } 80 81 protected: 82 int cpu_id; 83}; 84 85/** 86 * FullO3CPU class, has each of the stages (fetch through commit) 87 * within it, as well as all of the time buffers between stages. The 88 * tick() function for the CPU is defined here. 89 */ 90template <class Impl> 91class FullO3CPU : public BaseO3CPU 92{ 93 public: 94 // Typedefs from the Impl here. 95 typedef typename Impl::CPUPol CPUPolicy; 96 typedef typename Impl::Params Params; 97 typedef typename Impl::DynInstPtr DynInstPtr; 98 99 typedef O3ThreadState<Impl> Thread; 100 101 typedef typename std::list<DynInstPtr>::iterator ListIt; 102 103 friend class O3ThreadContext<Impl>; 104 105 public: 106 enum Status { 107 Running, 108 Idle, 109 Halted, 110 Blocked, 111 SwitchedOut 112 }; 113 114#if FULL_SYSTEM 115 TheISA::ITB * itb; 116 TheISA::DTB * dtb; 117#endif 118 119 /** Overall CPU status. */ 120 Status _status; 121 122 /** Per-thread status in CPU, used for SMT. */ 123 Status _threadStatus[Impl::MaxThreads]; 124 125 private: 126 class TickEvent : public Event 127 { 128 private: 129 /** Pointer to the CPU. */ 130 FullO3CPU<Impl> *cpu; 131 132 public: 133 /** Constructs a tick event. */ 134 TickEvent(FullO3CPU<Impl> *c); 135 136 /** Processes a tick event, calling tick() on the CPU. */ 137 void process(); 138 /** Returns the description of the tick event. */ 139 const char *description(); 140 }; 141 142 /** The tick event used for scheduling CPU ticks. */ 143 TickEvent tickEvent; 144 145 /** Schedule tick event, regardless of its current state. */ 146 void scheduleTickEvent(int delay) 147 { 148 if (tickEvent.squashed()) 149 tickEvent.reschedule(nextCycle(curTick + cycles(delay))); 150 else if (!tickEvent.scheduled()) 151 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 152 } 153 154 /** Unschedule tick event, regardless of its current state. */ 155 void unscheduleTickEvent() 156 { 157 if (tickEvent.scheduled()) 158 tickEvent.squash(); 159 } 160 161 class ActivateThreadEvent : public Event 162 { 163 private: 164 /** Number of Thread to Activate */ 165 int tid; 166 167 /** Pointer to the CPU. */ 168 FullO3CPU<Impl> *cpu; 169 170 public: 171 /** Constructs the event. */ 172 ActivateThreadEvent(); 173 174 /** Initialize Event */ 175 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 176 177 /** Processes the event, calling activateThread() on the CPU. */ 178 void process(); 179 180 /** Returns the description of the event. */ 181 const char *description(); 182 }; 183 184 /** Schedule thread to activate , regardless of its current state. */ 185 void scheduleActivateThreadEvent(int tid, int delay) 186 { 187 // Schedule thread to activate, regardless of its current state. 188 if (activateThreadEvent[tid].squashed()) 189 activateThreadEvent[tid]. 190 reschedule(nextCycle(curTick + cycles(delay))); 191 else if (!activateThreadEvent[tid].scheduled()) 192 activateThreadEvent[tid]. 193 schedule(nextCycle(curTick + cycles(delay))); 194 } 195 196 /** Unschedule actiavte thread event, regardless of its current state. */ 197 void unscheduleActivateThreadEvent(int tid) 198 { 199 if (activateThreadEvent[tid].scheduled()) 200 activateThreadEvent[tid].squash(); 201 } 202 203 /** The tick event used for scheduling CPU ticks. */ 204 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 205 206 class DeallocateContextEvent : public Event 207 { 208 private: 209 /** Number of Thread to deactivate */ 210 int tid; 211 212 /** Should the thread be removed from the CPU? */ 213 bool remove; 214 215 /** Pointer to the CPU. */ 216 FullO3CPU<Impl> *cpu; 217 218 public: 219 /** Constructs the event. */ 220 DeallocateContextEvent(); 221 222 /** Initialize Event */ 223 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 224 225 /** Processes the event, calling activateThread() on the CPU. */ 226 void process(); 227 228 /** Sets whether the thread should also be removed from the CPU. */ 229 void setRemove(bool _remove) { remove = _remove; } 230 231 /** Returns the description of the event. */ 232 const char *description(); 233 }; 234 235 /** Schedule cpu to deallocate thread context.*/ 236 void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 237 { 238 // Schedule thread to activate, regardless of its current state. 239 if (deallocateContextEvent[tid].squashed()) 240 deallocateContextEvent[tid]. 241 reschedule(nextCycle(curTick + cycles(delay))); 242 else if (!deallocateContextEvent[tid].scheduled()) 243 deallocateContextEvent[tid]. 244 schedule(nextCycle(curTick + cycles(delay))); 245 } 246 247 /** Unschedule thread deallocation in CPU */ 248 void unscheduleDeallocateContextEvent(int tid) 249 { 250 if (deallocateContextEvent[tid].scheduled()) 251 deallocateContextEvent[tid].squash(); 252 } 253 254 /** The tick event used for scheduling CPU ticks. */ 255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 256 257 public: 258 /** Constructs a CPU with the given parameters. */ 259 FullO3CPU(Params *params); 260 /** Destructor. */ 261 ~FullO3CPU(); 262 263 /** Registers statistics. */ 264 void fullCPURegStats(); 265 266 /** Returns a specific port. */ 267 Port *getPort(const std::string &if_name, int idx); 268 269 /** Ticks CPU, calling tick() on each stage, and checking the overall 270 * activity to see if the CPU should deschedule itself. 271 */ 272 void tick(); 273 274 /** Initialize the CPU */ 275 void init(); 276 277 /** Returns the Number of Active Threads in the CPU */ 278 int numActiveThreads() 279 { return activeThreads.size(); } 280 281 /** Add Thread to Active Threads List */ 282 void activateThread(unsigned tid); 283 284 /** Remove Thread from Active Threads List */ 285 void deactivateThread(unsigned tid); 286 287 /** Setup CPU to insert a thread's context */ 288 void insertThread(unsigned tid); 289 290 /** Remove all of a thread's context from CPU */ 291 void removeThread(unsigned tid); 292 293 /** Count the Total Instructions Committed in the CPU. */ 294 virtual Counter totalInstructions() const 295 { 296 Counter total(0); 297 298 for (int i=0; i < thread.size(); i++) 299 total += thread[i]->numInst; 300 301 return total; 302 } 303 304 /** Add Thread to Active Threads List. */ 305 void activateContext(int tid, int delay); 306 307 /** Remove Thread from Active Threads List */ 308 void suspendContext(int tid); 309 310 /** Remove Thread from Active Threads List && 311 * Possibly Remove Thread Context from CPU. 312 */ 313 bool deallocateContext(int tid, bool remove, int delay = 1); 314 315 /** Remove Thread from Active Threads List && 316 * Remove Thread Context from CPU. 317 */ 318 void haltContext(int tid); 319 320 /** Activate a Thread When CPU Resources are Available. */ 321 void activateWhenReady(int tid); 322 323 /** Add or Remove a Thread Context in the CPU. */ 324 void doContextSwitch(); 325 326 /** Update The Order In Which We Process Threads. */ 327 void updateThreadPriority(); 328 329 /** Serialize state. */ 330 virtual void serialize(std::ostream &os); 331 332 /** Unserialize from a checkpoint. */ 333 virtual void unserialize(Checkpoint *cp, const std::string §ion); 334 335 public: 336 /** Executes a syscall on this cycle. 337 * --------------------------------------- 338 * Note: this is a virtual function. CPU-Specific 339 * functionality defined in derived classes 340 */ 341 virtual void syscall(int tid) { panic("Unimplemented!"); } 342 343 /** Starts draining the CPU's pipeline of all instructions in 344 * order to stop all memory accesses. */ 345 virtual unsigned int drain(Event *drain_event); 346 347 /** Resumes execution after a drain. */ 348 virtual void resume(); 349 350 /** Signals to this CPU that a stage has completed switching out. */ 351 void signalDrained(); 352 353 /** Switches out this CPU. */ 354 virtual void switchOut(); 355 356 /** Takes over from another CPU. */ 357 virtual void takeOverFrom(BaseCPU *oldCPU); 358 359 /** Get the current instruction sequence number, and increment it. */ 360 InstSeqNum getAndIncrementInstSeq() 361 { return globalSeqNum++; } 362 363#if FULL_SYSTEM 364 /** Check if this address is a valid instruction address. */ 365 bool validInstAddr(Addr addr) { return true; } 366 367 /** Check if this address is a valid data address. */ 368 bool validDataAddr(Addr addr) { return true; } 369 370 /** Get instruction asid. */ 371 int getInstAsid(unsigned tid) 372 { return regFile.miscRegs[tid].getInstAsid(); } 373 374 /** Get data asid. */ 375 int getDataAsid(unsigned tid) 376 { return regFile.miscRegs[tid].getDataAsid(); } 377#else 378 /** Get instruction asid. */ 379 int getInstAsid(unsigned tid) 380 { return thread[tid]->getInstAsid(); } 381 382 /** Get data asid. */ 383 int getDataAsid(unsigned tid) 384 { return thread[tid]->getDataAsid(); } 385 386#endif 387 388 /** Register accessors. Index refers to the physical register index. */ 389 uint64_t readIntReg(int reg_idx); 390 391 TheISA::FloatReg readFloatReg(int reg_idx); 392 393 TheISA::FloatReg readFloatReg(int reg_idx, int width); 394 395 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 396 397 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 398 399 void setIntReg(int reg_idx, uint64_t val); 400 401 void setFloatReg(int reg_idx, TheISA::FloatReg val); 402 403 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 404 405 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 406 407 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 408 409 uint64_t readArchIntReg(int reg_idx, unsigned tid); 410 411 float readArchFloatRegSingle(int reg_idx, unsigned tid); 412 413 double readArchFloatRegDouble(int reg_idx, unsigned tid); 414 415 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 416 417 /** Architectural register accessors. Looks up in the commit 418 * rename table to obtain the true physical index of the 419 * architected register first, then accesses that physical 420 * register. 421 */ 422 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 423 424 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 425 426 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 427 428 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 429 430 /** Reads the commit PC of a specific thread. */ 431 uint64_t readPC(unsigned tid); 432 433 /** Sets the commit PC of a specific thread. */ 434 void setPC(Addr new_PC, unsigned tid); 435 436 /** Reads the next PC of a specific thread. */ 437 uint64_t readNextPC(unsigned tid); 438 439 /** Sets the next PC of a specific thread. */ 440 void setNextPC(uint64_t val, unsigned tid); 441 442 /** Reads the next NPC of a specific thread. */ 443 uint64_t readNextNPC(unsigned tid); 444 445 /** Sets the next NPC of a specific thread. */ 446 void setNextNPC(uint64_t val, unsigned tid); 447 448 /** Function to add instruction onto the head of the list of the 449 * instructions. Used when new instructions are fetched. 450 */ 451 ListIt addInst(DynInstPtr &inst); 452 453 /** Function to tell the CPU that an instruction has completed. */ 454 void instDone(unsigned tid); 455 456 /** Add Instructions to the CPU Remove List*/ 457 void addToRemoveList(DynInstPtr &inst); 458 459 /** Remove an instruction from the front end of the list. There's 460 * no restriction on location of the instruction. 461 */ 462 void removeFrontInst(DynInstPtr &inst); 463 464 /** Remove all instructions that are not currently in the ROB. 465 * There's also an option to not squash delay slot instructions.*/ 466 void removeInstsNotInROB(unsigned tid, bool squash_delay_slot, 467 const InstSeqNum &delay_slot_seq_num); 468 469 /** Remove all instructions younger than the given sequence number. */ 470 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 471 472 /** Removes the instruction pointed to by the iterator. */ 473 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 474 475 /** Cleans up all instructions on the remove list. */ 476 void cleanUpRemovedInsts(); 477 478 /** Debug function to print all instructions on the list. */ 479 void dumpInsts(); 480 481 public: 482 /** List of all the instructions in flight. */ 483 std::list<DynInstPtr> instList; 484 485 /** List of all the instructions that will be removed at the end of this 486 * cycle. 487 */ 488 std::queue<ListIt> removeList; 489 490#ifdef DEBUG 491 /** Debug structure to keep track of the sequence numbers still in 492 * flight. 493 */ 494 std::set<InstSeqNum> snList; 495#endif 496 497 /** Records if instructions need to be removed this cycle due to 498 * being retired or squashed. 499 */ 500 bool removeInstsThisCycle; 501 502 protected: 503 /** The fetch stage. */ 504 typename CPUPolicy::Fetch fetch; 505 506 /** The decode stage. */ 507 typename CPUPolicy::Decode decode; 508 509 /** The dispatch stage. */ 510 typename CPUPolicy::Rename rename; 511 512 /** The issue/execute/writeback stages. */ 513 typename CPUPolicy::IEW iew; 514 515 /** The commit stage. */ 516 typename CPUPolicy::Commit commit; 517 518 /** The register file. */ 519 typename CPUPolicy::RegFile regFile; 520 521 /** The free list. */ 522 typename CPUPolicy::FreeList freeList; 523 524 /** The rename map. */ 525 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 526 527 /** The commit rename map. */ 528 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 529 530 /** The re-order buffer. */ 531 typename CPUPolicy::ROB rob; 532 533 /** Active Threads List */ 534 std::list<unsigned> activeThreads; 535 536 /** Integer Register Scoreboard */ 537 Scoreboard scoreboard; 538 539 public: 540 /** Enum to give each stage a specific index, so when calling 541 * activateStage() or deactivateStage(), they can specify which stage 542 * is being activated/deactivated. 543 */ 544 enum StageIdx { 545 FetchIdx, 546 DecodeIdx, 547 RenameIdx, 548 IEWIdx, 549 CommitIdx, 550 NumStages }; 551 552 /** Typedefs from the Impl to get the structs that each of the 553 * time buffers should use. 554 */ 555 typedef typename CPUPolicy::TimeStruct TimeStruct; 556 557 typedef typename CPUPolicy::FetchStruct FetchStruct; 558 559 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 560 561 typedef typename CPUPolicy::RenameStruct RenameStruct; 562 563 typedef typename CPUPolicy::IEWStruct IEWStruct; 564 565 /** The main time buffer to do backwards communication. */ 566 TimeBuffer<TimeStruct> timeBuffer; 567 568 /** The fetch stage's instruction queue. */ 569 TimeBuffer<FetchStruct> fetchQueue; 570 571 /** The decode stage's instruction queue. */ 572 TimeBuffer<DecodeStruct> decodeQueue; 573 574 /** The rename stage's instruction queue. */ 575 TimeBuffer<RenameStruct> renameQueue; 576 577 /** The IEW stage's instruction queue. */ 578 TimeBuffer<IEWStruct> iewQueue; 579 580 private: 581 /** The activity recorder; used to tell if the CPU has any 582 * activity remaining or if it can go to idle and deschedule 583 * itself. 584 */ 585 ActivityRecorder activityRec; 586 587 public: 588 /** Records that there was time buffer activity this cycle. */ 589 void activityThisCycle() { activityRec.activity(); } 590 591 /** Changes a stage's status to active within the activity recorder. */ 592 void activateStage(const StageIdx idx) 593 { activityRec.activateStage(idx); } 594 595 /** Changes a stage's status to inactive within the activity recorder. */ 596 void deactivateStage(const StageIdx idx) 597 { activityRec.deactivateStage(idx); } 598 599 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 600 void wakeCPU(); 601 602 /** Gets a free thread id. Use if thread ids change across system. */ 603 int getFreeTid(); 604 605 public: 606 /** Returns a pointer to a thread context. */ 607 ThreadContext *tcBase(unsigned tid) 608 { 609 return thread[tid]->getTC(); 610 } 611 612 /** The global sequence number counter. */ 613 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 614 615 /** Pointer to the checker, which can dynamically verify 616 * instruction results at run time. This can be set to NULL if it 617 * is not being used. 618 */ 619 Checker<DynInstPtr> *checker; 620 621#if FULL_SYSTEM 622 /** Pointer to the system. */ 623 System *system; 624 625 /** Pointer to physical memory. */ 626 PhysicalMemory *physmem; 627#endif 628 629 /** Event to call process() on once draining has completed. */ 630 Event *drainEvent; 631 632 /** Counter of how many stages have completed draining. */ 633 int drainCount; 634 635 /** Pointers to all of the threads in the CPU. */ 636 std::vector<Thread *> thread; 637 638 /** Whether or not the CPU should defer its registration. */ 639 bool deferRegistration; 640 641 /** Is there a context switch pending? */ 642 bool contextSwitch; 643 644 /** Threads Scheduled to Enter CPU */ 645 std::list<int> cpuWaitList; 646 647 /** The cycle that the CPU was last running, used for statistics. */ 648 Tick lastRunningCycle; 649 650 /** The cycle that the CPU was last activated by a new thread*/ 651 Tick lastActivatedCycle; 652 653 /** Number of Threads CPU can process */ 654 unsigned numThreads; 655 656 /** Mapping for system thread id to cpu id */ 657 std::map<unsigned,unsigned> threadMap; 658 659 /** Available thread ids in the cpu*/ 660 std::vector<unsigned> tids; 661 662 /** Stat for total number of times the CPU is descheduled. */ 663 Stats::Scalar<> timesIdled; 664 /** Stat for total number of cycles the CPU spends descheduled. */ 665 Stats::Scalar<> idleCycles; 666 /** Stat for the number of committed instructions per thread. */ 667 Stats::Vector<> committedInsts; 668 /** Stat for the total number of committed instructions. */ 669 Stats::Scalar<> totalCommittedInsts; 670 /** Stat for the CPI per thread. */ 671 Stats::Formula cpi; 672 /** Stat for the total CPI. */ 673 Stats::Formula totalCpi; 674 /** Stat for the IPC per thread. */ 675 Stats::Formula ipc; 676 /** Stat for the total IPC. */ 677 Stats::Formula totalIpc; 678}; 679 680#endif // __CPU_O3_CPU_HH__ 681