cpu.hh revision 2843:19c4c6c2b5b1
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_CPU_HH__ 33#define __CPU_O3_CPU_HH__ 34 35#include <iostream> 36#include <list> 37#include <queue> 38#include <set> 39#include <vector> 40 41#include "arch/isa_traits.hh" 42#include "base/statistics.hh" 43#include "base/timebuf.hh" 44#include "config/full_system.hh" 45#include "cpu/activity.hh" 46#include "cpu/base.hh" 47#include "cpu/simple_thread.hh" 48#include "cpu/o3/comm.hh" 49#include "cpu/o3/cpu_policy.hh" 50#include "cpu/o3/scoreboard.hh" 51#include "cpu/o3/thread_state.hh" 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext; 60 61class Checkpoint; 62class MemObject; 63class Process; 64 65class BaseO3CPU : public BaseCPU 66{ 67 //Stuff that's pretty ISA independent will go here. 68 public: 69 typedef BaseCPU::Params Params; 70 71 BaseO3CPU(Params *params); 72 73 void regStats(); 74 75 /** Sets this CPU's ID. */ 76 void setCpuId(int id) { cpu_id = id; } 77 78 /** Reads this CPU's ID. */ 79 int readCpuId() { return cpu_id; } 80 81 protected: 82 int cpu_id; 83}; 84 85/** 86 * FullO3CPU class, has each of the stages (fetch through commit) 87 * within it, as well as all of the time buffers between stages. The 88 * tick() function for the CPU is defined here. 89 */ 90template <class Impl> 91class FullO3CPU : public BaseO3CPU 92{ 93 public: 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 97 // Typedefs from the Impl here. 98 typedef typename Impl::CPUPol CPUPolicy; 99 typedef typename Impl::Params Params; 100 typedef typename Impl::DynInstPtr DynInstPtr; 101 102 typedef O3ThreadState<Impl> Thread; 103 104 typedef typename std::list<DynInstPtr>::iterator ListIt; 105 106 friend class O3ThreadContext<Impl>; 107 108 public: 109 enum Status { 110 Running, 111 Idle, 112 Halted, 113 Blocked, 114 Drained, 115 SwitchedOut 116 }; 117 118 /** Overall CPU status. */ 119 Status _status; 120 121 /** Per-thread status in CPU, used for SMT. */ 122 Status _threadStatus[Impl::MaxThreads]; 123 124 private: 125 class TickEvent : public Event 126 { 127 private: 128 /** Pointer to the CPU. */ 129 FullO3CPU<Impl> *cpu; 130 131 public: 132 /** Constructs a tick event. */ 133 TickEvent(FullO3CPU<Impl> *c); 134 135 /** Processes a tick event, calling tick() on the CPU. */ 136 void process(); 137 /** Returns the description of the tick event. */ 138 const char *description(); 139 }; 140 141 /** The tick event used for scheduling CPU ticks. */ 142 TickEvent tickEvent; 143 144 /** Schedule tick event, regardless of its current state. */ 145 void scheduleTickEvent(int delay) 146 { 147 if (tickEvent.squashed()) 148 tickEvent.reschedule(curTick + cycles(delay)); 149 else if (!tickEvent.scheduled()) 150 tickEvent.schedule(curTick + cycles(delay)); 151 } 152 153 /** Unschedule tick event, regardless of its current state. */ 154 void unscheduleTickEvent() 155 { 156 if (tickEvent.scheduled()) 157 tickEvent.squash(); 158 } 159 160 class ActivateThreadEvent : public Event 161 { 162 private: 163 /** Number of Thread to Activate */ 164 int tid; 165 166 /** Pointer to the CPU. */ 167 FullO3CPU<Impl> *cpu; 168 169 public: 170 /** Constructs the event. */ 171 ActivateThreadEvent(); 172 173 /** Initialize Event */ 174 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 175 176 /** Processes the event, calling activateThread() on the CPU. */ 177 void process(); 178 179 /** Returns the description of the event. */ 180 const char *description(); 181 }; 182 183 /** Schedule thread to activate , regardless of its current state. */ 184 void scheduleActivateThreadEvent(int tid, int delay) 185 { 186 // Schedule thread to activate, regardless of its current state. 187 if (activateThreadEvent[tid].squashed()) 188 activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 189 else if (!activateThreadEvent[tid].scheduled()) 190 activateThreadEvent[tid].schedule(curTick + cycles(delay)); 191 } 192 193 /** Unschedule actiavte thread event, regardless of its current state. */ 194 void unscheduleActivateThreadEvent(int tid) 195 { 196 if (activateThreadEvent[tid].scheduled()) 197 activateThreadEvent[tid].squash(); 198 } 199 200 /** The tick event used for scheduling CPU ticks. */ 201 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 202 203 public: 204 /** Constructs a CPU with the given parameters. */ 205 FullO3CPU(Params *params); 206 /** Destructor. */ 207 ~FullO3CPU(); 208 209 /** Registers statistics. */ 210 void fullCPURegStats(); 211 212 /** Ticks CPU, calling tick() on each stage, and checking the overall 213 * activity to see if the CPU should deschedule itself. 214 */ 215 void tick(); 216 217 /** Initialize the CPU */ 218 void init(); 219 220 /** Returns the Number of Active Threads in the CPU */ 221 int numActiveThreads() 222 { return activeThreads.size(); } 223 224 /** Add Thread to Active Threads List */ 225 void activateThread(unsigned int tid); 226 227 /** Setup CPU to insert a thread's context */ 228 void insertThread(unsigned tid); 229 230 /** Remove all of a thread's context from CPU */ 231 void removeThread(unsigned tid); 232 233 /** Count the Total Instructions Committed in the CPU. */ 234 virtual Counter totalInstructions() const 235 { 236 Counter total(0); 237 238 for (int i=0; i < thread.size(); i++) 239 total += thread[i]->numInst; 240 241 return total; 242 } 243 244 /** Add Thread to Active Threads List. */ 245 void activateContext(int tid, int delay); 246 247 /** Remove Thread from Active Threads List */ 248 void suspendContext(int tid); 249 250 /** Remove Thread from Active Threads List && 251 * Remove Thread Context from CPU. 252 */ 253 void deallocateContext(int tid); 254 255 /** Remove Thread from Active Threads List && 256 * Remove Thread Context from CPU. 257 */ 258 void haltContext(int tid); 259 260 /** Activate a Thread When CPU Resources are Available. */ 261 void activateWhenReady(int tid); 262 263 /** Add or Remove a Thread Context in the CPU. */ 264 void doContextSwitch(); 265 266 /** Update The Order In Which We Process Threads. */ 267 void updateThreadPriority(); 268 269 /** Executes a syscall on this cycle. 270 * --------------------------------------- 271 * Note: this is a virtual function. CPU-Specific 272 * functionality defined in derived classes 273 */ 274 virtual void syscall(int tid) { panic("Unimplemented!"); } 275 276 /** Starts draining the CPU's pipeline of all instructions in 277 * order to stop all memory accesses. */ 278 virtual bool drain(Event *drain_event); 279 280 /** Resumes execution after a drain. */ 281 virtual void resume(); 282 283 /** Signals to this CPU that a stage has completed switching out. */ 284 void signalDrained(); 285 286 /** Switches out this CPU. */ 287 virtual void switchOut(); 288 289 /** Takes over from another CPU. */ 290 virtual void takeOverFrom(BaseCPU *oldCPU); 291 292 /** Get the current instruction sequence number, and increment it. */ 293 InstSeqNum getAndIncrementInstSeq() 294 { return globalSeqNum++; } 295 296#if FULL_SYSTEM 297 /** Check if this address is a valid instruction address. */ 298 bool validInstAddr(Addr addr) { return true; } 299 300 /** Check if this address is a valid data address. */ 301 bool validDataAddr(Addr addr) { return true; } 302 303 /** Get instruction asid. */ 304 int getInstAsid(unsigned tid) 305 { return regFile.miscRegs[tid].getInstAsid(); } 306 307 /** Get data asid. */ 308 int getDataAsid(unsigned tid) 309 { return regFile.miscRegs[tid].getDataAsid(); } 310#else 311 /** Get instruction asid. */ 312 int getInstAsid(unsigned tid) 313 { return thread[tid]->getInstAsid(); } 314 315 /** Get data asid. */ 316 int getDataAsid(unsigned tid) 317 { return thread[tid]->getDataAsid(); } 318 319#endif 320 321 /** Register accessors. Index refers to the physical register index. */ 322 uint64_t readIntReg(int reg_idx); 323 324 FloatReg readFloatReg(int reg_idx); 325 326 FloatReg readFloatReg(int reg_idx, int width); 327 328 FloatRegBits readFloatRegBits(int reg_idx); 329 330 FloatRegBits readFloatRegBits(int reg_idx, int width); 331 332 void setIntReg(int reg_idx, uint64_t val); 333 334 void setFloatReg(int reg_idx, FloatReg val); 335 336 void setFloatReg(int reg_idx, FloatReg val, int width); 337 338 void setFloatRegBits(int reg_idx, FloatRegBits val); 339 340 void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 341 342 uint64_t readArchIntReg(int reg_idx, unsigned tid); 343 344 float readArchFloatRegSingle(int reg_idx, unsigned tid); 345 346 double readArchFloatRegDouble(int reg_idx, unsigned tid); 347 348 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 349 350 /** Architectural register accessors. Looks up in the commit 351 * rename table to obtain the true physical index of the 352 * architected register first, then accesses that physical 353 * register. 354 */ 355 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 356 357 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 358 359 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 360 361 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 362 363 /** Reads the commit PC of a specific thread. */ 364 uint64_t readPC(unsigned tid); 365 366 /** Sets the commit PC of a specific thread. */ 367 void setPC(Addr new_PC, unsigned tid); 368 369 /** Reads the next PC of a specific thread. */ 370 uint64_t readNextPC(unsigned tid); 371 372 /** Sets the next PC of a specific thread. */ 373 void setNextPC(uint64_t val, unsigned tid); 374 375 /** Reads the next NPC of a specific thread. */ 376 uint64_t readNextNPC(unsigned tid); 377 378 /** Sets the next NPC of a specific thread. */ 379 void setNextNPC(uint64_t val, unsigned tid); 380 381 /** Function to add instruction onto the head of the list of the 382 * instructions. Used when new instructions are fetched. 383 */ 384 ListIt addInst(DynInstPtr &inst); 385 386 /** Function to tell the CPU that an instruction has completed. */ 387 void instDone(unsigned tid); 388 389 /** Add Instructions to the CPU Remove List*/ 390 void addToRemoveList(DynInstPtr &inst); 391 392 /** Remove an instruction from the front end of the list. There's 393 * no restriction on location of the instruction. 394 */ 395 void removeFrontInst(DynInstPtr &inst); 396 397 /** Remove all instructions that are not currently in the ROB. */ 398 void removeInstsNotInROB(unsigned tid); 399 400 /** Remove all instructions younger than the given sequence number. */ 401 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 402 403 /** Removes the instruction pointed to by the iterator. */ 404 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 405 406 /** Cleans up all instructions on the remove list. */ 407 void cleanUpRemovedInsts(); 408 409 /** Debug function to print all instructions on the list. */ 410 void dumpInsts(); 411 412 public: 413 /** List of all the instructions in flight. */ 414 std::list<DynInstPtr> instList; 415 416 /** List of all the instructions that will be removed at the end of this 417 * cycle. 418 */ 419 std::queue<ListIt> removeList; 420 421#ifdef DEBUG 422 /** Debug structure to keep track of the sequence numbers still in 423 * flight. 424 */ 425 std::set<InstSeqNum> snList; 426#endif 427 428 /** Records if instructions need to be removed this cycle due to 429 * being retired or squashed. 430 */ 431 bool removeInstsThisCycle; 432 433 protected: 434 /** The fetch stage. */ 435 typename CPUPolicy::Fetch fetch; 436 437 /** The decode stage. */ 438 typename CPUPolicy::Decode decode; 439 440 /** The dispatch stage. */ 441 typename CPUPolicy::Rename rename; 442 443 /** The issue/execute/writeback stages. */ 444 typename CPUPolicy::IEW iew; 445 446 /** The commit stage. */ 447 typename CPUPolicy::Commit commit; 448 449 /** The register file. */ 450 typename CPUPolicy::RegFile regFile; 451 452 /** The free list. */ 453 typename CPUPolicy::FreeList freeList; 454 455 /** The rename map. */ 456 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 457 458 /** The commit rename map. */ 459 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 460 461 /** The re-order buffer. */ 462 typename CPUPolicy::ROB rob; 463 464 /** Active Threads List */ 465 std::list<unsigned> activeThreads; 466 467 /** Integer Register Scoreboard */ 468 Scoreboard scoreboard; 469 470 public: 471 /** Enum to give each stage a specific index, so when calling 472 * activateStage() or deactivateStage(), they can specify which stage 473 * is being activated/deactivated. 474 */ 475 enum StageIdx { 476 FetchIdx, 477 DecodeIdx, 478 RenameIdx, 479 IEWIdx, 480 CommitIdx, 481 NumStages }; 482 483 /** Typedefs from the Impl to get the structs that each of the 484 * time buffers should use. 485 */ 486 typedef typename CPUPolicy::TimeStruct TimeStruct; 487 488 typedef typename CPUPolicy::FetchStruct FetchStruct; 489 490 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 491 492 typedef typename CPUPolicy::RenameStruct RenameStruct; 493 494 typedef typename CPUPolicy::IEWStruct IEWStruct; 495 496 /** The main time buffer to do backwards communication. */ 497 TimeBuffer<TimeStruct> timeBuffer; 498 499 /** The fetch stage's instruction queue. */ 500 TimeBuffer<FetchStruct> fetchQueue; 501 502 /** The decode stage's instruction queue. */ 503 TimeBuffer<DecodeStruct> decodeQueue; 504 505 /** The rename stage's instruction queue. */ 506 TimeBuffer<RenameStruct> renameQueue; 507 508 /** The IEW stage's instruction queue. */ 509 TimeBuffer<IEWStruct> iewQueue; 510 511 private: 512 /** The activity recorder; used to tell if the CPU has any 513 * activity remaining or if it can go to idle and deschedule 514 * itself. 515 */ 516 ActivityRecorder activityRec; 517 518 public: 519 /** Records that there was time buffer activity this cycle. */ 520 void activityThisCycle() { activityRec.activity(); } 521 522 /** Changes a stage's status to active within the activity recorder. */ 523 void activateStage(const StageIdx idx) 524 { activityRec.activateStage(idx); } 525 526 /** Changes a stage's status to inactive within the activity recorder. */ 527 void deactivateStage(const StageIdx idx) 528 { activityRec.deactivateStage(idx); } 529 530 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 531 void wakeCPU(); 532 533 /** Gets a free thread id. Use if thread ids change across system. */ 534 int getFreeTid(); 535 536 public: 537 /** Returns a pointer to a thread context. */ 538 ThreadContext *tcBase(unsigned tid) 539 { 540 return thread[tid]->getTC(); 541 } 542 543 /** The global sequence number counter. */ 544 InstSeqNum globalSeqNum; 545 546 /** Pointer to the checker, which can dynamically verify 547 * instruction results at run time. This can be set to NULL if it 548 * is not being used. 549 */ 550 Checker<DynInstPtr> *checker; 551 552#if FULL_SYSTEM 553 /** Pointer to the system. */ 554 System *system; 555 556 /** Pointer to physical memory. */ 557 PhysicalMemory *physmem; 558#endif 559 560 /** Pointer to memory. */ 561 MemObject *mem; 562 563 /** Event to call process() on once draining has completed. */ 564 Event *drainEvent; 565 566 /** Counter of how many stages have completed draining. */ 567 int drainCount; 568 569 /** Pointers to all of the threads in the CPU. */ 570 std::vector<Thread *> thread; 571 572 /** Pointer to the icache interface. */ 573 MemInterface *icacheInterface; 574 /** Pointer to the dcache interface. */ 575 MemInterface *dcacheInterface; 576 577 /** Whether or not the CPU should defer its registration. */ 578 bool deferRegistration; 579 580 /** Is there a context switch pending? */ 581 bool contextSwitch; 582 583 /** Threads Scheduled to Enter CPU */ 584 std::list<int> cpuWaitList; 585 586 /** The cycle that the CPU was last running, used for statistics. */ 587 Tick lastRunningCycle; 588 589 /** The cycle that the CPU was last activated by a new thread*/ 590 Tick lastActivatedCycle; 591 592 /** Number of Threads CPU can process */ 593 unsigned numThreads; 594 595 /** Mapping for system thread id to cpu id */ 596 std::map<unsigned,unsigned> threadMap; 597 598 /** Available thread ids in the cpu*/ 599 std::vector<unsigned> tids; 600 601 /** Stat for total number of times the CPU is descheduled. */ 602 Stats::Scalar<> timesIdled; 603 /** Stat for total number of cycles the CPU spends descheduled. */ 604 Stats::Scalar<> idleCycles; 605 /** Stat for the number of committed instructions per thread. */ 606 Stats::Vector<> committedInsts; 607 /** Stat for the total number of committed instructions. */ 608 Stats::Scalar<> totalCommittedInsts; 609 /** Stat for the CPI per thread. */ 610 Stats::Formula cpi; 611 /** Stat for the total CPI. */ 612 Stats::Formula totalCpi; 613 /** Stat for the IPC per thread. */ 614 Stats::Formula ipc; 615 /** Stat for the total IPC. */ 616 Stats::Formula totalIpc; 617}; 618 619#endif // __CPU_O3_CPU_HH__ 620