cpu.hh revision 1689
11689SN/A/* 22325SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292756Sksewell@umich.edu//Todo: Add in a lot of the functions that are ISA specific. Also define 301689SN/A//the functions that currently exist within the base cpu class. Define 311689SN/A//everything for the simobject stuff so it can be serialized and 321858SN/A//instantiated, add in debugging statements everywhere. Have CPU schedule 336658Snate@binkert.org//itself properly. Threads! 342733Sktlim@umich.edu// Avoid running stages and advancing queues if idle/stalled. 354762Snate@binkert.org 364762Snate@binkert.org#ifndef __CPU_BETA_CPU_FULL_CPU_HH__ 374762Snate@binkert.org#define __CPU_BETA_CPU_FULL_CPU_HH__ 384762Snate@binkert.org 394762Snate@binkert.org#include <iostream> 405595Sgblack@eecs.umich.edu#include <list> 414762Snate@binkert.org#include <vector> 424762Snate@binkert.org 434762Snate@binkert.org#include "base/statistics.hh" 444762Snate@binkert.org#include "base/timebuf.hh" 451858SN/A#include "cpu/base_cpu.hh" 462356SN/A#include "cpu/beta_cpu/comm.hh" 471060SN/A#include "cpu/beta_cpu/cpu_policy.hh" 481060SN/A#include "cpu/exec_context.hh" 491060SN/A#include "sim/process.hh" 501060SN/A 511060SN/A#ifdef FULL_SYSTEM 522794Sktlim@umich.edu#include "arch/alpha/ev5.hh" 532794Sktlim@umich.eduusing namespace EV5; 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.educlass FunctionalMemory; 575702Ssaidi@eecs.umich.educlass Process; 585702Ssaidi@eecs.umich.edu 595702Ssaidi@eecs.umich.educlass BaseFullCPU : public BaseCPU 605529Snate@binkert.org{ 615529Snate@binkert.org //Stuff that's pretty ISA independent will go here. 622669Sktlim@umich.edu public: 636221Snate@binkert.org typedef BaseCPU::Params Params; 641060SN/A 655529Snate@binkert.org#ifdef FULL_SYSTEM 665712Shsul@eecs.umich.edu BaseFullCPU(Params ¶ms); 671060SN/A#else 681060SN/A BaseFullCPU(Params ¶ms); 691060SN/A#endif // FULL_SYSTEM 702292SN/A 712733Sktlim@umich.edu protected: 722292SN/A int cpu_id; 732292SN/A}; 742292SN/A 752292SN/Atemplate <class Impl> 761060SN/Aclass FullBetaCPU : public BaseFullCPU 771755SN/A{ 785606Snate@binkert.org public: 791060SN/A //Put typedefs from the Impl here. 801060SN/A typedef typename Impl::ISA ISA; 811060SN/A typedef typename Impl::CPUPol CPUPolicy; 821060SN/A typedef typename Impl::Params Params; 831060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 841755SN/A 851060SN/A public: 861060SN/A enum Status { 871060SN/A Running, 881060SN/A Idle, 891060SN/A Halted, 901060SN/A Blocked // ? 915336Shines@cs.fsu.edu }; 921060SN/A 934873Sstever@eecs.umich.edu Status _status; 941060SN/A 951060SN/A private: 961060SN/A class TickEvent : public Event 972829Sksewell@umich.edu { 985606Snate@binkert.org private: 992829Sksewell@umich.edu FullBetaCPU<Impl> *cpu; 1002829Sksewell@umich.edu 1012829Sksewell@umich.edu public: 1022829Sksewell@umich.edu TickEvent(FullBetaCPU<Impl> *c); 1032829Sksewell@umich.edu void process(); 1042829Sksewell@umich.edu const char *description(); 1052829Sksewell@umich.edu }; 1062829Sksewell@umich.edu 1072829Sksewell@umich.edu TickEvent tickEvent; 1082829Sksewell@umich.edu 1092829Sksewell@umich.edu /// Schedule tick event, regardless of its current state. 1102829Sksewell@umich.edu void scheduleTickEvent(int delay) 1112829Sksewell@umich.edu { 1122829Sksewell@umich.edu if (tickEvent.squashed()) 1132829Sksewell@umich.edu tickEvent.reschedule(curTick + delay); 1142829Sksewell@umich.edu else if (!tickEvent.scheduled()) 1152829Sksewell@umich.edu tickEvent.schedule(curTick + delay); 1162829Sksewell@umich.edu } 1172829Sksewell@umich.edu 1182829Sksewell@umich.edu /// Unschedule tick event, regardless of its current state. 1192829Sksewell@umich.edu void unscheduleTickEvent() 1205336Shines@cs.fsu.edu { 1212829Sksewell@umich.edu if (tickEvent.scheduled()) 1224873Sstever@eecs.umich.edu tickEvent.squash(); 1232829Sksewell@umich.edu } 1242829Sksewell@umich.edu 1252829Sksewell@umich.edu public: 1262875Sksewell@umich.edu FullBetaCPU(Params ¶ms); 1275606Snate@binkert.org ~FullBetaCPU(); 1282875Sksewell@umich.edu 1292875Sksewell@umich.edu void fullCPURegStats(); 1302875Sksewell@umich.edu 1312875Sksewell@umich.edu void tick(); 1322875Sksewell@umich.edu 1332875Sksewell@umich.edu void init(); 1343859Sbinkertn@umich.edu 1352875Sksewell@umich.edu void activateContext(int thread_num, int delay); 1362875Sksewell@umich.edu void suspendContext(int thread_num); 1372875Sksewell@umich.edu void deallocateContext(int thread_num); 1383859Sbinkertn@umich.edu void haltContext(int thread_num); 1392875Sksewell@umich.edu 1402875Sksewell@umich.edu void switchOut(); 1412875Sksewell@umich.edu void takeOverFrom(BaseCPU *oldCPU); 1422875Sksewell@umich.edu 1432875Sksewell@umich.edu /** Get the current instruction sequence number, and increment it. */ 1442875Sksewell@umich.edu InstSeqNum getAndIncrementInstSeq(); 1452875Sksewell@umich.edu 1463221Sktlim@umich.edu#ifdef FULL_SYSTEM 1473221Sktlim@umich.edu /** Check if this address is a valid instruction address. */ 1482875Sksewell@umich.edu bool validInstAddr(Addr addr) { return true; } 1492875Sksewell@umich.edu 1502875Sksewell@umich.edu /** Check if this address is a valid data address. */ 1512875Sksewell@umich.edu bool validDataAddr(Addr addr) { return true; } 1525336Shines@cs.fsu.edu 1532875Sksewell@umich.edu /** Get instruction asid. */ 1544873Sstever@eecs.umich.edu int getInstAsid() 1552875Sksewell@umich.edu { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); } 1562875Sksewell@umich.edu 1572875Sksewell@umich.edu /** Get data asid. */ 1585595Sgblack@eecs.umich.edu int getDataAsid() 1592733Sktlim@umich.edu { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); } 1603781Sgblack@eecs.umich.edu#else 1613781Sgblack@eecs.umich.edu bool validInstAddr(Addr addr) 1621060SN/A { return thread[0]->validInstAddr(addr); } 1635737Scws3k@cs.virginia.edu 1645737Scws3k@cs.virginia.edu bool validDataAddr(Addr addr) 1655737Scws3k@cs.virginia.edu { return thread[0]->validDataAddr(addr); } 1662292SN/A 1675595Sgblack@eecs.umich.edu int getInstAsid() { return thread[0]->asid; } 1685595Sgblack@eecs.umich.edu int getDataAsid() { return thread[0]->asid; } 1695595Sgblack@eecs.umich.edu 1705595Sgblack@eecs.umich.edu#endif 1715595Sgblack@eecs.umich.edu 1721060SN/A // 1735595Sgblack@eecs.umich.edu // New accessors for new decoder. 1744329Sktlim@umich.edu // 1751060SN/A uint64_t readIntReg(int reg_idx); 1765529Snate@binkert.org 1772292SN/A float readFloatRegSingle(int reg_idx); 1782292SN/A 1791060SN/A double readFloatRegDouble(int reg_idx); 1805595Sgblack@eecs.umich.edu 1814329Sktlim@umich.edu uint64_t readFloatRegInt(int reg_idx); 1822292SN/A 1835529Snate@binkert.org void setIntReg(int reg_idx, uint64_t val); 1841060SN/A 1855529Snate@binkert.org void setFloatRegSingle(int reg_idx, float val); 1862292SN/A 1872292SN/A void setFloatRegDouble(int reg_idx, double val); 1886221Snate@binkert.org 1892292SN/A void setFloatRegInt(int reg_idx, uint64_t val); 1901060SN/A 1912873Sktlim@umich.edu uint64_t readPC(); 1922873Sktlim@umich.edu 1932873Sktlim@umich.edu void setNextPC(uint64_t val); 1942873Sktlim@umich.edu 1952873Sktlim@umich.edu void setPC(Addr new_PC); 1965804Snate@binkert.org 1972873Sktlim@umich.edu /** Function to add instruction onto the head of the list of the 1982873Sktlim@umich.edu * instructions. Used when new instructions are fetched. 1991060SN/A */ 2001060SN/A void addInst(DynInstPtr &inst); 2011858SN/A 2022292SN/A /** Function to tell the CPU that an instruction has completed. */ 2031060SN/A void instDone(); 2042843Sktlim@umich.edu 2056221Snate@binkert.org /** Remove all instructions in back of the given instruction, but leave 2061060SN/A * that instruction in the list. This is useful in a squash, when there 2073221Sktlim@umich.edu * are instructions in this list that don't exist in structures such as 2083221Sktlim@umich.edu * the ROB. The instruction doesn't have to be the last instruction in 2093221Sktlim@umich.edu * the list, but will be once this function completes. 2103221Sktlim@umich.edu * @todo: Remove only up until that inst? Squashed inst is most likely 2113221Sktlim@umich.edu * valid. 2121681SN/A */ 2134598Sbinkertn@umich.edu void removeBackInst(DynInstPtr &inst); 2142794Sktlim@umich.edu 2152316SN/A /** Remove an instruction from the front of the list. It is expected 2162316SN/A * that there are no instructions in front of it (that is, none are older 2172316SN/A * than the instruction being removed). Used when retiring instructions. 2182316SN/A * @todo: Remove the argument to this function, and just have it remove 2192316SN/A * last instruction once it's verified that commit has the same ordering 2204598Sbinkertn@umich.edu * as the instruction list. 2214598Sbinkertn@umich.edu */ 2224598Sbinkertn@umich.edu void removeFrontInst(DynInstPtr &inst); 2232794Sktlim@umich.edu 2242316SN/A /** Remove all instructions that are not currently in the ROB. */ 2251858SN/A void removeInstsNotInROB(); 2266221Snate@binkert.org 2276221Snate@binkert.org /** Remove all instructions younger than the given sequence number. */ 2281681SN/A void removeInstsUntil(const InstSeqNum &seq_num); 2291681SN/A 2302325SN/A /** Remove all instructions from the list. */ 2312325SN/A void removeAllInsts(); 2322325SN/A 2331060SN/A void dumpInsts(); 2342292SN/A 2352292SN/A /** Basically a wrapper function so that instructions executed at 2362292SN/A * commit can tell the instruction queue that they have completed. 2372292SN/A * Eventually this hack should be removed. 2382292SN/A */ 2392292SN/A void wakeDependents(DynInstPtr &inst); 2401060SN/A 2411060SN/A public: 2421060SN/A /** List of all the instructions in flight. */ 2431060SN/A list<DynInstPtr> instList; 2441060SN/A 2451060SN/A //not sure these should be private. 2461060SN/A protected: 2471060SN/A /** The fetch stage. */ 2481060SN/A typename CPUPolicy::Fetch fetch; 2491060SN/A 2501060SN/A /** The fetch stage's status. */ 2512292SN/A typename CPUPolicy::Fetch::Status fetchStatus; 2521060SN/A 2531060SN/A /** The decode stage. */ 2541060SN/A typename CPUPolicy::Decode decode; 2551060SN/A 2561060SN/A /** The decode stage's status. */ 2571060SN/A typename CPUPolicy::Decode::Status decodeStatus; 2581060SN/A 2591060SN/A /** The dispatch stage. */ 2602292SN/A typename CPUPolicy::Rename rename; 2612292SN/A 2622292SN/A /** The dispatch stage's status. */ 2632292SN/A typename CPUPolicy::Rename::Status renameStatus; 2642292SN/A 2656221Snate@binkert.org /** The issue/execute/writeback stages. */ 2662831Sksewell@umich.edu typename CPUPolicy::IEW iew; 2672831Sksewell@umich.edu 2682831Sksewell@umich.edu /** The issue/execute/writeback stage's status. */ 2692831Sksewell@umich.edu typename CPUPolicy::IEW::Status iewStatus; 2702831Sksewell@umich.edu 2712831Sksewell@umich.edu /** The commit stage. */ 2722292SN/A typename CPUPolicy::Commit commit; 2736221Snate@binkert.org 2742292SN/A /** The fetch stage's status. */ 2752292SN/A typename CPUPolicy::Commit::Status commitStatus; 2762316SN/A 2772292SN/A //Might want to just pass these objects in to the constructors of the 2782292SN/A //appropriate stage. regFile is in iew, freeList in dispatch, renameMap 2792292SN/A //in dispatch, and the rob in commit. 2802292SN/A /** The register file. */ 2812292SN/A typename CPUPolicy::RegFile regFile; 2822292SN/A 2831060SN/A /** The free list. */ 2842292SN/A typename CPUPolicy::FreeList freeList; 2852292SN/A 2861060SN/A /** The rename map. */ 2876221Snate@binkert.org typename CPUPolicy::RenameMap renameMap; 2882307SN/A 2892292SN/A /** The re-order buffer. */ 2902292SN/A typename CPUPolicy::ROB rob; 2912292SN/A 2922325SN/A public: 2932292SN/A /** Typedefs from the Impl to get the structs that each of the 2942292SN/A * time buffers should use. 2952292SN/A */ 2962325SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 2972292SN/A 2982292SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 2992292SN/A 3002292SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 3012292SN/A 3022292SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 3032292SN/A 3042292SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 3052292SN/A 3062292SN/A /** The main time buffer to do backwards communication. */ 3072292SN/A TimeBuffer<TimeStruct> timeBuffer; 3082325SN/A 3092292SN/A /** The fetch stage's instruction queue. */ 3102292SN/A TimeBuffer<FetchStruct> fetchQueue; 3112292SN/A 3122325SN/A /** The decode stage's instruction queue. */ 3132292SN/A TimeBuffer<DecodeStruct> decodeQueue; 3142292SN/A 3152292SN/A /** The rename stage's instruction queue. */ 3162292SN/A TimeBuffer<RenameStruct> renameQueue; 3172292SN/A 3182292SN/A /** The IEW stage's instruction queue. */ 3192292SN/A TimeBuffer<IEWStruct> iewQueue; 3202292SN/A 3213221Sktlim@umich.edu public: 3223221Sktlim@umich.edu /** The temporary exec context to support older accessors. */ 3233221Sktlim@umich.edu ExecContext *xc; 3242292SN/A 3252292SN/A /** Temporary function to get pointer to exec context. */ 3262292SN/A ExecContext *xcBase() 3272292SN/A { 3282292SN/A#ifdef FULL_SYSTEM 3292292SN/A return system->execContexts[0]; 3306221Snate@binkert.org#else 3316221Snate@binkert.org return thread[0]; 3321060SN/A#endif 3332292SN/A } 3341060SN/A 3351060SN/A InstSeqNum globalSeqNum; 3362292SN/A 3372292SN/A#ifdef FULL_SYSTEM 3382292SN/A System *system; 3392829Sksewell@umich.edu 3406221Snate@binkert.org MemoryController *memCtrl; 3413093Sksewell@umich.edu PhysicalMemory *physmem; 3426221Snate@binkert.org 3436221Snate@binkert.org AlphaITB *itb; 3446221Snate@binkert.org AlphaDTB *dtb; 3453093Sksewell@umich.edu 3462292SN/A// SWContext *swCtx; 3475595Sgblack@eecs.umich.edu#else 3485595Sgblack@eecs.umich.edu std::vector<ExecContext *> thread; 3495595Sgblack@eecs.umich.edu#endif 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu FunctionalMemory *mem; 3526221Snate@binkert.org 3535595Sgblack@eecs.umich.edu MemInterface *icacheInterface; 3545595Sgblack@eecs.umich.edu MemInterface *dcacheInterface; 3555595Sgblack@eecs.umich.edu 3566221Snate@binkert.org bool deferRegistration; 3575595Sgblack@eecs.umich.edu 3586221Snate@binkert.org Counter numInsts; 3595595Sgblack@eecs.umich.edu 3606221Snate@binkert.org Counter funcExeInst; 3616221Snate@binkert.org}; 3625595Sgblack@eecs.umich.edu 3636331Sgblack@eecs.umich.edu#endif 3645595Sgblack@eecs.umich.edu