cpu.hh revision 13908:6ab98c626b06
1/* 2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/generic/types.hh" 57#include "arch/types.hh" 58#include "base/statistics.hh" 59#include "config/the_isa.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class Process; 80 81struct BaseCPUParams; 82 83class BaseO3CPU : public BaseCPU 84{ 85 //Stuff that's pretty ISA independent will go here. 86 public: 87 BaseO3CPU(BaseCPUParams *params); 88 89 void regStats(); 90}; 91 92/** 93 * FullO3CPU class, has each of the stages (fetch through commit) 94 * within it, as well as all of the time buffers between stages. The 95 * tick() function for the CPU is defined here. 96 */ 97template <class Impl> 98class FullO3CPU : public BaseO3CPU 99{ 100 public: 101 // Typedefs from the Impl here. 102 typedef typename Impl::CPUPol CPUPolicy; 103 typedef typename Impl::DynInstPtr DynInstPtr; 104 typedef typename Impl::O3CPU O3CPU; 105 106 using VecElem = TheISA::VecElem; 107 using VecRegContainer = TheISA::VecRegContainer; 108 109 using VecPredRegContainer = TheISA::VecPredRegContainer; 110 111 typedef O3ThreadState<Impl> ImplState; 112 typedef O3ThreadState<Impl> Thread; 113 114 typedef typename std::list<DynInstPtr>::iterator ListIt; 115 116 friend class O3ThreadContext<Impl>; 117 118 public: 119 enum Status { 120 Running, 121 Idle, 122 Halted, 123 Blocked, 124 SwitchedOut 125 }; 126 127 BaseTLB *itb; 128 BaseTLB *dtb; 129 using LSQRequest = typename LSQ<Impl>::LSQRequest; 130 131 /** Overall CPU status. */ 132 Status _status; 133 134 private: 135 136 /** 137 * IcachePort class for instruction fetch. 138 */ 139 class IcachePort : public MasterPort 140 { 141 protected: 142 /** Pointer to fetch. */ 143 DefaultFetch<Impl> *fetch; 144 145 public: 146 /** Default constructor. */ 147 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 148 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 149 { } 150 151 protected: 152 153 /** Timing version of receive. Handles setting fetch to the 154 * proper status to start fetching. */ 155 virtual bool recvTimingResp(PacketPtr pkt); 156 157 /** Handles doing a retry of a failed fetch. */ 158 virtual void recvReqRetry(); 159 }; 160 161 /** 162 * DcachePort class for the load/store queue. 163 */ 164 class DcachePort : public MasterPort 165 { 166 protected: 167 168 /** Pointer to LSQ. */ 169 LSQ<Impl> *lsq; 170 FullO3CPU<Impl> *cpu; 171 172 public: 173 /** Default constructor. */ 174 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 175 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 176 cpu(_cpu) 177 { } 178 179 protected: 180 181 /** Timing version of receive. Handles writing back and 182 * completing the load or store that has returned from 183 * memory. */ 184 virtual bool recvTimingResp(PacketPtr pkt); 185 virtual void recvTimingSnoopReq(PacketPtr pkt); 186 187 virtual void recvFunctionalSnoop(PacketPtr pkt) 188 { 189 // @todo: Is there a need for potential invalidation here? 190 } 191 192 /** Handles doing a retry of the previous send. */ 193 virtual void recvReqRetry(); 194 195 /** 196 * As this CPU requires snooping to maintain the load store queue 197 * change the behaviour from the base CPU port. 198 * 199 * @return true since we have to snoop 200 */ 201 virtual bool isSnooping() const { return true; } 202 }; 203 204 /** The tick event used for scheduling CPU ticks. */ 205 EventFunctionWrapper tickEvent; 206 207 /** The exit event used for terminating all ready-to-exit threads */ 208 EventFunctionWrapper threadExitEvent; 209 210 /** Schedule tick event, regardless of its current state. */ 211 void scheduleTickEvent(Cycles delay) 212 { 213 if (tickEvent.squashed()) 214 reschedule(tickEvent, clockEdge(delay)); 215 else if (!tickEvent.scheduled()) 216 schedule(tickEvent, clockEdge(delay)); 217 } 218 219 /** Unschedule tick event, regardless of its current state. */ 220 void unscheduleTickEvent() 221 { 222 if (tickEvent.scheduled()) 223 tickEvent.squash(); 224 } 225 226 /** 227 * Check if the pipeline has drained and signal drain done. 228 * 229 * This method checks if a drain has been requested and if the CPU 230 * has drained successfully (i.e., there are no instructions in 231 * the pipeline). If the CPU has drained, it deschedules the tick 232 * event and signals the drain manager. 233 * 234 * @return False if a drain hasn't been requested or the CPU 235 * hasn't drained, true otherwise. 236 */ 237 bool tryDrain(); 238 239 /** 240 * Perform sanity checks after a drain. 241 * 242 * This method is called from drain() when it has determined that 243 * the CPU is fully drained when gem5 is compiled with the NDEBUG 244 * macro undefined. The intention of this method is to do more 245 * extensive tests than the isDrained() method to weed out any 246 * draining bugs. 247 */ 248 void drainSanityCheck() const; 249 250 /** Check if a system is in a drained state. */ 251 bool isDrained() const; 252 253 public: 254 /** Constructs a CPU with the given parameters. */ 255 FullO3CPU(DerivO3CPUParams *params); 256 /** Destructor. */ 257 ~FullO3CPU(); 258 259 /** Registers statistics. */ 260 void regStats() override; 261 262 ProbePointArg<PacketPtr> *ppInstAccessComplete; 263 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 264 265 /** Register probe points. */ 266 void regProbePoints() override; 267 268 void demapPage(Addr vaddr, uint64_t asn) 269 { 270 this->itb->demapPage(vaddr, asn); 271 this->dtb->demapPage(vaddr, asn); 272 } 273 274 void demapInstPage(Addr vaddr, uint64_t asn) 275 { 276 this->itb->demapPage(vaddr, asn); 277 } 278 279 void demapDataPage(Addr vaddr, uint64_t asn) 280 { 281 this->dtb->demapPage(vaddr, asn); 282 } 283 284 /** Ticks CPU, calling tick() on each stage, and checking the overall 285 * activity to see if the CPU should deschedule itself. 286 */ 287 void tick(); 288 289 /** Initialize the CPU */ 290 void init() override; 291 292 void startup() override; 293 294 /** Returns the Number of Active Threads in the CPU */ 295 int numActiveThreads() 296 { return activeThreads.size(); } 297 298 /** Add Thread to Active Threads List */ 299 void activateThread(ThreadID tid); 300 301 /** Remove Thread from Active Threads List */ 302 void deactivateThread(ThreadID tid); 303 304 /** Setup CPU to insert a thread's context */ 305 void insertThread(ThreadID tid); 306 307 /** Remove all of a thread's context from CPU */ 308 void removeThread(ThreadID tid); 309 310 /** Count the Total Instructions Committed in the CPU. */ 311 Counter totalInsts() const override; 312 313 /** Count the Total Ops (including micro ops) committed in the CPU. */ 314 Counter totalOps() const override; 315 316 /** Add Thread to Active Threads List. */ 317 void activateContext(ThreadID tid) override; 318 319 /** Remove Thread from Active Threads List */ 320 void suspendContext(ThreadID tid) override; 321 322 /** Remove Thread from Active Threads List && 323 * Remove Thread Context from CPU. 324 */ 325 void haltContext(ThreadID tid) override; 326 327 /** Update The Order In Which We Process Threads. */ 328 void updateThreadPriority(); 329 330 /** Is the CPU draining? */ 331 bool isDraining() const { return drainState() == DrainState::Draining; } 332 333 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 334 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 335 336 /** Insert tid to the list of threads trying to exit */ 337 void addThreadToExitingList(ThreadID tid); 338 339 /** Is the thread trying to exit? */ 340 bool isThreadExiting(ThreadID tid) const; 341 342 /** 343 * If a thread is trying to exit and its corresponding trap event 344 * has been completed, schedule an event to terminate the thread. 345 */ 346 void scheduleThreadExitEvent(ThreadID tid); 347 348 /** Terminate all threads that are ready to exit */ 349 void exitThreads(); 350 351 public: 352 /** Executes a syscall. 353 * @todo: Determine if this needs to be virtual. 354 */ 355 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 356 357 /** Starts draining the CPU's pipeline of all instructions in 358 * order to stop all memory accesses. */ 359 DrainState drain() override; 360 361 /** Resumes execution after a drain. */ 362 void drainResume() override; 363 364 /** 365 * Commit has reached a safe point to drain a thread. 366 * 367 * Commit calls this method to inform the pipeline that it has 368 * reached a point where it is not executed microcode and is about 369 * to squash uncommitted instructions to fully drain the pipeline. 370 */ 371 void commitDrained(ThreadID tid); 372 373 /** Switches out this CPU. */ 374 void switchOut() override; 375 376 /** Takes over from another CPU. */ 377 void takeOverFrom(BaseCPU *oldCPU) override; 378 379 void verifyMemoryMode() const override; 380 381 /** Get the current instruction sequence number, and increment it. */ 382 InstSeqNum getAndIncrementInstSeq() 383 { return globalSeqNum++; } 384 385 /** Traps to handle given fault. */ 386 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 387 388 bool simPalCheck(int palFunc, ThreadID tid); 389 390 /** Check if a change in renaming is needed for vector registers. 391 * The vecMode variable is updated and propagated to rename maps. 392 * 393 * @param tid ThreadID 394 * @param freelist list of free registers 395 */ 396 void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist); 397 398 /** Returns the Fault for any valid interrupt. */ 399 Fault getInterrupts(); 400 401 /** Processes any an interrupt fault. */ 402 void processInterrupts(const Fault &interrupt); 403 404 /** Halts the CPU. */ 405 void halt() { panic("Halt not implemented!\n"); } 406 407 /** Register accessors. Index refers to the physical register index. */ 408 409 /** Reads a miscellaneous register. */ 410 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 411 412 /** Reads a misc. register, including any side effects the read 413 * might have as defined by the architecture. 414 */ 415 RegVal readMiscReg(int misc_reg, ThreadID tid); 416 417 /** Sets a miscellaneous register. */ 418 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 419 420 /** Sets a misc. register, including any side effects the write 421 * might have as defined by the architecture. 422 */ 423 void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 424 425 RegVal readIntReg(PhysRegIdPtr phys_reg); 426 427 RegVal readFloatReg(PhysRegIdPtr phys_reg); 428 429 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 430 431 /** 432 * Read physical vector register for modification. 433 */ 434 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 435 436 /** Returns current vector renaming mode */ 437 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; } 438 439 /** Sets the current vector renaming mode */ 440 void vecRenameMode(Enums::VecRegRenameMode vec_mode) 441 { vecMode = vec_mode; } 442 443 /** 444 * Read physical vector register lane 445 */ 446 template<typename VecElem, int LaneIdx> 447 VecLaneT<VecElem, true> 448 readVecLane(PhysRegIdPtr phys_reg) const 449 { 450 vecRegfileReads++; 451 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 452 } 453 454 /** 455 * Read physical vector register lane 456 */ 457 template<typename VecElem> 458 VecLaneT<VecElem, true> 459 readVecLane(PhysRegIdPtr phys_reg) const 460 { 461 vecRegfileReads++; 462 return regFile.readVecLane<VecElem>(phys_reg); 463 } 464 465 /** Write a lane of the destination vector register. */ 466 template<typename LD> 467 void 468 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 469 { 470 vecRegfileWrites++; 471 return regFile.setVecLane(phys_reg, val); 472 } 473 474 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 475 476 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 477 478 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 479 480 RegVal readCCReg(PhysRegIdPtr phys_reg); 481 482 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 483 484 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 485 486 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 487 488 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 489 490 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 491 492 void setCCReg(PhysRegIdPtr phys_reg, RegVal val); 493 494 RegVal readArchIntReg(int reg_idx, ThreadID tid); 495 496 RegVal readArchFloatReg(int reg_idx, ThreadID tid); 497 498 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 499 /** Read architectural vector register for modification. */ 500 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 501 502 /** Read architectural vector register lane. */ 503 template<typename VecElem> 504 VecLaneT<VecElem, true> 505 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 506 { 507 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 508 RegId(VecRegClass, reg_idx)); 509 return readVecLane<VecElem>(phys_reg); 510 } 511 512 513 /** Write a lane of the destination vector register. */ 514 template<typename LD> 515 void 516 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 517 { 518 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 519 RegId(VecRegClass, reg_idx)); 520 setVecLane(phys_reg, val); 521 } 522 523 const VecElem& readArchVecElem(const RegIndex& reg_idx, 524 const ElemIndex& ldx, ThreadID tid) const; 525 526 const VecPredRegContainer& readArchVecPredReg(int reg_idx, 527 ThreadID tid) const; 528 529 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 530 531 RegVal readArchCCReg(int reg_idx, ThreadID tid); 532 533 /** Architectural register accessors. Looks up in the commit 534 * rename table to obtain the true physical index of the 535 * architected register first, then accesses that physical 536 * register. 537 */ 538 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 539 540 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); 541 542 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 543 ThreadID tid); 544 545 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 546 547 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 548 const VecElem& val, ThreadID tid); 549 550 void setArchCCReg(int reg_idx, RegVal val, ThreadID tid); 551 552 /** Sets the commit PC state of a specific thread. */ 553 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 554 555 /** Reads the commit PC state of a specific thread. */ 556 TheISA::PCState pcState(ThreadID tid); 557 558 /** Reads the commit PC of a specific thread. */ 559 Addr instAddr(ThreadID tid); 560 561 /** Reads the commit micro PC of a specific thread. */ 562 MicroPC microPC(ThreadID tid); 563 564 /** Reads the next PC of a specific thread. */ 565 Addr nextInstAddr(ThreadID tid); 566 567 /** Initiates a squash of all in-flight instructions for a given 568 * thread. The source of the squash is an external update of 569 * state through the TC. 570 */ 571 void squashFromTC(ThreadID tid); 572 573 /** Function to add instruction onto the head of the list of the 574 * instructions. Used when new instructions are fetched. 575 */ 576 ListIt addInst(const DynInstPtr &inst); 577 578 /** Function to tell the CPU that an instruction has completed. */ 579 void instDone(ThreadID tid, const DynInstPtr &inst); 580 581 /** Remove an instruction from the front end of the list. There's 582 * no restriction on location of the instruction. 583 */ 584 void removeFrontInst(const DynInstPtr &inst); 585 586 /** Remove all instructions that are not currently in the ROB. 587 * There's also an option to not squash delay slot instructions.*/ 588 void removeInstsNotInROB(ThreadID tid); 589 590 /** Remove all instructions younger than the given sequence number. */ 591 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 592 593 /** Removes the instruction pointed to by the iterator. */ 594 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 595 596 /** Cleans up all instructions on the remove list. */ 597 void cleanUpRemovedInsts(); 598 599 /** Debug function to print all instructions on the list. */ 600 void dumpInsts(); 601 602 public: 603#ifndef NDEBUG 604 /** Count of total number of dynamic instructions in flight. */ 605 int instcount; 606#endif 607 608 /** List of all the instructions in flight. */ 609 std::list<DynInstPtr> instList; 610 611 /** List of all the instructions that will be removed at the end of this 612 * cycle. 613 */ 614 std::queue<ListIt> removeList; 615 616#ifdef DEBUG 617 /** Debug structure to keep track of the sequence numbers still in 618 * flight. 619 */ 620 std::set<InstSeqNum> snList; 621#endif 622 623 /** Records if instructions need to be removed this cycle due to 624 * being retired or squashed. 625 */ 626 bool removeInstsThisCycle; 627 628 protected: 629 /** The fetch stage. */ 630 typename CPUPolicy::Fetch fetch; 631 632 /** The decode stage. */ 633 typename CPUPolicy::Decode decode; 634 635 /** The dispatch stage. */ 636 typename CPUPolicy::Rename rename; 637 638 /** The issue/execute/writeback stages. */ 639 typename CPUPolicy::IEW iew; 640 641 /** The commit stage. */ 642 typename CPUPolicy::Commit commit; 643 644 /** The rename mode of the vector registers */ 645 Enums::VecRegRenameMode vecMode; 646 647 /** The register file. */ 648 PhysRegFile regFile; 649 650 /** The free list. */ 651 typename CPUPolicy::FreeList freeList; 652 653 /** The rename map. */ 654 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 655 656 /** The commit rename map. */ 657 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 658 659 /** The re-order buffer. */ 660 typename CPUPolicy::ROB rob; 661 662 /** Active Threads List */ 663 std::list<ThreadID> activeThreads; 664 665 /** 666 * This is a list of threads that are trying to exit. Each thread id 667 * is mapped to a boolean value denoting whether the thread is ready 668 * to exit. 669 */ 670 std::unordered_map<ThreadID, bool> exitingThreads; 671 672 /** Integer Register Scoreboard */ 673 Scoreboard scoreboard; 674 675 std::vector<TheISA::ISA *> isa; 676 677 /** Instruction port. Note that it has to appear after the fetch stage. */ 678 IcachePort icachePort; 679 680 /** Data port. Note that it has to appear after the iew stages */ 681 DcachePort dcachePort; 682 683 public: 684 /** Enum to give each stage a specific index, so when calling 685 * activateStage() or deactivateStage(), they can specify which stage 686 * is being activated/deactivated. 687 */ 688 enum StageIdx { 689 FetchIdx, 690 DecodeIdx, 691 RenameIdx, 692 IEWIdx, 693 CommitIdx, 694 NumStages }; 695 696 /** Typedefs from the Impl to get the structs that each of the 697 * time buffers should use. 698 */ 699 typedef typename CPUPolicy::TimeStruct TimeStruct; 700 701 typedef typename CPUPolicy::FetchStruct FetchStruct; 702 703 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 704 705 typedef typename CPUPolicy::RenameStruct RenameStruct; 706 707 typedef typename CPUPolicy::IEWStruct IEWStruct; 708 709 /** The main time buffer to do backwards communication. */ 710 TimeBuffer<TimeStruct> timeBuffer; 711 712 /** The fetch stage's instruction queue. */ 713 TimeBuffer<FetchStruct> fetchQueue; 714 715 /** The decode stage's instruction queue. */ 716 TimeBuffer<DecodeStruct> decodeQueue; 717 718 /** The rename stage's instruction queue. */ 719 TimeBuffer<RenameStruct> renameQueue; 720 721 /** The IEW stage's instruction queue. */ 722 TimeBuffer<IEWStruct> iewQueue; 723 724 private: 725 /** The activity recorder; used to tell if the CPU has any 726 * activity remaining or if it can go to idle and deschedule 727 * itself. 728 */ 729 ActivityRecorder activityRec; 730 731 public: 732 /** Records that there was time buffer activity this cycle. */ 733 void activityThisCycle() { activityRec.activity(); } 734 735 /** Changes a stage's status to active within the activity recorder. */ 736 void activateStage(const StageIdx idx) 737 { activityRec.activateStage(idx); } 738 739 /** Changes a stage's status to inactive within the activity recorder. */ 740 void deactivateStage(const StageIdx idx) 741 { activityRec.deactivateStage(idx); } 742 743 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 744 void wakeCPU(); 745 746 virtual void wakeup(ThreadID tid) override; 747 748 /** Gets a free thread id. Use if thread ids change across system. */ 749 ThreadID getFreeTid(); 750 751 public: 752 /** Returns a pointer to a thread context. */ 753 ThreadContext * 754 tcBase(ThreadID tid) 755 { 756 return thread[tid]->getTC(); 757 } 758 759 /** The global sequence number counter. */ 760 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 761 762 /** Pointer to the checker, which can dynamically verify 763 * instruction results at run time. This can be set to NULL if it 764 * is not being used. 765 */ 766 Checker<Impl> *checker; 767 768 /** Pointer to the system. */ 769 System *system; 770 771 /** Pointers to all of the threads in the CPU. */ 772 std::vector<Thread *> thread; 773 774 /** Threads Scheduled to Enter CPU */ 775 std::list<int> cpuWaitList; 776 777 /** The cycle that the CPU was last running, used for statistics. */ 778 Cycles lastRunningCycle; 779 780 /** The cycle that the CPU was last activated by a new thread*/ 781 Tick lastActivatedCycle; 782 783 /** Mapping for system thread id to cpu id */ 784 std::map<ThreadID, unsigned> threadMap; 785 786 /** Available thread ids in the cpu*/ 787 std::vector<ThreadID> tids; 788 789 /** CPU pushRequest function, forwards request to LSQ. */ 790 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, 791 unsigned int size, Addr addr, Request::Flags flags, 792 uint64_t *res, AtomicOpFunctor *amo_op = nullptr) 793 { 794 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, 795 flags, res, amo_op); 796 } 797 798 /** CPU read function, forwards read to LSQ. */ 799 Fault read(LSQRequest* req, int load_idx) 800 { 801 return this->iew.ldstQueue.read(req, load_idx); 802 } 803 804 /** CPU write function, forwards write to LSQ. */ 805 Fault write(LSQRequest* req, uint8_t *data, int store_idx) 806 { 807 return this->iew.ldstQueue.write(req, data, store_idx); 808 } 809 810 /** Used by the fetch unit to get a hold of the instruction port. */ 811 MasterPort &getInstPort() override { return icachePort; } 812 813 /** Get the dcache port (used to find block size for translations). */ 814 MasterPort &getDataPort() override { return dcachePort; } 815 816 /** Stat for total number of times the CPU is descheduled. */ 817 Stats::Scalar timesIdled; 818 /** Stat for total number of cycles the CPU spends descheduled. */ 819 Stats::Scalar idleCycles; 820 /** Stat for total number of cycles the CPU spends descheduled due to a 821 * quiesce operation or waiting for an interrupt. */ 822 Stats::Scalar quiesceCycles; 823 /** Stat for the number of committed instructions per thread. */ 824 Stats::Vector committedInsts; 825 /** Stat for the number of committed ops (including micro ops) per thread. */ 826 Stats::Vector committedOps; 827 /** Stat for the CPI per thread. */ 828 Stats::Formula cpi; 829 /** Stat for the total CPI. */ 830 Stats::Formula totalCpi; 831 /** Stat for the IPC per thread. */ 832 Stats::Formula ipc; 833 /** Stat for the total IPC. */ 834 Stats::Formula totalIpc; 835 836 //number of integer register file accesses 837 Stats::Scalar intRegfileReads; 838 Stats::Scalar intRegfileWrites; 839 //number of float register file accesses 840 Stats::Scalar fpRegfileReads; 841 Stats::Scalar fpRegfileWrites; 842 //number of vector register file accesses 843 mutable Stats::Scalar vecRegfileReads; 844 Stats::Scalar vecRegfileWrites; 845 //number of predicate register file accesses 846 mutable Stats::Scalar vecPredRegfileReads; 847 Stats::Scalar vecPredRegfileWrites; 848 //number of CC register file accesses 849 Stats::Scalar ccRegfileReads; 850 Stats::Scalar ccRegfileWrites; 851 //number of misc 852 Stats::Scalar miscRegfileReads; 853 Stats::Scalar miscRegfileWrites; 854}; 855 856#endif // __CPU_O3_CPU_HH__ 857