cpu.hh revision 13590:d7e018859709
1/* 2 * Copyright (c) 2011-2013, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/generic/types.hh" 57#include "arch/types.hh" 58#include "base/statistics.hh" 59#include "config/the_isa.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class MemObject; 80class Process; 81 82struct BaseCPUParams; 83 84class BaseO3CPU : public BaseCPU 85{ 86 //Stuff that's pretty ISA independent will go here. 87 public: 88 BaseO3CPU(BaseCPUParams *params); 89 90 void regStats(); 91}; 92 93/** 94 * FullO3CPU class, has each of the stages (fetch through commit) 95 * within it, as well as all of the time buffers between stages. The 96 * tick() function for the CPU is defined here. 97 */ 98template <class Impl> 99class FullO3CPU : public BaseO3CPU 100{ 101 public: 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 110 typedef O3ThreadState<Impl> ImplState; 111 typedef O3ThreadState<Impl> Thread; 112 113 typedef typename std::list<DynInstPtr>::iterator ListIt; 114 115 friend class O3ThreadContext<Impl>; 116 117 public: 118 enum Status { 119 Running, 120 Idle, 121 Halted, 122 Blocked, 123 SwitchedOut 124 }; 125 126 BaseTLB *itb; 127 BaseTLB *dtb; 128 using LSQRequest = typename LSQ<Impl>::LSQRequest; 129 130 /** Overall CPU status. */ 131 Status _status; 132 133 private: 134 135 /** 136 * IcachePort class for instruction fetch. 137 */ 138 class IcachePort : public MasterPort 139 { 140 protected: 141 /** Pointer to fetch. */ 142 DefaultFetch<Impl> *fetch; 143 144 public: 145 /** Default constructor. */ 146 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 147 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 148 { } 149 150 protected: 151 152 /** Timing version of receive. Handles setting fetch to the 153 * proper status to start fetching. */ 154 virtual bool recvTimingResp(PacketPtr pkt); 155 156 /** Handles doing a retry of a failed fetch. */ 157 virtual void recvReqRetry(); 158 }; 159 160 /** 161 * DcachePort class for the load/store queue. 162 */ 163 class DcachePort : public MasterPort 164 { 165 protected: 166 167 /** Pointer to LSQ. */ 168 LSQ<Impl> *lsq; 169 FullO3CPU<Impl> *cpu; 170 171 public: 172 /** Default constructor. */ 173 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 174 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 175 cpu(_cpu) 176 { } 177 178 protected: 179 180 /** Timing version of receive. Handles writing back and 181 * completing the load or store that has returned from 182 * memory. */ 183 virtual bool recvTimingResp(PacketPtr pkt); 184 virtual void recvTimingSnoopReq(PacketPtr pkt); 185 186 virtual void recvFunctionalSnoop(PacketPtr pkt) 187 { 188 // @todo: Is there a need for potential invalidation here? 189 } 190 191 /** Handles doing a retry of the previous send. */ 192 virtual void recvReqRetry(); 193 194 /** 195 * As this CPU requires snooping to maintain the load store queue 196 * change the behaviour from the base CPU port. 197 * 198 * @return true since we have to snoop 199 */ 200 virtual bool isSnooping() const { return true; } 201 }; 202 203 /** The tick event used for scheduling CPU ticks. */ 204 EventFunctionWrapper tickEvent; 205 206 /** Schedule tick event, regardless of its current state. */ 207 void scheduleTickEvent(Cycles delay) 208 { 209 if (tickEvent.squashed()) 210 reschedule(tickEvent, clockEdge(delay)); 211 else if (!tickEvent.scheduled()) 212 schedule(tickEvent, clockEdge(delay)); 213 } 214 215 /** Unschedule tick event, regardless of its current state. */ 216 void unscheduleTickEvent() 217 { 218 if (tickEvent.scheduled()) 219 tickEvent.squash(); 220 } 221 222 /** 223 * Check if the pipeline has drained and signal drain done. 224 * 225 * This method checks if a drain has been requested and if the CPU 226 * has drained successfully (i.e., there are no instructions in 227 * the pipeline). If the CPU has drained, it deschedules the tick 228 * event and signals the drain manager. 229 * 230 * @return False if a drain hasn't been requested or the CPU 231 * hasn't drained, true otherwise. 232 */ 233 bool tryDrain(); 234 235 /** 236 * Perform sanity checks after a drain. 237 * 238 * This method is called from drain() when it has determined that 239 * the CPU is fully drained when gem5 is compiled with the NDEBUG 240 * macro undefined. The intention of this method is to do more 241 * extensive tests than the isDrained() method to weed out any 242 * draining bugs. 243 */ 244 void drainSanityCheck() const; 245 246 /** Check if a system is in a drained state. */ 247 bool isDrained() const; 248 249 public: 250 /** Constructs a CPU with the given parameters. */ 251 FullO3CPU(DerivO3CPUParams *params); 252 /** Destructor. */ 253 ~FullO3CPU(); 254 255 /** Registers statistics. */ 256 void regStats() override; 257 258 ProbePointArg<PacketPtr> *ppInstAccessComplete; 259 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 260 261 /** Register probe points. */ 262 void regProbePoints() override; 263 264 void demapPage(Addr vaddr, uint64_t asn) 265 { 266 this->itb->demapPage(vaddr, asn); 267 this->dtb->demapPage(vaddr, asn); 268 } 269 270 void demapInstPage(Addr vaddr, uint64_t asn) 271 { 272 this->itb->demapPage(vaddr, asn); 273 } 274 275 void demapDataPage(Addr vaddr, uint64_t asn) 276 { 277 this->dtb->demapPage(vaddr, asn); 278 } 279 280 /** Ticks CPU, calling tick() on each stage, and checking the overall 281 * activity to see if the CPU should deschedule itself. 282 */ 283 void tick(); 284 285 /** Initialize the CPU */ 286 void init() override; 287 288 void startup() override; 289 290 /** Returns the Number of Active Threads in the CPU */ 291 int numActiveThreads() 292 { return activeThreads.size(); } 293 294 /** Add Thread to Active Threads List */ 295 void activateThread(ThreadID tid); 296 297 /** Remove Thread from Active Threads List */ 298 void deactivateThread(ThreadID tid); 299 300 /** Setup CPU to insert a thread's context */ 301 void insertThread(ThreadID tid); 302 303 /** Remove all of a thread's context from CPU */ 304 void removeThread(ThreadID tid); 305 306 /** Count the Total Instructions Committed in the CPU. */ 307 Counter totalInsts() const override; 308 309 /** Count the Total Ops (including micro ops) committed in the CPU. */ 310 Counter totalOps() const override; 311 312 /** Add Thread to Active Threads List. */ 313 void activateContext(ThreadID tid) override; 314 315 /** Remove Thread from Active Threads List */ 316 void suspendContext(ThreadID tid) override; 317 318 /** Remove Thread from Active Threads List && 319 * Remove Thread Context from CPU. 320 */ 321 void haltContext(ThreadID tid) override; 322 323 /** Update The Order In Which We Process Threads. */ 324 void updateThreadPriority(); 325 326 /** Is the CPU draining? */ 327 bool isDraining() const { return drainState() == DrainState::Draining; } 328 329 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 330 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 331 332 public: 333 /** Executes a syscall. 334 * @todo: Determine if this needs to be virtual. 335 */ 336 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 337 338 /** Starts draining the CPU's pipeline of all instructions in 339 * order to stop all memory accesses. */ 340 DrainState drain() override; 341 342 /** Resumes execution after a drain. */ 343 void drainResume() override; 344 345 /** 346 * Commit has reached a safe point to drain a thread. 347 * 348 * Commit calls this method to inform the pipeline that it has 349 * reached a point where it is not executed microcode and is about 350 * to squash uncommitted instructions to fully drain the pipeline. 351 */ 352 void commitDrained(ThreadID tid); 353 354 /** Switches out this CPU. */ 355 void switchOut() override; 356 357 /** Takes over from another CPU. */ 358 void takeOverFrom(BaseCPU *oldCPU) override; 359 360 void verifyMemoryMode() const override; 361 362 /** Get the current instruction sequence number, and increment it. */ 363 InstSeqNum getAndIncrementInstSeq() 364 { return globalSeqNum++; } 365 366 /** Traps to handle given fault. */ 367 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 368 369 /** HW return from error interrupt. */ 370 Fault hwrei(ThreadID tid); 371 372 bool simPalCheck(int palFunc, ThreadID tid); 373 374 /** Returns the Fault for any valid interrupt. */ 375 Fault getInterrupts(); 376 377 /** Processes any an interrupt fault. */ 378 void processInterrupts(const Fault &interrupt); 379 380 /** Halts the CPU. */ 381 void halt() { panic("Halt not implemented!\n"); } 382 383 /** Register accessors. Index refers to the physical register index. */ 384 385 /** Reads a miscellaneous register. */ 386 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 387 388 /** Reads a misc. register, including any side effects the read 389 * might have as defined by the architecture. 390 */ 391 RegVal readMiscReg(int misc_reg, ThreadID tid); 392 393 /** Sets a miscellaneous register. */ 394 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 395 396 /** Sets a misc. register, including any side effects the write 397 * might have as defined by the architecture. 398 */ 399 void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 400 401 RegVal readIntReg(PhysRegIdPtr phys_reg); 402 403 RegVal readFloatRegBits(PhysRegIdPtr phys_reg); 404 405 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 406 407 /** 408 * Read physical vector register for modification. 409 */ 410 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 411 412 /** 413 * Read physical vector register lane 414 */ 415 template<typename VecElem, int LaneIdx> 416 VecLaneT<VecElem, true> 417 readVecLane(PhysRegIdPtr phys_reg) const 418 { 419 vecRegfileReads++; 420 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 421 } 422 423 /** 424 * Read physical vector register lane 425 */ 426 template<typename VecElem> 427 VecLaneT<VecElem, true> 428 readVecLane(PhysRegIdPtr phys_reg) const 429 { 430 vecRegfileReads++; 431 return regFile.readVecLane<VecElem>(phys_reg); 432 } 433 434 /** Write a lane of the destination vector register. */ 435 template<typename LD> 436 void 437 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 438 { 439 vecRegfileWrites++; 440 return regFile.setVecLane(phys_reg, val); 441 } 442 443 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 444 445 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 446 447 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 448 449 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); 450 451 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 452 453 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 454 455 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 456 457 RegVal readArchIntReg(int reg_idx, ThreadID tid); 458 459 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); 460 461 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 462 /** Read architectural vector register for modification. */ 463 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 464 465 /** Read architectural vector register lane. */ 466 template<typename VecElem> 467 VecLaneT<VecElem, true> 468 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 469 { 470 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 471 RegId(VecRegClass, reg_idx)); 472 return readVecLane<VecElem>(phys_reg); 473 } 474 475 476 /** Write a lane of the destination vector register. */ 477 template<typename LD> 478 void 479 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 480 { 481 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 482 RegId(VecRegClass, reg_idx)); 483 setVecLane(phys_reg, val); 484 } 485 486 const VecElem& readArchVecElem(const RegIndex& reg_idx, 487 const ElemIndex& ldx, ThreadID tid) const; 488 489 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 490 491 /** Architectural register accessors. Looks up in the commit 492 * rename table to obtain the true physical index of the 493 * architected register first, then accesses that physical 494 * register. 495 */ 496 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 497 498 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); 499 500 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 501 502 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 503 const VecElem& val, ThreadID tid); 504 505 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 506 507 /** Sets the commit PC state of a specific thread. */ 508 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 509 510 /** Reads the commit PC state of a specific thread. */ 511 TheISA::PCState pcState(ThreadID tid); 512 513 /** Reads the commit PC of a specific thread. */ 514 Addr instAddr(ThreadID tid); 515 516 /** Reads the commit micro PC of a specific thread. */ 517 MicroPC microPC(ThreadID tid); 518 519 /** Reads the next PC of a specific thread. */ 520 Addr nextInstAddr(ThreadID tid); 521 522 /** Initiates a squash of all in-flight instructions for a given 523 * thread. The source of the squash is an external update of 524 * state through the TC. 525 */ 526 void squashFromTC(ThreadID tid); 527 528 /** Function to add instruction onto the head of the list of the 529 * instructions. Used when new instructions are fetched. 530 */ 531 ListIt addInst(const DynInstPtr &inst); 532 533 /** Function to tell the CPU that an instruction has completed. */ 534 void instDone(ThreadID tid, const DynInstPtr &inst); 535 536 /** Remove an instruction from the front end of the list. There's 537 * no restriction on location of the instruction. 538 */ 539 void removeFrontInst(const DynInstPtr &inst); 540 541 /** Remove all instructions that are not currently in the ROB. 542 * There's also an option to not squash delay slot instructions.*/ 543 void removeInstsNotInROB(ThreadID tid); 544 545 /** Remove all instructions younger than the given sequence number. */ 546 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 547 548 /** Removes the instruction pointed to by the iterator. */ 549 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 550 551 /** Cleans up all instructions on the remove list. */ 552 void cleanUpRemovedInsts(); 553 554 /** Debug function to print all instructions on the list. */ 555 void dumpInsts(); 556 557 public: 558#ifndef NDEBUG 559 /** Count of total number of dynamic instructions in flight. */ 560 int instcount; 561#endif 562 563 /** List of all the instructions in flight. */ 564 std::list<DynInstPtr> instList; 565 566 /** List of all the instructions that will be removed at the end of this 567 * cycle. 568 */ 569 std::queue<ListIt> removeList; 570 571#ifdef DEBUG 572 /** Debug structure to keep track of the sequence numbers still in 573 * flight. 574 */ 575 std::set<InstSeqNum> snList; 576#endif 577 578 /** Records if instructions need to be removed this cycle due to 579 * being retired or squashed. 580 */ 581 bool removeInstsThisCycle; 582 583 protected: 584 /** The fetch stage. */ 585 typename CPUPolicy::Fetch fetch; 586 587 /** The decode stage. */ 588 typename CPUPolicy::Decode decode; 589 590 /** The dispatch stage. */ 591 typename CPUPolicy::Rename rename; 592 593 /** The issue/execute/writeback stages. */ 594 typename CPUPolicy::IEW iew; 595 596 /** The commit stage. */ 597 typename CPUPolicy::Commit commit; 598 599 /** The rename mode of the vector registers */ 600 Enums::VecRegRenameMode vecMode; 601 602 /** The register file. */ 603 PhysRegFile regFile; 604 605 /** The free list. */ 606 typename CPUPolicy::FreeList freeList; 607 608 /** The rename map. */ 609 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 610 611 /** The commit rename map. */ 612 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 613 614 /** The re-order buffer. */ 615 typename CPUPolicy::ROB rob; 616 617 /** Active Threads List */ 618 std::list<ThreadID> activeThreads; 619 620 /** Integer Register Scoreboard */ 621 Scoreboard scoreboard; 622 623 std::vector<TheISA::ISA *> isa; 624 625 /** Instruction port. Note that it has to appear after the fetch stage. */ 626 IcachePort icachePort; 627 628 /** Data port. Note that it has to appear after the iew stages */ 629 DcachePort dcachePort; 630 631 public: 632 /** Enum to give each stage a specific index, so when calling 633 * activateStage() or deactivateStage(), they can specify which stage 634 * is being activated/deactivated. 635 */ 636 enum StageIdx { 637 FetchIdx, 638 DecodeIdx, 639 RenameIdx, 640 IEWIdx, 641 CommitIdx, 642 NumStages }; 643 644 /** Typedefs from the Impl to get the structs that each of the 645 * time buffers should use. 646 */ 647 typedef typename CPUPolicy::TimeStruct TimeStruct; 648 649 typedef typename CPUPolicy::FetchStruct FetchStruct; 650 651 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 652 653 typedef typename CPUPolicy::RenameStruct RenameStruct; 654 655 typedef typename CPUPolicy::IEWStruct IEWStruct; 656 657 /** The main time buffer to do backwards communication. */ 658 TimeBuffer<TimeStruct> timeBuffer; 659 660 /** The fetch stage's instruction queue. */ 661 TimeBuffer<FetchStruct> fetchQueue; 662 663 /** The decode stage's instruction queue. */ 664 TimeBuffer<DecodeStruct> decodeQueue; 665 666 /** The rename stage's instruction queue. */ 667 TimeBuffer<RenameStruct> renameQueue; 668 669 /** The IEW stage's instruction queue. */ 670 TimeBuffer<IEWStruct> iewQueue; 671 672 private: 673 /** The activity recorder; used to tell if the CPU has any 674 * activity remaining or if it can go to idle and deschedule 675 * itself. 676 */ 677 ActivityRecorder activityRec; 678 679 public: 680 /** Records that there was time buffer activity this cycle. */ 681 void activityThisCycle() { activityRec.activity(); } 682 683 /** Changes a stage's status to active within the activity recorder. */ 684 void activateStage(const StageIdx idx) 685 { activityRec.activateStage(idx); } 686 687 /** Changes a stage's status to inactive within the activity recorder. */ 688 void deactivateStage(const StageIdx idx) 689 { activityRec.deactivateStage(idx); } 690 691 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 692 void wakeCPU(); 693 694 virtual void wakeup(ThreadID tid) override; 695 696 /** Gets a free thread id. Use if thread ids change across system. */ 697 ThreadID getFreeTid(); 698 699 public: 700 /** Returns a pointer to a thread context. */ 701 ThreadContext * 702 tcBase(ThreadID tid) 703 { 704 return thread[tid]->getTC(); 705 } 706 707 /** The global sequence number counter. */ 708 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 709 710 /** Pointer to the checker, which can dynamically verify 711 * instruction results at run time. This can be set to NULL if it 712 * is not being used. 713 */ 714 Checker<Impl> *checker; 715 716 /** Pointer to the system. */ 717 System *system; 718 719 /** Pointers to all of the threads in the CPU. */ 720 std::vector<Thread *> thread; 721 722 /** Threads Scheduled to Enter CPU */ 723 std::list<int> cpuWaitList; 724 725 /** The cycle that the CPU was last running, used for statistics. */ 726 Cycles lastRunningCycle; 727 728 /** The cycle that the CPU was last activated by a new thread*/ 729 Tick lastActivatedCycle; 730 731 /** Mapping for system thread id to cpu id */ 732 std::map<ThreadID, unsigned> threadMap; 733 734 /** Available thread ids in the cpu*/ 735 std::vector<ThreadID> tids; 736 737 /** CPU pushRequest function, forwards request to LSQ. */ 738 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, 739 unsigned int size, Addr addr, Request::Flags flags, 740 uint64_t *res) 741 { 742 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, 743 flags, res); 744 } 745 746 /** CPU read function, forwards read to LSQ. */ 747 Fault read(LSQRequest* req, int load_idx) 748 { 749 return this->iew.ldstQueue.read(req, load_idx); 750 } 751 752 /** CPU write function, forwards write to LSQ. */ 753 Fault write(LSQRequest* req, uint8_t *data, int store_idx) 754 { 755 return this->iew.ldstQueue.write(req, data, store_idx); 756 } 757 758 /** Used by the fetch unit to get a hold of the instruction port. */ 759 MasterPort &getInstPort() override { return icachePort; } 760 761 /** Get the dcache port (used to find block size for translations). */ 762 MasterPort &getDataPort() override { return dcachePort; } 763 764 /** Stat for total number of times the CPU is descheduled. */ 765 Stats::Scalar timesIdled; 766 /** Stat for total number of cycles the CPU spends descheduled. */ 767 Stats::Scalar idleCycles; 768 /** Stat for total number of cycles the CPU spends descheduled due to a 769 * quiesce operation or waiting for an interrupt. */ 770 Stats::Scalar quiesceCycles; 771 /** Stat for the number of committed instructions per thread. */ 772 Stats::Vector committedInsts; 773 /** Stat for the number of committed ops (including micro ops) per thread. */ 774 Stats::Vector committedOps; 775 /** Stat for the CPI per thread. */ 776 Stats::Formula cpi; 777 /** Stat for the total CPI. */ 778 Stats::Formula totalCpi; 779 /** Stat for the IPC per thread. */ 780 Stats::Formula ipc; 781 /** Stat for the total IPC. */ 782 Stats::Formula totalIpc; 783 784 //number of integer register file accesses 785 Stats::Scalar intRegfileReads; 786 Stats::Scalar intRegfileWrites; 787 //number of float register file accesses 788 Stats::Scalar fpRegfileReads; 789 Stats::Scalar fpRegfileWrites; 790 //number of vector register file accesses 791 mutable Stats::Scalar vecRegfileReads; 792 Stats::Scalar vecRegfileWrites; 793 //number of CC register file accesses 794 Stats::Scalar ccRegfileReads; 795 Stats::Scalar ccRegfileWrites; 796 //number of misc 797 Stats::Scalar miscRegfileReads; 798 Stats::Scalar miscRegfileWrites; 799}; 800 801#endif // __CPU_O3_CPU_HH__ 802