cpu.hh revision 13582:989577bf6abc
1/* 2 * Copyright (c) 2011-2013, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/generic/types.hh" 57#include "arch/types.hh" 58#include "base/statistics.hh" 59#include "config/the_isa.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class MemObject; 80class Process; 81 82struct BaseCPUParams; 83 84class BaseO3CPU : public BaseCPU 85{ 86 //Stuff that's pretty ISA independent will go here. 87 public: 88 BaseO3CPU(BaseCPUParams *params); 89 90 void regStats(); 91}; 92 93/** 94 * FullO3CPU class, has each of the stages (fetch through commit) 95 * within it, as well as all of the time buffers between stages. The 96 * tick() function for the CPU is defined here. 97 */ 98template <class Impl> 99class FullO3CPU : public BaseO3CPU 100{ 101 public: 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 110 typedef O3ThreadState<Impl> ImplState; 111 typedef O3ThreadState<Impl> Thread; 112 113 typedef typename std::list<DynInstPtr>::iterator ListIt; 114 115 friend class O3ThreadContext<Impl>; 116 117 public: 118 enum Status { 119 Running, 120 Idle, 121 Halted, 122 Blocked, 123 SwitchedOut 124 }; 125 126 BaseTLB *itb; 127 BaseTLB *dtb; 128 129 /** Overall CPU status. */ 130 Status _status; 131 132 private: 133 134 /** 135 * IcachePort class for instruction fetch. 136 */ 137 class IcachePort : public MasterPort 138 { 139 protected: 140 /** Pointer to fetch. */ 141 DefaultFetch<Impl> *fetch; 142 143 public: 144 /** Default constructor. */ 145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 146 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 147 { } 148 149 protected: 150 151 /** Timing version of receive. Handles setting fetch to the 152 * proper status to start fetching. */ 153 virtual bool recvTimingResp(PacketPtr pkt); 154 155 /** Handles doing a retry of a failed fetch. */ 156 virtual void recvReqRetry(); 157 }; 158 159 /** 160 * DcachePort class for the load/store queue. 161 */ 162 class DcachePort : public MasterPort 163 { 164 protected: 165 166 /** Pointer to LSQ. */ 167 LSQ<Impl> *lsq; 168 FullO3CPU<Impl> *cpu; 169 170 public: 171 /** Default constructor. */ 172 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 173 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 174 cpu(_cpu) 175 { } 176 177 protected: 178 179 /** Timing version of receive. Handles writing back and 180 * completing the load or store that has returned from 181 * memory. */ 182 virtual bool recvTimingResp(PacketPtr pkt); 183 virtual void recvTimingSnoopReq(PacketPtr pkt); 184 185 virtual void recvFunctionalSnoop(PacketPtr pkt) 186 { 187 // @todo: Is there a need for potential invalidation here? 188 } 189 190 /** Handles doing a retry of the previous send. */ 191 virtual void recvReqRetry(); 192 193 /** 194 * As this CPU requires snooping to maintain the load store queue 195 * change the behaviour from the base CPU port. 196 * 197 * @return true since we have to snoop 198 */ 199 virtual bool isSnooping() const { return true; } 200 }; 201 202 /** The tick event used for scheduling CPU ticks. */ 203 EventFunctionWrapper tickEvent; 204 205 /** Schedule tick event, regardless of its current state. */ 206 void scheduleTickEvent(Cycles delay) 207 { 208 if (tickEvent.squashed()) 209 reschedule(tickEvent, clockEdge(delay)); 210 else if (!tickEvent.scheduled()) 211 schedule(tickEvent, clockEdge(delay)); 212 } 213 214 /** Unschedule tick event, regardless of its current state. */ 215 void unscheduleTickEvent() 216 { 217 if (tickEvent.scheduled()) 218 tickEvent.squash(); 219 } 220 221 /** 222 * Check if the pipeline has drained and signal drain done. 223 * 224 * This method checks if a drain has been requested and if the CPU 225 * has drained successfully (i.e., there are no instructions in 226 * the pipeline). If the CPU has drained, it deschedules the tick 227 * event and signals the drain manager. 228 * 229 * @return False if a drain hasn't been requested or the CPU 230 * hasn't drained, true otherwise. 231 */ 232 bool tryDrain(); 233 234 /** 235 * Perform sanity checks after a drain. 236 * 237 * This method is called from drain() when it has determined that 238 * the CPU is fully drained when gem5 is compiled with the NDEBUG 239 * macro undefined. The intention of this method is to do more 240 * extensive tests than the isDrained() method to weed out any 241 * draining bugs. 242 */ 243 void drainSanityCheck() const; 244 245 /** Check if a system is in a drained state. */ 246 bool isDrained() const; 247 248 public: 249 /** Constructs a CPU with the given parameters. */ 250 FullO3CPU(DerivO3CPUParams *params); 251 /** Destructor. */ 252 ~FullO3CPU(); 253 254 /** Registers statistics. */ 255 void regStats() override; 256 257 ProbePointArg<PacketPtr> *ppInstAccessComplete; 258 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 259 260 /** Register probe points. */ 261 void regProbePoints() override; 262 263 void demapPage(Addr vaddr, uint64_t asn) 264 { 265 this->itb->demapPage(vaddr, asn); 266 this->dtb->demapPage(vaddr, asn); 267 } 268 269 void demapInstPage(Addr vaddr, uint64_t asn) 270 { 271 this->itb->demapPage(vaddr, asn); 272 } 273 274 void demapDataPage(Addr vaddr, uint64_t asn) 275 { 276 this->dtb->demapPage(vaddr, asn); 277 } 278 279 /** Ticks CPU, calling tick() on each stage, and checking the overall 280 * activity to see if the CPU should deschedule itself. 281 */ 282 void tick(); 283 284 /** Initialize the CPU */ 285 void init() override; 286 287 void startup() override; 288 289 /** Returns the Number of Active Threads in the CPU */ 290 int numActiveThreads() 291 { return activeThreads.size(); } 292 293 /** Add Thread to Active Threads List */ 294 void activateThread(ThreadID tid); 295 296 /** Remove Thread from Active Threads List */ 297 void deactivateThread(ThreadID tid); 298 299 /** Setup CPU to insert a thread's context */ 300 void insertThread(ThreadID tid); 301 302 /** Remove all of a thread's context from CPU */ 303 void removeThread(ThreadID tid); 304 305 /** Count the Total Instructions Committed in the CPU. */ 306 Counter totalInsts() const override; 307 308 /** Count the Total Ops (including micro ops) committed in the CPU. */ 309 Counter totalOps() const override; 310 311 /** Add Thread to Active Threads List. */ 312 void activateContext(ThreadID tid) override; 313 314 /** Remove Thread from Active Threads List */ 315 void suspendContext(ThreadID tid) override; 316 317 /** Remove Thread from Active Threads List && 318 * Remove Thread Context from CPU. 319 */ 320 void haltContext(ThreadID tid) override; 321 322 /** Update The Order In Which We Process Threads. */ 323 void updateThreadPriority(); 324 325 /** Is the CPU draining? */ 326 bool isDraining() const { return drainState() == DrainState::Draining; } 327 328 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 329 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 330 331 public: 332 /** Executes a syscall. 333 * @todo: Determine if this needs to be virtual. 334 */ 335 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 336 337 /** Starts draining the CPU's pipeline of all instructions in 338 * order to stop all memory accesses. */ 339 DrainState drain() override; 340 341 /** Resumes execution after a drain. */ 342 void drainResume() override; 343 344 /** 345 * Commit has reached a safe point to drain a thread. 346 * 347 * Commit calls this method to inform the pipeline that it has 348 * reached a point where it is not executed microcode and is about 349 * to squash uncommitted instructions to fully drain the pipeline. 350 */ 351 void commitDrained(ThreadID tid); 352 353 /** Switches out this CPU. */ 354 void switchOut() override; 355 356 /** Takes over from another CPU. */ 357 void takeOverFrom(BaseCPU *oldCPU) override; 358 359 void verifyMemoryMode() const override; 360 361 /** Get the current instruction sequence number, and increment it. */ 362 InstSeqNum getAndIncrementInstSeq() 363 { return globalSeqNum++; } 364 365 /** Traps to handle given fault. */ 366 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 367 368 /** HW return from error interrupt. */ 369 Fault hwrei(ThreadID tid); 370 371 bool simPalCheck(int palFunc, ThreadID tid); 372 373 /** Returns the Fault for any valid interrupt. */ 374 Fault getInterrupts(); 375 376 /** Processes any an interrupt fault. */ 377 void processInterrupts(const Fault &interrupt); 378 379 /** Halts the CPU. */ 380 void halt() { panic("Halt not implemented!\n"); } 381 382 /** Register accessors. Index refers to the physical register index. */ 383 384 /** Reads a miscellaneous register. */ 385 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 386 387 /** Reads a misc. register, including any side effects the read 388 * might have as defined by the architecture. 389 */ 390 RegVal readMiscReg(int misc_reg, ThreadID tid); 391 392 /** Sets a miscellaneous register. */ 393 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 394 395 /** Sets a misc. register, including any side effects the write 396 * might have as defined by the architecture. 397 */ 398 void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 399 400 RegVal readIntReg(PhysRegIdPtr phys_reg); 401 402 RegVal readFloatRegBits(PhysRegIdPtr phys_reg); 403 404 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 405 406 /** 407 * Read physical vector register for modification. 408 */ 409 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 410 411 /** 412 * Read physical vector register lane 413 */ 414 template<typename VecElem, int LaneIdx> 415 VecLaneT<VecElem, true> 416 readVecLane(PhysRegIdPtr phys_reg) const 417 { 418 vecRegfileReads++; 419 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 420 } 421 422 /** 423 * Read physical vector register lane 424 */ 425 template<typename VecElem> 426 VecLaneT<VecElem, true> 427 readVecLane(PhysRegIdPtr phys_reg) const 428 { 429 vecRegfileReads++; 430 return regFile.readVecLane<VecElem>(phys_reg); 431 } 432 433 /** Write a lane of the destination vector register. */ 434 template<typename LD> 435 void 436 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 437 { 438 vecRegfileWrites++; 439 return regFile.setVecLane(phys_reg, val); 440 } 441 442 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 443 444 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 445 446 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 447 448 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); 449 450 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 451 452 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 453 454 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 455 456 RegVal readArchIntReg(int reg_idx, ThreadID tid); 457 458 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); 459 460 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 461 /** Read architectural vector register for modification. */ 462 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 463 464 /** Read architectural vector register lane. */ 465 template<typename VecElem> 466 VecLaneT<VecElem, true> 467 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 468 { 469 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 470 RegId(VecRegClass, reg_idx)); 471 return readVecLane<VecElem>(phys_reg); 472 } 473 474 475 /** Write a lane of the destination vector register. */ 476 template<typename LD> 477 void 478 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 479 { 480 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 481 RegId(VecRegClass, reg_idx)); 482 setVecLane(phys_reg, val); 483 } 484 485 const VecElem& readArchVecElem(const RegIndex& reg_idx, 486 const ElemIndex& ldx, ThreadID tid) const; 487 488 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 489 490 /** Architectural register accessors. Looks up in the commit 491 * rename table to obtain the true physical index of the 492 * architected register first, then accesses that physical 493 * register. 494 */ 495 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 496 497 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); 498 499 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 500 501 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 502 const VecElem& val, ThreadID tid); 503 504 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 505 506 /** Sets the commit PC state of a specific thread. */ 507 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 508 509 /** Reads the commit PC state of a specific thread. */ 510 TheISA::PCState pcState(ThreadID tid); 511 512 /** Reads the commit PC of a specific thread. */ 513 Addr instAddr(ThreadID tid); 514 515 /** Reads the commit micro PC of a specific thread. */ 516 MicroPC microPC(ThreadID tid); 517 518 /** Reads the next PC of a specific thread. */ 519 Addr nextInstAddr(ThreadID tid); 520 521 /** Initiates a squash of all in-flight instructions for a given 522 * thread. The source of the squash is an external update of 523 * state through the TC. 524 */ 525 void squashFromTC(ThreadID tid); 526 527 /** Function to add instruction onto the head of the list of the 528 * instructions. Used when new instructions are fetched. 529 */ 530 ListIt addInst(const DynInstPtr &inst); 531 532 /** Function to tell the CPU that an instruction has completed. */ 533 void instDone(ThreadID tid, const DynInstPtr &inst); 534 535 /** Remove an instruction from the front end of the list. There's 536 * no restriction on location of the instruction. 537 */ 538 void removeFrontInst(const DynInstPtr &inst); 539 540 /** Remove all instructions that are not currently in the ROB. 541 * There's also an option to not squash delay slot instructions.*/ 542 void removeInstsNotInROB(ThreadID tid); 543 544 /** Remove all instructions younger than the given sequence number. */ 545 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 546 547 /** Removes the instruction pointed to by the iterator. */ 548 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 549 550 /** Cleans up all instructions on the remove list. */ 551 void cleanUpRemovedInsts(); 552 553 /** Debug function to print all instructions on the list. */ 554 void dumpInsts(); 555 556 public: 557#ifndef NDEBUG 558 /** Count of total number of dynamic instructions in flight. */ 559 int instcount; 560#endif 561 562 /** List of all the instructions in flight. */ 563 std::list<DynInstPtr> instList; 564 565 /** List of all the instructions that will be removed at the end of this 566 * cycle. 567 */ 568 std::queue<ListIt> removeList; 569 570#ifdef DEBUG 571 /** Debug structure to keep track of the sequence numbers still in 572 * flight. 573 */ 574 std::set<InstSeqNum> snList; 575#endif 576 577 /** Records if instructions need to be removed this cycle due to 578 * being retired or squashed. 579 */ 580 bool removeInstsThisCycle; 581 582 protected: 583 /** The fetch stage. */ 584 typename CPUPolicy::Fetch fetch; 585 586 /** The decode stage. */ 587 typename CPUPolicy::Decode decode; 588 589 /** The dispatch stage. */ 590 typename CPUPolicy::Rename rename; 591 592 /** The issue/execute/writeback stages. */ 593 typename CPUPolicy::IEW iew; 594 595 /** The commit stage. */ 596 typename CPUPolicy::Commit commit; 597 598 /** The rename mode of the vector registers */ 599 Enums::VecRegRenameMode vecMode; 600 601 /** The register file. */ 602 PhysRegFile regFile; 603 604 /** The free list. */ 605 typename CPUPolicy::FreeList freeList; 606 607 /** The rename map. */ 608 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 609 610 /** The commit rename map. */ 611 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 612 613 /** The re-order buffer. */ 614 typename CPUPolicy::ROB rob; 615 616 /** Active Threads List */ 617 std::list<ThreadID> activeThreads; 618 619 /** Integer Register Scoreboard */ 620 Scoreboard scoreboard; 621 622 std::vector<TheISA::ISA *> isa; 623 624 /** Instruction port. Note that it has to appear after the fetch stage. */ 625 IcachePort icachePort; 626 627 /** Data port. Note that it has to appear after the iew stages */ 628 DcachePort dcachePort; 629 630 public: 631 /** Enum to give each stage a specific index, so when calling 632 * activateStage() or deactivateStage(), they can specify which stage 633 * is being activated/deactivated. 634 */ 635 enum StageIdx { 636 FetchIdx, 637 DecodeIdx, 638 RenameIdx, 639 IEWIdx, 640 CommitIdx, 641 NumStages }; 642 643 /** Typedefs from the Impl to get the structs that each of the 644 * time buffers should use. 645 */ 646 typedef typename CPUPolicy::TimeStruct TimeStruct; 647 648 typedef typename CPUPolicy::FetchStruct FetchStruct; 649 650 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 651 652 typedef typename CPUPolicy::RenameStruct RenameStruct; 653 654 typedef typename CPUPolicy::IEWStruct IEWStruct; 655 656 /** The main time buffer to do backwards communication. */ 657 TimeBuffer<TimeStruct> timeBuffer; 658 659 /** The fetch stage's instruction queue. */ 660 TimeBuffer<FetchStruct> fetchQueue; 661 662 /** The decode stage's instruction queue. */ 663 TimeBuffer<DecodeStruct> decodeQueue; 664 665 /** The rename stage's instruction queue. */ 666 TimeBuffer<RenameStruct> renameQueue; 667 668 /** The IEW stage's instruction queue. */ 669 TimeBuffer<IEWStruct> iewQueue; 670 671 private: 672 /** The activity recorder; used to tell if the CPU has any 673 * activity remaining or if it can go to idle and deschedule 674 * itself. 675 */ 676 ActivityRecorder activityRec; 677 678 public: 679 /** Records that there was time buffer activity this cycle. */ 680 void activityThisCycle() { activityRec.activity(); } 681 682 /** Changes a stage's status to active within the activity recorder. */ 683 void activateStage(const StageIdx idx) 684 { activityRec.activateStage(idx); } 685 686 /** Changes a stage's status to inactive within the activity recorder. */ 687 void deactivateStage(const StageIdx idx) 688 { activityRec.deactivateStage(idx); } 689 690 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 691 void wakeCPU(); 692 693 virtual void wakeup(ThreadID tid) override; 694 695 /** Gets a free thread id. Use if thread ids change across system. */ 696 ThreadID getFreeTid(); 697 698 public: 699 /** Returns a pointer to a thread context. */ 700 ThreadContext * 701 tcBase(ThreadID tid) 702 { 703 return thread[tid]->getTC(); 704 } 705 706 /** The global sequence number counter. */ 707 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 708 709 /** Pointer to the checker, which can dynamically verify 710 * instruction results at run time. This can be set to NULL if it 711 * is not being used. 712 */ 713 Checker<Impl> *checker; 714 715 /** Pointer to the system. */ 716 System *system; 717 718 /** Pointers to all of the threads in the CPU. */ 719 std::vector<Thread *> thread; 720 721 /** Threads Scheduled to Enter CPU */ 722 std::list<int> cpuWaitList; 723 724 /** The cycle that the CPU was last running, used for statistics. */ 725 Cycles lastRunningCycle; 726 727 /** The cycle that the CPU was last activated by a new thread*/ 728 Tick lastActivatedCycle; 729 730 /** Mapping for system thread id to cpu id */ 731 std::map<ThreadID, unsigned> threadMap; 732 733 /** Available thread ids in the cpu*/ 734 std::vector<ThreadID> tids; 735 736 /** CPU read function, forwards read to LSQ. */ 737 Fault read(const RequestPtr &req, 738 RequestPtr &sreqLow, RequestPtr &sreqHigh, 739 int load_idx) 740 { 741 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 742 } 743 744 /** CPU write function, forwards write to LSQ. */ 745 Fault write(const RequestPtr &req, 746 const RequestPtr &sreqLow, const RequestPtr &sreqHigh, 747 uint8_t *data, int store_idx) 748 { 749 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 750 data, store_idx); 751 } 752 753 /** Used by the fetch unit to get a hold of the instruction port. */ 754 MasterPort &getInstPort() override { return icachePort; } 755 756 /** Get the dcache port (used to find block size for translations). */ 757 MasterPort &getDataPort() override { return dcachePort; } 758 759 /** Stat for total number of times the CPU is descheduled. */ 760 Stats::Scalar timesIdled; 761 /** Stat for total number of cycles the CPU spends descheduled. */ 762 Stats::Scalar idleCycles; 763 /** Stat for total number of cycles the CPU spends descheduled due to a 764 * quiesce operation or waiting for an interrupt. */ 765 Stats::Scalar quiesceCycles; 766 /** Stat for the number of committed instructions per thread. */ 767 Stats::Vector committedInsts; 768 /** Stat for the number of committed ops (including micro ops) per thread. */ 769 Stats::Vector committedOps; 770 /** Stat for the CPI per thread. */ 771 Stats::Formula cpi; 772 /** Stat for the total CPI. */ 773 Stats::Formula totalCpi; 774 /** Stat for the IPC per thread. */ 775 Stats::Formula ipc; 776 /** Stat for the total IPC. */ 777 Stats::Formula totalIpc; 778 779 //number of integer register file accesses 780 Stats::Scalar intRegfileReads; 781 Stats::Scalar intRegfileWrites; 782 //number of float register file accesses 783 Stats::Scalar fpRegfileReads; 784 Stats::Scalar fpRegfileWrites; 785 //number of vector register file accesses 786 mutable Stats::Scalar vecRegfileReads; 787 Stats::Scalar vecRegfileWrites; 788 //number of CC register file accesses 789 Stats::Scalar ccRegfileReads; 790 Stats::Scalar ccRegfileWrites; 791 //number of misc 792 Stats::Scalar miscRegfileReads; 793 Stats::Scalar miscRegfileWrites; 794}; 795 796#endif // __CPU_O3_CPU_HH__ 797