cpu.hh revision 13500:6e0a2a7c6d8c
1/* 2 * Copyright (c) 2011-2013, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/generic/types.hh" 57#include "arch/types.hh" 58#include "base/statistics.hh" 59#include "config/the_isa.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class MemObject; 80class Process; 81 82struct BaseCPUParams; 83 84class BaseO3CPU : public BaseCPU 85{ 86 //Stuff that's pretty ISA independent will go here. 87 public: 88 BaseO3CPU(BaseCPUParams *params); 89 90 void regStats(); 91}; 92 93/** 94 * FullO3CPU class, has each of the stages (fetch through commit) 95 * within it, as well as all of the time buffers between stages. The 96 * tick() function for the CPU is defined here. 97 */ 98template <class Impl> 99class FullO3CPU : public BaseO3CPU 100{ 101 public: 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 110 typedef O3ThreadState<Impl> ImplState; 111 typedef O3ThreadState<Impl> Thread; 112 113 typedef typename std::list<DynInstPtr>::iterator ListIt; 114 115 friend class O3ThreadContext<Impl>; 116 117 public: 118 enum Status { 119 Running, 120 Idle, 121 Halted, 122 Blocked, 123 SwitchedOut 124 }; 125 126 BaseTLB *itb; 127 BaseTLB *dtb; 128 129 /** Overall CPU status. */ 130 Status _status; 131 132 private: 133 134 /** 135 * IcachePort class for instruction fetch. 136 */ 137 class IcachePort : public MasterPort 138 { 139 protected: 140 /** Pointer to fetch. */ 141 DefaultFetch<Impl> *fetch; 142 143 public: 144 /** Default constructor. */ 145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 146 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 147 { } 148 149 protected: 150 151 /** Timing version of receive. Handles setting fetch to the 152 * proper status to start fetching. */ 153 virtual bool recvTimingResp(PacketPtr pkt); 154 155 /** Handles doing a retry of a failed fetch. */ 156 virtual void recvReqRetry(); 157 }; 158 159 /** 160 * DcachePort class for the load/store queue. 161 */ 162 class DcachePort : public MasterPort 163 { 164 protected: 165 166 /** Pointer to LSQ. */ 167 LSQ<Impl> *lsq; 168 FullO3CPU<Impl> *cpu; 169 170 public: 171 /** Default constructor. */ 172 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 173 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 174 cpu(_cpu) 175 { } 176 177 protected: 178 179 /** Timing version of receive. Handles writing back and 180 * completing the load or store that has returned from 181 * memory. */ 182 virtual bool recvTimingResp(PacketPtr pkt); 183 virtual void recvTimingSnoopReq(PacketPtr pkt); 184 185 virtual void recvFunctionalSnoop(PacketPtr pkt) 186 { 187 // @todo: Is there a need for potential invalidation here? 188 } 189 190 /** Handles doing a retry of the previous send. */ 191 virtual void recvReqRetry(); 192 193 /** 194 * As this CPU requires snooping to maintain the load store queue 195 * change the behaviour from the base CPU port. 196 * 197 * @return true since we have to snoop 198 */ 199 virtual bool isSnooping() const { return true; } 200 }; 201 202 /** The tick event used for scheduling CPU ticks. */ 203 EventFunctionWrapper tickEvent; 204 205 /** Schedule tick event, regardless of its current state. */ 206 void scheduleTickEvent(Cycles delay) 207 { 208 if (tickEvent.squashed()) 209 reschedule(tickEvent, clockEdge(delay)); 210 else if (!tickEvent.scheduled()) 211 schedule(tickEvent, clockEdge(delay)); 212 } 213 214 /** Unschedule tick event, regardless of its current state. */ 215 void unscheduleTickEvent() 216 { 217 if (tickEvent.scheduled()) 218 tickEvent.squash(); 219 } 220 221 /** 222 * Check if the pipeline has drained and signal drain done. 223 * 224 * This method checks if a drain has been requested and if the CPU 225 * has drained successfully (i.e., there are no instructions in 226 * the pipeline). If the CPU has drained, it deschedules the tick 227 * event and signals the drain manager. 228 * 229 * @return False if a drain hasn't been requested or the CPU 230 * hasn't drained, true otherwise. 231 */ 232 bool tryDrain(); 233 234 /** 235 * Perform sanity checks after a drain. 236 * 237 * This method is called from drain() when it has determined that 238 * the CPU is fully drained when gem5 is compiled with the NDEBUG 239 * macro undefined. The intention of this method is to do more 240 * extensive tests than the isDrained() method to weed out any 241 * draining bugs. 242 */ 243 void drainSanityCheck() const; 244 245 /** Check if a system is in a drained state. */ 246 bool isDrained() const; 247 248 public: 249 /** Constructs a CPU with the given parameters. */ 250 FullO3CPU(DerivO3CPUParams *params); 251 /** Destructor. */ 252 ~FullO3CPU(); 253 254 /** Registers statistics. */ 255 void regStats() override; 256 257 ProbePointArg<PacketPtr> *ppInstAccessComplete; 258 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 259 260 /** Register probe points. */ 261 void regProbePoints() override; 262 263 void demapPage(Addr vaddr, uint64_t asn) 264 { 265 this->itb->demapPage(vaddr, asn); 266 this->dtb->demapPage(vaddr, asn); 267 } 268 269 void demapInstPage(Addr vaddr, uint64_t asn) 270 { 271 this->itb->demapPage(vaddr, asn); 272 } 273 274 void demapDataPage(Addr vaddr, uint64_t asn) 275 { 276 this->dtb->demapPage(vaddr, asn); 277 } 278 279 /** Ticks CPU, calling tick() on each stage, and checking the overall 280 * activity to see if the CPU should deschedule itself. 281 */ 282 void tick(); 283 284 /** Initialize the CPU */ 285 void init() override; 286 287 void startup() override; 288 289 /** Returns the Number of Active Threads in the CPU */ 290 int numActiveThreads() 291 { return activeThreads.size(); } 292 293 /** Add Thread to Active Threads List */ 294 void activateThread(ThreadID tid); 295 296 /** Remove Thread from Active Threads List */ 297 void deactivateThread(ThreadID tid); 298 299 /** Setup CPU to insert a thread's context */ 300 void insertThread(ThreadID tid); 301 302 /** Remove all of a thread's context from CPU */ 303 void removeThread(ThreadID tid); 304 305 /** Count the Total Instructions Committed in the CPU. */ 306 Counter totalInsts() const override; 307 308 /** Count the Total Ops (including micro ops) committed in the CPU. */ 309 Counter totalOps() const override; 310 311 /** Add Thread to Active Threads List. */ 312 void activateContext(ThreadID tid) override; 313 314 /** Remove Thread from Active Threads List */ 315 void suspendContext(ThreadID tid) override; 316 317 /** Remove Thread from Active Threads List && 318 * Remove Thread Context from CPU. 319 */ 320 void haltContext(ThreadID tid) override; 321 322 /** Update The Order In Which We Process Threads. */ 323 void updateThreadPriority(); 324 325 /** Is the CPU draining? */ 326 bool isDraining() const { return drainState() == DrainState::Draining; } 327 328 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 329 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 330 331 public: 332 /** Executes a syscall. 333 * @todo: Determine if this needs to be virtual. 334 */ 335 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 336 337 /** Starts draining the CPU's pipeline of all instructions in 338 * order to stop all memory accesses. */ 339 DrainState drain() override; 340 341 /** Resumes execution after a drain. */ 342 void drainResume() override; 343 344 /** 345 * Commit has reached a safe point to drain a thread. 346 * 347 * Commit calls this method to inform the pipeline that it has 348 * reached a point where it is not executed microcode and is about 349 * to squash uncommitted instructions to fully drain the pipeline. 350 */ 351 void commitDrained(ThreadID tid); 352 353 /** Switches out this CPU. */ 354 void switchOut() override; 355 356 /** Takes over from another CPU. */ 357 void takeOverFrom(BaseCPU *oldCPU) override; 358 359 void verifyMemoryMode() const override; 360 361 /** Get the current instruction sequence number, and increment it. */ 362 InstSeqNum getAndIncrementInstSeq() 363 { return globalSeqNum++; } 364 365 /** Traps to handle given fault. */ 366 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 367 368 /** HW return from error interrupt. */ 369 Fault hwrei(ThreadID tid); 370 371 bool simPalCheck(int palFunc, ThreadID tid); 372 373 /** Returns the Fault for any valid interrupt. */ 374 Fault getInterrupts(); 375 376 /** Processes any an interrupt fault. */ 377 void processInterrupts(const Fault &interrupt); 378 379 /** Halts the CPU. */ 380 void halt() { panic("Halt not implemented!\n"); } 381 382 /** Register accessors. Index refers to the physical register index. */ 383 384 /** Reads a miscellaneous register. */ 385 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 386 387 /** Reads a misc. register, including any side effects the read 388 * might have as defined by the architecture. 389 */ 390 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 391 392 /** Sets a miscellaneous register. */ 393 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 394 ThreadID tid); 395 396 /** Sets a misc. register, including any side effects the write 397 * might have as defined by the architecture. 398 */ 399 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 400 ThreadID tid); 401 402 uint64_t readIntReg(PhysRegIdPtr phys_reg); 403 404 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); 405 406 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 407 408 /** 409 * Read physical vector register for modification. 410 */ 411 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 412 413 /** 414 * Read physical vector register lane 415 */ 416 template<typename VecElem, int LaneIdx> 417 VecLaneT<VecElem, true> 418 readVecLane(PhysRegIdPtr phys_reg) const 419 { 420 vecRegfileReads++; 421 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 422 } 423 424 /** 425 * Read physical vector register lane 426 */ 427 template<typename VecElem> 428 VecLaneT<VecElem, true> 429 readVecLane(PhysRegIdPtr phys_reg) const 430 { 431 vecRegfileReads++; 432 return regFile.readVecLane<VecElem>(phys_reg); 433 } 434 435 /** Write a lane of the destination vector register. */ 436 template<typename LD> 437 void 438 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 439 { 440 vecRegfileWrites++; 441 return regFile.setVecLane(phys_reg, val); 442 } 443 444 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 445 446 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 447 448 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); 449 450 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); 451 452 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 453 454 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 455 456 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 457 458 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 459 460 uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid); 461 462 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 463 /** Read architectural vector register for modification. */ 464 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 465 466 /** Read architectural vector register lane. */ 467 template<typename VecElem> 468 VecLaneT<VecElem, true> 469 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 470 { 471 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 472 RegId(VecRegClass, reg_idx)); 473 return readVecLane<VecElem>(phys_reg); 474 } 475 476 477 /** Write a lane of the destination vector register. */ 478 template<typename LD> 479 void 480 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 481 { 482 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 483 RegId(VecRegClass, reg_idx)); 484 setVecLane(phys_reg, val); 485 } 486 487 const VecElem& readArchVecElem(const RegIndex& reg_idx, 488 const ElemIndex& ldx, ThreadID tid) const; 489 490 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 491 492 /** Architectural register accessors. Looks up in the commit 493 * rename table to obtain the true physical index of the 494 * architected register first, then accesses that physical 495 * register. 496 */ 497 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 498 499 void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid); 500 501 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 502 503 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 504 const VecElem& val, ThreadID tid); 505 506 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 507 508 /** Sets the commit PC state of a specific thread. */ 509 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 510 511 /** Reads the commit PC state of a specific thread. */ 512 TheISA::PCState pcState(ThreadID tid); 513 514 /** Reads the commit PC of a specific thread. */ 515 Addr instAddr(ThreadID tid); 516 517 /** Reads the commit micro PC of a specific thread. */ 518 MicroPC microPC(ThreadID tid); 519 520 /** Reads the next PC of a specific thread. */ 521 Addr nextInstAddr(ThreadID tid); 522 523 /** Initiates a squash of all in-flight instructions for a given 524 * thread. The source of the squash is an external update of 525 * state through the TC. 526 */ 527 void squashFromTC(ThreadID tid); 528 529 /** Function to add instruction onto the head of the list of the 530 * instructions. Used when new instructions are fetched. 531 */ 532 ListIt addInst(const DynInstPtr &inst); 533 534 /** Function to tell the CPU that an instruction has completed. */ 535 void instDone(ThreadID tid, const DynInstPtr &inst); 536 537 /** Remove an instruction from the front end of the list. There's 538 * no restriction on location of the instruction. 539 */ 540 void removeFrontInst(const DynInstPtr &inst); 541 542 /** Remove all instructions that are not currently in the ROB. 543 * There's also an option to not squash delay slot instructions.*/ 544 void removeInstsNotInROB(ThreadID tid); 545 546 /** Remove all instructions younger than the given sequence number. */ 547 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 548 549 /** Removes the instruction pointed to by the iterator. */ 550 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 551 552 /** Cleans up all instructions on the remove list. */ 553 void cleanUpRemovedInsts(); 554 555 /** Debug function to print all instructions on the list. */ 556 void dumpInsts(); 557 558 public: 559#ifndef NDEBUG 560 /** Count of total number of dynamic instructions in flight. */ 561 int instcount; 562#endif 563 564 /** List of all the instructions in flight. */ 565 std::list<DynInstPtr> instList; 566 567 /** List of all the instructions that will be removed at the end of this 568 * cycle. 569 */ 570 std::queue<ListIt> removeList; 571 572#ifdef DEBUG 573 /** Debug structure to keep track of the sequence numbers still in 574 * flight. 575 */ 576 std::set<InstSeqNum> snList; 577#endif 578 579 /** Records if instructions need to be removed this cycle due to 580 * being retired or squashed. 581 */ 582 bool removeInstsThisCycle; 583 584 protected: 585 /** The fetch stage. */ 586 typename CPUPolicy::Fetch fetch; 587 588 /** The decode stage. */ 589 typename CPUPolicy::Decode decode; 590 591 /** The dispatch stage. */ 592 typename CPUPolicy::Rename rename; 593 594 /** The issue/execute/writeback stages. */ 595 typename CPUPolicy::IEW iew; 596 597 /** The commit stage. */ 598 typename CPUPolicy::Commit commit; 599 600 /** The rename mode of the vector registers */ 601 Enums::VecRegRenameMode vecMode; 602 603 /** The register file. */ 604 PhysRegFile regFile; 605 606 /** The free list. */ 607 typename CPUPolicy::FreeList freeList; 608 609 /** The rename map. */ 610 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 611 612 /** The commit rename map. */ 613 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 614 615 /** The re-order buffer. */ 616 typename CPUPolicy::ROB rob; 617 618 /** Active Threads List */ 619 std::list<ThreadID> activeThreads; 620 621 /** Integer Register Scoreboard */ 622 Scoreboard scoreboard; 623 624 std::vector<TheISA::ISA *> isa; 625 626 /** Instruction port. Note that it has to appear after the fetch stage. */ 627 IcachePort icachePort; 628 629 /** Data port. Note that it has to appear after the iew stages */ 630 DcachePort dcachePort; 631 632 public: 633 /** Enum to give each stage a specific index, so when calling 634 * activateStage() or deactivateStage(), they can specify which stage 635 * is being activated/deactivated. 636 */ 637 enum StageIdx { 638 FetchIdx, 639 DecodeIdx, 640 RenameIdx, 641 IEWIdx, 642 CommitIdx, 643 NumStages }; 644 645 /** Typedefs from the Impl to get the structs that each of the 646 * time buffers should use. 647 */ 648 typedef typename CPUPolicy::TimeStruct TimeStruct; 649 650 typedef typename CPUPolicy::FetchStruct FetchStruct; 651 652 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 653 654 typedef typename CPUPolicy::RenameStruct RenameStruct; 655 656 typedef typename CPUPolicy::IEWStruct IEWStruct; 657 658 /** The main time buffer to do backwards communication. */ 659 TimeBuffer<TimeStruct> timeBuffer; 660 661 /** The fetch stage's instruction queue. */ 662 TimeBuffer<FetchStruct> fetchQueue; 663 664 /** The decode stage's instruction queue. */ 665 TimeBuffer<DecodeStruct> decodeQueue; 666 667 /** The rename stage's instruction queue. */ 668 TimeBuffer<RenameStruct> renameQueue; 669 670 /** The IEW stage's instruction queue. */ 671 TimeBuffer<IEWStruct> iewQueue; 672 673 private: 674 /** The activity recorder; used to tell if the CPU has any 675 * activity remaining or if it can go to idle and deschedule 676 * itself. 677 */ 678 ActivityRecorder activityRec; 679 680 public: 681 /** Records that there was time buffer activity this cycle. */ 682 void activityThisCycle() { activityRec.activity(); } 683 684 /** Changes a stage's status to active within the activity recorder. */ 685 void activateStage(const StageIdx idx) 686 { activityRec.activateStage(idx); } 687 688 /** Changes a stage's status to inactive within the activity recorder. */ 689 void deactivateStage(const StageIdx idx) 690 { activityRec.deactivateStage(idx); } 691 692 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 693 void wakeCPU(); 694 695 virtual void wakeup(ThreadID tid) override; 696 697 /** Gets a free thread id. Use if thread ids change across system. */ 698 ThreadID getFreeTid(); 699 700 public: 701 /** Returns a pointer to a thread context. */ 702 ThreadContext * 703 tcBase(ThreadID tid) 704 { 705 return thread[tid]->getTC(); 706 } 707 708 /** The global sequence number counter. */ 709 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 710 711 /** Pointer to the checker, which can dynamically verify 712 * instruction results at run time. This can be set to NULL if it 713 * is not being used. 714 */ 715 Checker<Impl> *checker; 716 717 /** Pointer to the system. */ 718 System *system; 719 720 /** Pointers to all of the threads in the CPU. */ 721 std::vector<Thread *> thread; 722 723 /** Threads Scheduled to Enter CPU */ 724 std::list<int> cpuWaitList; 725 726 /** The cycle that the CPU was last running, used for statistics. */ 727 Cycles lastRunningCycle; 728 729 /** The cycle that the CPU was last activated by a new thread*/ 730 Tick lastActivatedCycle; 731 732 /** Mapping for system thread id to cpu id */ 733 std::map<ThreadID, unsigned> threadMap; 734 735 /** Available thread ids in the cpu*/ 736 std::vector<ThreadID> tids; 737 738 /** CPU read function, forwards read to LSQ. */ 739 Fault read(const RequestPtr &req, 740 RequestPtr &sreqLow, RequestPtr &sreqHigh, 741 int load_idx) 742 { 743 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 744 } 745 746 /** CPU write function, forwards write to LSQ. */ 747 Fault write(const RequestPtr &req, 748 const RequestPtr &sreqLow, const RequestPtr &sreqHigh, 749 uint8_t *data, int store_idx) 750 { 751 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 752 data, store_idx); 753 } 754 755 /** Used by the fetch unit to get a hold of the instruction port. */ 756 MasterPort &getInstPort() override { return icachePort; } 757 758 /** Get the dcache port (used to find block size for translations). */ 759 MasterPort &getDataPort() override { return dcachePort; } 760 761 /** Stat for total number of times the CPU is descheduled. */ 762 Stats::Scalar timesIdled; 763 /** Stat for total number of cycles the CPU spends descheduled. */ 764 Stats::Scalar idleCycles; 765 /** Stat for total number of cycles the CPU spends descheduled due to a 766 * quiesce operation or waiting for an interrupt. */ 767 Stats::Scalar quiesceCycles; 768 /** Stat for the number of committed instructions per thread. */ 769 Stats::Vector committedInsts; 770 /** Stat for the number of committed ops (including micro ops) per thread. */ 771 Stats::Vector committedOps; 772 /** Stat for the CPI per thread. */ 773 Stats::Formula cpi; 774 /** Stat for the total CPI. */ 775 Stats::Formula totalCpi; 776 /** Stat for the IPC per thread. */ 777 Stats::Formula ipc; 778 /** Stat for the total IPC. */ 779 Stats::Formula totalIpc; 780 781 //number of integer register file accesses 782 Stats::Scalar intRegfileReads; 783 Stats::Scalar intRegfileWrites; 784 //number of float register file accesses 785 Stats::Scalar fpRegfileReads; 786 Stats::Scalar fpRegfileWrites; 787 //number of vector register file accesses 788 mutable Stats::Scalar vecRegfileReads; 789 Stats::Scalar vecRegfileWrites; 790 //number of CC register file accesses 791 Stats::Scalar ccRegfileReads; 792 Stats::Scalar ccRegfileWrites; 793 //number of misc 794 Stats::Scalar miscRegfileReads; 795 Stats::Scalar miscRegfileWrites; 796}; 797 798#endif // __CPU_O3_CPU_HH__ 799