cpu.hh revision 13429:a1e199fd8122
15217Ssaidi@eecs.umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2013, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49428SAndreas.Sandberg@ARM.com * All rights reserved 59428SAndreas.Sandberg@ARM.com * 69428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 149428SAndreas.Sandberg@ARM.com * 155217Ssaidi@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 165217Ssaidi@eecs.umich.edu * Copyright (c) 2011 Regents of the University of California 175217Ssaidi@eecs.umich.edu * All rights reserved. 185217Ssaidi@eecs.umich.edu * 195217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 205217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 215217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 225217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 235217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 245217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 255217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 265217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 275217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 285217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 295217Ssaidi@eecs.umich.edu * 305217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 315217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 325217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 335217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 345217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 355217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 365217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 375217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 385217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 395217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 405217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 415217Ssaidi@eecs.umich.edu * 425217Ssaidi@eecs.umich.edu * Authors: Kevin Lim 435217Ssaidi@eecs.umich.edu * Korey Sewell 4411793Sbrandon.potter@amd.com * Rick Strong 4511793Sbrandon.potter@amd.com */ 4613610Sgiacomo.gabrielli@arm.com 4711627Smichael.lebeane@amd.com#ifndef __CPU_O3_CPU_HH__ 4812334Sgabeblack@google.com#define __CPU_O3_CPU_HH__ 495217Ssaidi@eecs.umich.edu 506658Snate@binkert.org#include <iostream> 519441SAndreas.Sandberg@ARM.com#include <list> 529441SAndreas.Sandberg@ARM.com#include <queue> 538232Snate@binkert.org#include <set> 5411627Smichael.lebeane@amd.com#include <vector> 5511627Smichael.lebeane@amd.com 569441SAndreas.Sandberg@ARM.com#include "arch/generic/types.hh" 575217Ssaidi@eecs.umich.edu#include "arch/types.hh" 585217Ssaidi@eecs.umich.edu#include "base/statistics.hh" 595217Ssaidi@eecs.umich.edu#include "config/the_isa.hh" 605217Ssaidi@eecs.umich.edu#include "cpu/o3/comm.hh" 615217Ssaidi@eecs.umich.edu#include "cpu/o3/cpu_policy.hh" 625217Ssaidi@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 635217Ssaidi@eecs.umich.edu#include "cpu/o3/thread_state.hh" 645217Ssaidi@eecs.umich.edu#include "cpu/activity.hh" 6513557Sgabeblack@google.com#include "cpu/base.hh" 6613557Sgabeblack@google.com#include "cpu/simple_thread.hh" 675217Ssaidi@eecs.umich.edu#include "cpu/timebuf.hh" 685217Ssaidi@eecs.umich.edu//#include "cpu/o3/thread_context.hh" 695217Ssaidi@eecs.umich.edu#include "params/DerivO3CPU.hh" 705217Ssaidi@eecs.umich.edu#include "sim/process.hh" 715217Ssaidi@eecs.umich.edu 725217Ssaidi@eecs.umich.edutemplate <class> 735217Ssaidi@eecs.umich.educlass Checker; 7413611Sgabeblack@google.comclass ThreadContext; 7513611Sgabeblack@google.comtemplate <class> 765217Ssaidi@eecs.umich.educlass O3ThreadContext; 775217Ssaidi@eecs.umich.edu 785217Ssaidi@eecs.umich.educlass Checkpoint; 795217Ssaidi@eecs.umich.educlass MemObject; 8012109SRekai.GonzalezAlberquilla@arm.comclass Process; 8112109SRekai.GonzalezAlberquilla@arm.com 8212109SRekai.GonzalezAlberquilla@arm.comstruct BaseCPUParams; 8312109SRekai.GonzalezAlberquilla@arm.com 8412109SRekai.GonzalezAlberquilla@arm.comclass BaseO3CPU : public BaseCPU 8512109SRekai.GonzalezAlberquilla@arm.com{ 8612109SRekai.GonzalezAlberquilla@arm.com //Stuff that's pretty ISA independent will go here. 8712109SRekai.GonzalezAlberquilla@arm.com public: 8812109SRekai.GonzalezAlberquilla@arm.com BaseO3CPU(BaseCPUParams *params); 8912109SRekai.GonzalezAlberquilla@arm.com 9013610Sgiacomo.gabrielli@arm.com void regStats(); 9113610Sgiacomo.gabrielli@arm.com}; 9213610Sgiacomo.gabrielli@arm.com 9313610Sgiacomo.gabrielli@arm.com/** 9413610Sgiacomo.gabrielli@arm.com * FullO3CPU class, has each of the stages (fetch through commit) 9513610Sgiacomo.gabrielli@arm.com * within it, as well as all of the time buffers between stages. The 9613610Sgiacomo.gabrielli@arm.com * tick() function for the CPU is defined here. 9713610Sgiacomo.gabrielli@arm.com */ 9813610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 9913610Sgiacomo.gabrielli@arm.comclass FullO3CPU : public BaseO3CPU 10013610Sgiacomo.gabrielli@arm.com{ 1015217Ssaidi@eecs.umich.edu public: 10213557Sgabeblack@google.com // Typedefs from the Impl here. 10313557Sgabeblack@google.com typedef typename Impl::CPUPol CPUPolicy; 1045217Ssaidi@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 1055217Ssaidi@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 1065217Ssaidi@eecs.umich.edu 1075217Ssaidi@eecs.umich.edu using VecElem = TheISA::VecElem; 1085217Ssaidi@eecs.umich.edu using VecRegContainer = TheISA::VecRegContainer; 1099920Syasuko.eckert@amd.com 1109920Syasuko.eckert@amd.com typedef O3ThreadState<Impl> ImplState; 11113622Sgabeblack@google.com typedef O3ThreadState<Impl> Thread; 11213622Sgabeblack@google.com 1139920Syasuko.eckert@amd.com typedef typename std::list<DynInstPtr>::iterator ListIt; 1149920Syasuko.eckert@amd.com 1159920Syasuko.eckert@amd.com friend class O3ThreadContext<Impl>; 1169920Syasuko.eckert@amd.com 1177720Sgblack@eecs.umich.edu public: 1187720Sgblack@eecs.umich.edu enum Status { 1195712Shsul@eecs.umich.edu Running, 1205712Shsul@eecs.umich.edu Idle, 1215217Ssaidi@eecs.umich.edu Halted, 1225217Ssaidi@eecs.umich.edu Blocked, 1235714Shsul@eecs.umich.edu SwitchedOut 12411005Sandreas.sandberg@arm.com }; 12511005Sandreas.sandberg@arm.com 12611005Sandreas.sandberg@arm.com BaseTLB *itb; 1275714Shsul@eecs.umich.edu BaseTLB *dtb; 1285714Shsul@eecs.umich.edu 1295714Shsul@eecs.umich.edu /** Overall CPU status. */ 1305217Ssaidi@eecs.umich.edu Status _status; 1319428SAndreas.Sandberg@ARM.com 1329428SAndreas.Sandberg@ARM.com private: 13311627Smichael.lebeane@amd.com 13411627Smichael.lebeane@amd.com /** 13511627Smichael.lebeane@amd.com * IcachePort class for instruction fetch. 13611627Smichael.lebeane@amd.com */ 13711627Smichael.lebeane@amd.com class IcachePort : public MasterPort 13811627Smichael.lebeane@amd.com { 13911627Smichael.lebeane@amd.com protected: 14011627Smichael.lebeane@amd.com /** Pointer to fetch. */ 14111627Smichael.lebeane@amd.com DefaultFetch<Impl> *fetch; 14211627Smichael.lebeane@amd.com 14311627Smichael.lebeane@amd.com public: 14411627Smichael.lebeane@amd.com /** Default constructor. */ 14511627Smichael.lebeane@amd.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 14611627Smichael.lebeane@amd.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 14711627Smichael.lebeane@amd.com { } 14811627Smichael.lebeane@amd.com 14911627Smichael.lebeane@amd.com protected: 15011627Smichael.lebeane@amd.com 15111627Smichael.lebeane@amd.com /** Timing version of receive. Handles setting fetch to the 15211627Smichael.lebeane@amd.com * proper status to start fetching. */ 15311627Smichael.lebeane@amd.com virtual bool recvTimingResp(PacketPtr pkt); 15411627Smichael.lebeane@amd.com 15511627Smichael.lebeane@amd.com /** Handles doing a retry of a failed fetch. */ 15611627Smichael.lebeane@amd.com virtual void recvReqRetry(); 15711627Smichael.lebeane@amd.com }; 15811627Smichael.lebeane@amd.com 15911627Smichael.lebeane@amd.com /** 16011627Smichael.lebeane@amd.com * DcachePort class for the load/store queue. 16111627Smichael.lebeane@amd.com */ 16211627Smichael.lebeane@amd.com class DcachePort : public MasterPort 16311627Smichael.lebeane@amd.com { 16411627Smichael.lebeane@amd.com protected: 16511627Smichael.lebeane@amd.com 16610905Sandreas.sandberg@arm.com /** Pointer to LSQ. */ 1679428SAndreas.Sandberg@ARM.com LSQ<Impl> *lsq; 1689428SAndreas.Sandberg@ARM.com FullO3CPU<Impl> *cpu; 1699428SAndreas.Sandberg@ARM.com 17013557Sgabeblack@google.com public: 1719428SAndreas.Sandberg@ARM.com /** Default constructor. */ 17213611Sgabeblack@google.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1739428SAndreas.Sandberg@ARM.com : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 1749428SAndreas.Sandberg@ARM.com cpu(_cpu) 17510905Sandreas.sandberg@arm.com { } 1769428SAndreas.Sandberg@ARM.com 17712109SRekai.GonzalezAlberquilla@arm.com protected: 17812109SRekai.GonzalezAlberquilla@arm.com 17912109SRekai.GonzalezAlberquilla@arm.com /** Timing version of receive. Handles writing back and 18012109SRekai.GonzalezAlberquilla@arm.com * completing the load or store that has returned from 18112109SRekai.GonzalezAlberquilla@arm.com * memory. */ 18212109SRekai.GonzalezAlberquilla@arm.com virtual bool recvTimingResp(PacketPtr pkt); 18313610Sgiacomo.gabrielli@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 18413610Sgiacomo.gabrielli@arm.com 18513610Sgiacomo.gabrielli@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 18613610Sgiacomo.gabrielli@arm.com { 18713610Sgiacomo.gabrielli@arm.com // @todo: Is there a need for potential invalidation here? 18813610Sgiacomo.gabrielli@arm.com } 18913557Sgabeblack@google.com 1909428SAndreas.Sandberg@ARM.com /** Handles doing a retry of the previous send. */ 1919428SAndreas.Sandberg@ARM.com virtual void recvReqRetry(); 1929428SAndreas.Sandberg@ARM.com 1939428SAndreas.Sandberg@ARM.com /** 1949920Syasuko.eckert@amd.com * As this CPU requires snooping to maintain the load store queue 19513622Sgabeblack@google.com * change the behaviour from the base CPU port. 1969920Syasuko.eckert@amd.com * 1979920Syasuko.eckert@amd.com * @return true since we have to snoop 1989920Syasuko.eckert@amd.com */ 1999920Syasuko.eckert@amd.com virtual bool isSnooping() const { return true; } 2009920Syasuko.eckert@amd.com }; 20110905Sandreas.sandberg@arm.com 2029428SAndreas.Sandberg@ARM.com /** The tick event used for scheduling CPU ticks. */ 2039428SAndreas.Sandberg@ARM.com EventFunctionWrapper tickEvent; 2049428SAndreas.Sandberg@ARM.com 2059428SAndreas.Sandberg@ARM.com /** Schedule tick event, regardless of its current state. */ 2069428SAndreas.Sandberg@ARM.com void scheduleTickEvent(Cycles delay) 20710905Sandreas.sandberg@arm.com { 2089428SAndreas.Sandberg@ARM.com if (tickEvent.squashed()) 2099428SAndreas.Sandberg@ARM.com reschedule(tickEvent, clockEdge(delay)); 2109428SAndreas.Sandberg@ARM.com else if (!tickEvent.scheduled()) 21113557Sgabeblack@google.com schedule(tickEvent, clockEdge(delay)); 2129428SAndreas.Sandberg@ARM.com } 2139428SAndreas.Sandberg@ARM.com 21410905Sandreas.sandberg@arm.com /** Unschedule tick event, regardless of its current state. */ 2159428SAndreas.Sandberg@ARM.com void unscheduleTickEvent() 21613611Sgabeblack@google.com { 2179428SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 21812109SRekai.GonzalezAlberquilla@arm.com tickEvent.squash(); 21912109SRekai.GonzalezAlberquilla@arm.com } 22012109SRekai.GonzalezAlberquilla@arm.com 22112109SRekai.GonzalezAlberquilla@arm.com /** 22212109SRekai.GonzalezAlberquilla@arm.com * Check if the pipeline has drained and signal drain done. 22312109SRekai.GonzalezAlberquilla@arm.com * 22413610Sgiacomo.gabrielli@arm.com * This method checks if a drain has been requested and if the CPU 22513610Sgiacomo.gabrielli@arm.com * has drained successfully (i.e., there are no instructions in 22613610Sgiacomo.gabrielli@arm.com * the pipeline). If the CPU has drained, it deschedules the tick 22713610Sgiacomo.gabrielli@arm.com * event and signals the drain manager. 22813610Sgiacomo.gabrielli@arm.com * 22913610Sgiacomo.gabrielli@arm.com * @return False if a drain hasn't been requested or the CPU 23013557Sgabeblack@google.com * hasn't drained, true otherwise. 2319428SAndreas.Sandberg@ARM.com */ 2329428SAndreas.Sandberg@ARM.com bool tryDrain(); 2339428SAndreas.Sandberg@ARM.com 2349428SAndreas.Sandberg@ARM.com /** 2359920Syasuko.eckert@amd.com * Perform sanity checks after a drain. 23613622Sgabeblack@google.com * 2379920Syasuko.eckert@amd.com * This method is called from drain() when it has determined that 2389920Syasuko.eckert@amd.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 2399920Syasuko.eckert@amd.com * macro undefined. The intention of this method is to do more 2409920Syasuko.eckert@amd.com * extensive tests than the isDrained() method to weed out any 2419920Syasuko.eckert@amd.com * draining bugs. 2429428SAndreas.Sandberg@ARM.com */ 24310905Sandreas.sandberg@arm.com void drainSanityCheck() const; 2449428SAndreas.Sandberg@ARM.com 2459428SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 2469428SAndreas.Sandberg@ARM.com bool isDrained() const; 2479428SAndreas.Sandberg@ARM.com 2489441SAndreas.Sandberg@ARM.com public: 2499441SAndreas.Sandberg@ARM.com /** Constructs a CPU with the given parameters. */ 2509441SAndreas.Sandberg@ARM.com FullO3CPU(DerivO3CPUParams *params); 2519441SAndreas.Sandberg@ARM.com /** Destructor. */ 2529441SAndreas.Sandberg@ARM.com ~FullO3CPU(); 2539441SAndreas.Sandberg@ARM.com 2549441SAndreas.Sandberg@ARM.com /** Registers statistics. */ 2559441SAndreas.Sandberg@ARM.com void regStats() override; 2569441SAndreas.Sandberg@ARM.com 2579441SAndreas.Sandberg@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 2589441SAndreas.Sandberg@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 2599441SAndreas.Sandberg@ARM.com 2609441SAndreas.Sandberg@ARM.com /** Register probe points. */ 2619441SAndreas.Sandberg@ARM.com void regProbePoints() override; 2629441SAndreas.Sandberg@ARM.com 2639441SAndreas.Sandberg@ARM.com void demapPage(Addr vaddr, uint64_t asn) 2649441SAndreas.Sandberg@ARM.com { 2659441SAndreas.Sandberg@ARM.com this->itb->demapPage(vaddr, asn); 2669441SAndreas.Sandberg@ARM.com this->dtb->demapPage(vaddr, asn); 2679441SAndreas.Sandberg@ARM.com } 2689441SAndreas.Sandberg@ARM.com 2699441SAndreas.Sandberg@ARM.com void demapInstPage(Addr vaddr, uint64_t asn) 2709441SAndreas.Sandberg@ARM.com { 2719441SAndreas.Sandberg@ARM.com this->itb->demapPage(vaddr, asn); 2729441SAndreas.Sandberg@ARM.com } 2739441SAndreas.Sandberg@ARM.com 2749441SAndreas.Sandberg@ARM.com void demapDataPage(Addr vaddr, uint64_t asn) 2759441SAndreas.Sandberg@ARM.com { 2769441SAndreas.Sandberg@ARM.com this->dtb->demapPage(vaddr, asn); 2779441SAndreas.Sandberg@ARM.com } 2789441SAndreas.Sandberg@ARM.com 2799441SAndreas.Sandberg@ARM.com /** Ticks CPU, calling tick() on each stage, and checking the overall 2809441SAndreas.Sandberg@ARM.com * activity to see if the CPU should deschedule itself. 2819441SAndreas.Sandberg@ARM.com */ 282 void tick(); 283 284 /** Initialize the CPU */ 285 void init() override; 286 287 void startup() override; 288 289 /** Returns the Number of Active Threads in the CPU */ 290 int numActiveThreads() 291 { return activeThreads.size(); } 292 293 /** Add Thread to Active Threads List */ 294 void activateThread(ThreadID tid); 295 296 /** Remove Thread from Active Threads List */ 297 void deactivateThread(ThreadID tid); 298 299 /** Setup CPU to insert a thread's context */ 300 void insertThread(ThreadID tid); 301 302 /** Remove all of a thread's context from CPU */ 303 void removeThread(ThreadID tid); 304 305 /** Count the Total Instructions Committed in the CPU. */ 306 Counter totalInsts() const override; 307 308 /** Count the Total Ops (including micro ops) committed in the CPU. */ 309 Counter totalOps() const override; 310 311 /** Add Thread to Active Threads List. */ 312 void activateContext(ThreadID tid) override; 313 314 /** Remove Thread from Active Threads List */ 315 void suspendContext(ThreadID tid) override; 316 317 /** Remove Thread from Active Threads List && 318 * Remove Thread Context from CPU. 319 */ 320 void haltContext(ThreadID tid) override; 321 322 /** Update The Order In Which We Process Threads. */ 323 void updateThreadPriority(); 324 325 /** Is the CPU draining? */ 326 bool isDraining() const { return drainState() == DrainState::Draining; } 327 328 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 329 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 330 331 public: 332 /** Executes a syscall. 333 * @todo: Determine if this needs to be virtual. 334 */ 335 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 336 337 /** Starts draining the CPU's pipeline of all instructions in 338 * order to stop all memory accesses. */ 339 DrainState drain() override; 340 341 /** Resumes execution after a drain. */ 342 void drainResume() override; 343 344 /** 345 * Commit has reached a safe point to drain a thread. 346 * 347 * Commit calls this method to inform the pipeline that it has 348 * reached a point where it is not executed microcode and is about 349 * to squash uncommitted instructions to fully drain the pipeline. 350 */ 351 void commitDrained(ThreadID tid); 352 353 /** Switches out this CPU. */ 354 void switchOut() override; 355 356 /** Takes over from another CPU. */ 357 void takeOverFrom(BaseCPU *oldCPU) override; 358 359 void verifyMemoryMode() const override; 360 361 /** Get the current instruction sequence number, and increment it. */ 362 InstSeqNum getAndIncrementInstSeq() 363 { return globalSeqNum++; } 364 365 /** Traps to handle given fault. */ 366 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 367 368 /** HW return from error interrupt. */ 369 Fault hwrei(ThreadID tid); 370 371 bool simPalCheck(int palFunc, ThreadID tid); 372 373 /** Returns the Fault for any valid interrupt. */ 374 Fault getInterrupts(); 375 376 /** Processes any an interrupt fault. */ 377 void processInterrupts(const Fault &interrupt); 378 379 /** Halts the CPU. */ 380 void halt() { panic("Halt not implemented!\n"); } 381 382 /** Register accessors. Index refers to the physical register index. */ 383 384 /** Reads a miscellaneous register. */ 385 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 386 387 /** Reads a misc. register, including any side effects the read 388 * might have as defined by the architecture. 389 */ 390 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 391 392 /** Sets a miscellaneous register. */ 393 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 394 ThreadID tid); 395 396 /** Sets a misc. register, including any side effects the write 397 * might have as defined by the architecture. 398 */ 399 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 400 ThreadID tid); 401 402 uint64_t readIntReg(PhysRegIdPtr phys_reg); 403 404 TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); 405 406 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); 407 408 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 409 410 /** 411 * Read physical vector register for modification. 412 */ 413 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 414 415 /** 416 * Read physical vector register lane 417 */ 418 template<typename VecElem, int LaneIdx> 419 VecLaneT<VecElem, true> 420 readVecLane(PhysRegIdPtr phys_reg) const 421 { 422 vecRegfileReads++; 423 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 424 } 425 426 /** 427 * Read physical vector register lane 428 */ 429 template<typename VecElem> 430 VecLaneT<VecElem, true> 431 readVecLane(PhysRegIdPtr phys_reg) const 432 { 433 vecRegfileReads++; 434 return regFile.readVecLane<VecElem>(phys_reg); 435 } 436 437 /** Write a lane of the destination vector register. */ 438 template<typename LD> 439 void 440 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 441 { 442 vecRegfileWrites++; 443 return regFile.setVecLane(phys_reg, val); 444 } 445 446 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 447 448 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 449 450 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); 451 452 void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val); 453 454 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); 455 456 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 457 458 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 459 460 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 461 462 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 463 464 float readArchFloatReg(int reg_idx, ThreadID tid); 465 466 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 467 468 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 469 /** Read architectural vector register for modification. */ 470 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 471 472 /** Read architectural vector register lane. */ 473 template<typename VecElem> 474 VecLaneT<VecElem, true> 475 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 476 { 477 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 478 RegId(VecRegClass, reg_idx)); 479 return readVecLane<VecElem>(phys_reg); 480 } 481 482 483 /** Write a lane of the destination vector register. */ 484 template<typename LD> 485 void 486 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 487 { 488 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 489 RegId(VecRegClass, reg_idx)); 490 setVecLane(phys_reg, val); 491 } 492 493 const VecElem& readArchVecElem(const RegIndex& reg_idx, 494 const ElemIndex& ldx, ThreadID tid) const; 495 496 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 497 498 /** Architectural register accessors. Looks up in the commit 499 * rename table to obtain the true physical index of the 500 * architected register first, then accesses that physical 501 * register. 502 */ 503 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 504 505 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 506 507 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 508 509 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 510 511 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 512 const VecElem& val, ThreadID tid); 513 514 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 515 516 /** Sets the commit PC state of a specific thread. */ 517 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 518 519 /** Reads the commit PC state of a specific thread. */ 520 TheISA::PCState pcState(ThreadID tid); 521 522 /** Reads the commit PC of a specific thread. */ 523 Addr instAddr(ThreadID tid); 524 525 /** Reads the commit micro PC of a specific thread. */ 526 MicroPC microPC(ThreadID tid); 527 528 /** Reads the next PC of a specific thread. */ 529 Addr nextInstAddr(ThreadID tid); 530 531 /** Initiates a squash of all in-flight instructions for a given 532 * thread. The source of the squash is an external update of 533 * state through the TC. 534 */ 535 void squashFromTC(ThreadID tid); 536 537 /** Function to add instruction onto the head of the list of the 538 * instructions. Used when new instructions are fetched. 539 */ 540 ListIt addInst(const DynInstPtr &inst); 541 542 /** Function to tell the CPU that an instruction has completed. */ 543 void instDone(ThreadID tid, const DynInstPtr &inst); 544 545 /** Remove an instruction from the front end of the list. There's 546 * no restriction on location of the instruction. 547 */ 548 void removeFrontInst(const DynInstPtr &inst); 549 550 /** Remove all instructions that are not currently in the ROB. 551 * There's also an option to not squash delay slot instructions.*/ 552 void removeInstsNotInROB(ThreadID tid); 553 554 /** Remove all instructions younger than the given sequence number. */ 555 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 556 557 /** Removes the instruction pointed to by the iterator. */ 558 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 559 560 /** Cleans up all instructions on the remove list. */ 561 void cleanUpRemovedInsts(); 562 563 /** Debug function to print all instructions on the list. */ 564 void dumpInsts(); 565 566 public: 567#ifndef NDEBUG 568 /** Count of total number of dynamic instructions in flight. */ 569 int instcount; 570#endif 571 572 /** List of all the instructions in flight. */ 573 std::list<DynInstPtr> instList; 574 575 /** List of all the instructions that will be removed at the end of this 576 * cycle. 577 */ 578 std::queue<ListIt> removeList; 579 580#ifdef DEBUG 581 /** Debug structure to keep track of the sequence numbers still in 582 * flight. 583 */ 584 std::set<InstSeqNum> snList; 585#endif 586 587 /** Records if instructions need to be removed this cycle due to 588 * being retired or squashed. 589 */ 590 bool removeInstsThisCycle; 591 592 protected: 593 /** The fetch stage. */ 594 typename CPUPolicy::Fetch fetch; 595 596 /** The decode stage. */ 597 typename CPUPolicy::Decode decode; 598 599 /** The dispatch stage. */ 600 typename CPUPolicy::Rename rename; 601 602 /** The issue/execute/writeback stages. */ 603 typename CPUPolicy::IEW iew; 604 605 /** The commit stage. */ 606 typename CPUPolicy::Commit commit; 607 608 /** The rename mode of the vector registers */ 609 Enums::VecRegRenameMode vecMode; 610 611 /** The register file. */ 612 PhysRegFile regFile; 613 614 /** The free list. */ 615 typename CPUPolicy::FreeList freeList; 616 617 /** The rename map. */ 618 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 619 620 /** The commit rename map. */ 621 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 622 623 /** The re-order buffer. */ 624 typename CPUPolicy::ROB rob; 625 626 /** Active Threads List */ 627 std::list<ThreadID> activeThreads; 628 629 /** Integer Register Scoreboard */ 630 Scoreboard scoreboard; 631 632 std::vector<TheISA::ISA *> isa; 633 634 /** Instruction port. Note that it has to appear after the fetch stage. */ 635 IcachePort icachePort; 636 637 /** Data port. Note that it has to appear after the iew stages */ 638 DcachePort dcachePort; 639 640 public: 641 /** Enum to give each stage a specific index, so when calling 642 * activateStage() or deactivateStage(), they can specify which stage 643 * is being activated/deactivated. 644 */ 645 enum StageIdx { 646 FetchIdx, 647 DecodeIdx, 648 RenameIdx, 649 IEWIdx, 650 CommitIdx, 651 NumStages }; 652 653 /** Typedefs from the Impl to get the structs that each of the 654 * time buffers should use. 655 */ 656 typedef typename CPUPolicy::TimeStruct TimeStruct; 657 658 typedef typename CPUPolicy::FetchStruct FetchStruct; 659 660 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 661 662 typedef typename CPUPolicy::RenameStruct RenameStruct; 663 664 typedef typename CPUPolicy::IEWStruct IEWStruct; 665 666 /** The main time buffer to do backwards communication. */ 667 TimeBuffer<TimeStruct> timeBuffer; 668 669 /** The fetch stage's instruction queue. */ 670 TimeBuffer<FetchStruct> fetchQueue; 671 672 /** The decode stage's instruction queue. */ 673 TimeBuffer<DecodeStruct> decodeQueue; 674 675 /** The rename stage's instruction queue. */ 676 TimeBuffer<RenameStruct> renameQueue; 677 678 /** The IEW stage's instruction queue. */ 679 TimeBuffer<IEWStruct> iewQueue; 680 681 private: 682 /** The activity recorder; used to tell if the CPU has any 683 * activity remaining or if it can go to idle and deschedule 684 * itself. 685 */ 686 ActivityRecorder activityRec; 687 688 public: 689 /** Records that there was time buffer activity this cycle. */ 690 void activityThisCycle() { activityRec.activity(); } 691 692 /** Changes a stage's status to active within the activity recorder. */ 693 void activateStage(const StageIdx idx) 694 { activityRec.activateStage(idx); } 695 696 /** Changes a stage's status to inactive within the activity recorder. */ 697 void deactivateStage(const StageIdx idx) 698 { activityRec.deactivateStage(idx); } 699 700 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 701 void wakeCPU(); 702 703 virtual void wakeup(ThreadID tid) override; 704 705 /** Gets a free thread id. Use if thread ids change across system. */ 706 ThreadID getFreeTid(); 707 708 public: 709 /** Returns a pointer to a thread context. */ 710 ThreadContext * 711 tcBase(ThreadID tid) 712 { 713 return thread[tid]->getTC(); 714 } 715 716 /** The global sequence number counter. */ 717 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 718 719 /** Pointer to the checker, which can dynamically verify 720 * instruction results at run time. This can be set to NULL if it 721 * is not being used. 722 */ 723 Checker<Impl> *checker; 724 725 /** Pointer to the system. */ 726 System *system; 727 728 /** Pointers to all of the threads in the CPU. */ 729 std::vector<Thread *> thread; 730 731 /** Threads Scheduled to Enter CPU */ 732 std::list<int> cpuWaitList; 733 734 /** The cycle that the CPU was last running, used for statistics. */ 735 Cycles lastRunningCycle; 736 737 /** The cycle that the CPU was last activated by a new thread*/ 738 Tick lastActivatedCycle; 739 740 /** Mapping for system thread id to cpu id */ 741 std::map<ThreadID, unsigned> threadMap; 742 743 /** Available thread ids in the cpu*/ 744 std::vector<ThreadID> tids; 745 746 /** CPU read function, forwards read to LSQ. */ 747 Fault read(const RequestPtr &req, 748 RequestPtr &sreqLow, RequestPtr &sreqHigh, 749 int load_idx) 750 { 751 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 752 } 753 754 /** CPU write function, forwards write to LSQ. */ 755 Fault write(const RequestPtr &req, 756 const RequestPtr &sreqLow, const RequestPtr &sreqHigh, 757 uint8_t *data, int store_idx) 758 { 759 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 760 data, store_idx); 761 } 762 763 /** Used by the fetch unit to get a hold of the instruction port. */ 764 MasterPort &getInstPort() override { return icachePort; } 765 766 /** Get the dcache port (used to find block size for translations). */ 767 MasterPort &getDataPort() override { return dcachePort; } 768 769 /** Stat for total number of times the CPU is descheduled. */ 770 Stats::Scalar timesIdled; 771 /** Stat for total number of cycles the CPU spends descheduled. */ 772 Stats::Scalar idleCycles; 773 /** Stat for total number of cycles the CPU spends descheduled due to a 774 * quiesce operation or waiting for an interrupt. */ 775 Stats::Scalar quiesceCycles; 776 /** Stat for the number of committed instructions per thread. */ 777 Stats::Vector committedInsts; 778 /** Stat for the number of committed ops (including micro ops) per thread. */ 779 Stats::Vector committedOps; 780 /** Stat for the CPI per thread. */ 781 Stats::Formula cpi; 782 /** Stat for the total CPI. */ 783 Stats::Formula totalCpi; 784 /** Stat for the IPC per thread. */ 785 Stats::Formula ipc; 786 /** Stat for the total IPC. */ 787 Stats::Formula totalIpc; 788 789 //number of integer register file accesses 790 Stats::Scalar intRegfileReads; 791 Stats::Scalar intRegfileWrites; 792 //number of float register file accesses 793 Stats::Scalar fpRegfileReads; 794 Stats::Scalar fpRegfileWrites; 795 //number of vector register file accesses 796 mutable Stats::Scalar vecRegfileReads; 797 Stats::Scalar vecRegfileWrites; 798 //number of CC register file accesses 799 Stats::Scalar ccRegfileReads; 800 Stats::Scalar ccRegfileWrites; 801 //number of misc 802 Stats::Scalar miscRegfileReads; 803 Stats::Scalar miscRegfileWrites; 804}; 805 806#endif // __CPU_O3_CPU_HH__ 807