cpu.hh revision 11302
13900Ssaidi@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2011-2013 ARM Limited 32632Sstever@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 42632Sstever@eecs.umich.edu * All rights reserved 52632Sstever@eecs.umich.edu * 62632Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 72632Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 82632Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 92632Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 102632Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 112632Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 122632Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 132632Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 142632Sstever@eecs.umich.edu * 152632Sstever@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 162632Sstever@eecs.umich.edu * Copyright (c) 2011 Regents of the University of California 172632Sstever@eecs.umich.edu * All rights reserved. 182632Sstever@eecs.umich.edu * 192632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 202632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 212632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 222632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 232632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 242632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 252632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 262632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 272632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 282632Sstever@eecs.umich.edu * this software without specific prior written permission. 292632Sstever@eecs.umich.edu * 302632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312022SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322022SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332022SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342022SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352022SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362469SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372469SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382469SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392469SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402516SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412516SN/A * 422944Sgblack@eecs.umich.edu * Authors: Kevin Lim 432482SN/A * Korey Sewell 443598Sgblack@eecs.umich.edu * Rick Strong 453056Sgblack@eecs.umich.edu */ 462469SN/A 473056Sgblack@eecs.umich.edu#ifndef __CPU_O3_CPU_HH__ 483056Sgblack@eecs.umich.edu#define __CPU_O3_CPU_HH__ 493056Sgblack@eecs.umich.edu 503598Sgblack@eecs.umich.edu#include <iostream> 512516SN/A#include <list> 523056Sgblack@eecs.umich.edu#include <queue> 533598Sgblack@eecs.umich.edu#include <set> 543056Sgblack@eecs.umich.edu#include <vector> 553056Sgblack@eecs.umich.edu 563056Sgblack@eecs.umich.edu#include "arch/types.hh" 573056Sgblack@eecs.umich.edu#include "base/statistics.hh" 583056Sgblack@eecs.umich.edu#include "config/the_isa.hh" 593056Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 603056Sgblack@eecs.umich.edu#include "cpu/o3/cpu_policy.hh" 613598Sgblack@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 623056Sgblack@eecs.umich.edu#include "cpu/o3/thread_state.hh" 633056Sgblack@eecs.umich.edu#include "cpu/activity.hh" 643598Sgblack@eecs.umich.edu#include "cpu/base.hh" 654004Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 664004Sgblack@eecs.umich.edu#include "cpu/timebuf.hh" 673056Sgblack@eecs.umich.edu//#include "cpu/o3/thread_context.hh" 683056Sgblack@eecs.umich.edu#include "params/DerivO3CPU.hh" 693056Sgblack@eecs.umich.edu#include "sim/process.hh" 703056Sgblack@eecs.umich.edu 713056Sgblack@eecs.umich.edutemplate <class> 723056Sgblack@eecs.umich.educlass Checker; 733056Sgblack@eecs.umich.educlass ThreadContext; 743056Sgblack@eecs.umich.edutemplate <class> 753056Sgblack@eecs.umich.educlass O3ThreadContext; 763056Sgblack@eecs.umich.edu 773056Sgblack@eecs.umich.educlass Checkpoint; 783056Sgblack@eecs.umich.educlass MemObject; 793056Sgblack@eecs.umich.educlass Process; 803056Sgblack@eecs.umich.edu 813056Sgblack@eecs.umich.edustruct BaseCPUParams; 823056Sgblack@eecs.umich.edu 833056Sgblack@eecs.umich.educlass BaseO3CPU : public BaseCPU 842482SN/A{ 853598Sgblack@eecs.umich.edu //Stuff that's pretty ISA independent will go here. 863598Sgblack@eecs.umich.edu public: 873598Sgblack@eecs.umich.edu BaseO3CPU(BaseCPUParams *params); 883598Sgblack@eecs.umich.edu 893598Sgblack@eecs.umich.edu void regStats(); 903598Sgblack@eecs.umich.edu}; 913598Sgblack@eecs.umich.edu 923598Sgblack@eecs.umich.edu/** 933598Sgblack@eecs.umich.edu * FullO3CPU class, has each of the stages (fetch through commit) 943598Sgblack@eecs.umich.edu * within it, as well as all of the time buffers between stages. The 953598Sgblack@eecs.umich.edu * tick() function for the CPU is defined here. 963598Sgblack@eecs.umich.edu */ 973598Sgblack@eecs.umich.edutemplate <class Impl> 983598Sgblack@eecs.umich.educlass FullO3CPU : public BaseO3CPU 993598Sgblack@eecs.umich.edu{ 1003598Sgblack@eecs.umich.edu public: 1013598Sgblack@eecs.umich.edu // Typedefs from the Impl here. 1023598Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPolicy; 1033598Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 1043598Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 1053598Sgblack@eecs.umich.edu 1064004Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1074004Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> Thread; 1083598Sgblack@eecs.umich.edu 1093598Sgblack@eecs.umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 1103598Sgblack@eecs.umich.edu 1113598Sgblack@eecs.umich.edu friend class O3ThreadContext<Impl>; 1123598Sgblack@eecs.umich.edu 1133598Sgblack@eecs.umich.edu public: 1143598Sgblack@eecs.umich.edu enum Status { 1153598Sgblack@eecs.umich.edu Running, 1163598Sgblack@eecs.umich.edu Idle, 1172516SN/A Halted, 1182516SN/A Blocked, 1192516SN/A SwitchedOut 1202516SN/A }; 1212482SN/A 1222482SN/A TheISA::TLB * itb; 1232591SN/A TheISA::TLB * dtb; 1242516SN/A 1252580SN/A /** Overall CPU status. */ 1262580SN/A Status _status; 1272482SN/A 1282482SN/A private: 1292591SN/A 1302516SN/A /** 1312580SN/A * IcachePort class for instruction fetch. 1322580SN/A */ 1332482SN/A class IcachePort : public MasterPort 1342482SN/A { 1352591SN/A protected: 1362516SN/A /** Pointer to fetch. */ 1372580SN/A DefaultFetch<Impl> *fetch; 1382580SN/A 1392482SN/A public: 1402482SN/A /** Default constructor. */ 1412591SN/A IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1422516SN/A : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1432580SN/A { } 1442580SN/A 1452482SN/A protected: 1462482SN/A 1472591SN/A /** Timing version of receive. Handles setting fetch to the 1482516SN/A * proper status to start fetching. */ 1492580SN/A virtual bool recvTimingResp(PacketPtr pkt); 1502580SN/A virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1512482SN/A 1522482SN/A /** Handles doing a retry of a failed fetch. */ 1532591SN/A virtual void recvReqRetry(); 1542516SN/A }; 1552580SN/A 1562580SN/A /** 1572482SN/A * DcachePort class for the load/store queue. 1582469SN/A */ 1592482SN/A class DcachePort : public MasterPort 1602516SN/A { 1613042Sgblack@eecs.umich.edu protected: 1624004Sgblack@eecs.umich.edu 1634004Sgblack@eecs.umich.edu /** Pointer to LSQ. */ 1644004Sgblack@eecs.umich.edu LSQ<Impl> *lsq; 1654004Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 1664004Sgblack@eecs.umich.edu 1674004Sgblack@eecs.umich.edu public: 1684004Sgblack@eecs.umich.edu /** Default constructor. */ 1694004Sgblack@eecs.umich.edu DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1704004Sgblack@eecs.umich.edu : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 1714004Sgblack@eecs.umich.edu cpu(_cpu) 1724004Sgblack@eecs.umich.edu { } 1734004Sgblack@eecs.umich.edu 1744004Sgblack@eecs.umich.edu protected: 1754004Sgblack@eecs.umich.edu 1764004Sgblack@eecs.umich.edu /** Timing version of receive. Handles writing back and 1774004Sgblack@eecs.umich.edu * completing the load or store that has returned from 1784004Sgblack@eecs.umich.edu * memory. */ 1794004Sgblack@eecs.umich.edu virtual bool recvTimingResp(PacketPtr pkt); 1804004Sgblack@eecs.umich.edu virtual void recvTimingSnoopReq(PacketPtr pkt); 1814004Sgblack@eecs.umich.edu 1824004Sgblack@eecs.umich.edu virtual void recvFunctionalSnoop(PacketPtr pkt) 1834004Sgblack@eecs.umich.edu { 1844004Sgblack@eecs.umich.edu // @todo: Is there a need for potential invalidation here? 1854004Sgblack@eecs.umich.edu } 1864004Sgblack@eecs.umich.edu 1874004Sgblack@eecs.umich.edu /** Handles doing a retry of the previous send. */ 1884004Sgblack@eecs.umich.edu virtual void recvReqRetry(); 1894004Sgblack@eecs.umich.edu 1904004Sgblack@eecs.umich.edu /** 1914004Sgblack@eecs.umich.edu * As this CPU requires snooping to maintain the load store queue 1924004Sgblack@eecs.umich.edu * change the behaviour from the base CPU port. 1934004Sgblack@eecs.umich.edu * 1944004Sgblack@eecs.umich.edu * @return true since we have to snoop 1954004Sgblack@eecs.umich.edu */ 1964004Sgblack@eecs.umich.edu virtual bool isSnooping() const { return true; } 1974004Sgblack@eecs.umich.edu }; 1984004Sgblack@eecs.umich.edu 1994004Sgblack@eecs.umich.edu class TickEvent : public Event 2004004Sgblack@eecs.umich.edu { 2014004Sgblack@eecs.umich.edu private: 2024004Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 2034004Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 2044004Sgblack@eecs.umich.edu 2054004Sgblack@eecs.umich.edu public: 2064004Sgblack@eecs.umich.edu /** Constructs a tick event. */ 2074004Sgblack@eecs.umich.edu TickEvent(FullO3CPU<Impl> *c); 2084004Sgblack@eecs.umich.edu 2094004Sgblack@eecs.umich.edu /** Processes a tick event, calling tick() on the CPU. */ 2104004Sgblack@eecs.umich.edu void process(); 2114004Sgblack@eecs.umich.edu /** Returns the description of the tick event. */ 2124004Sgblack@eecs.umich.edu const char *description() const; 2134004Sgblack@eecs.umich.edu }; 2144004Sgblack@eecs.umich.edu 2154004Sgblack@eecs.umich.edu /** The tick event used for scheduling CPU ticks. */ 2164004Sgblack@eecs.umich.edu TickEvent tickEvent; 2174004Sgblack@eecs.umich.edu 2184004Sgblack@eecs.umich.edu /** Schedule tick event, regardless of its current state. */ 2194004Sgblack@eecs.umich.edu void scheduleTickEvent(Cycles delay) 2204004Sgblack@eecs.umich.edu { 2214004Sgblack@eecs.umich.edu if (tickEvent.squashed()) 2224004Sgblack@eecs.umich.edu reschedule(tickEvent, clockEdge(delay)); 2234004Sgblack@eecs.umich.edu else if (!tickEvent.scheduled()) 2244004Sgblack@eecs.umich.edu schedule(tickEvent, clockEdge(delay)); 2254004Sgblack@eecs.umich.edu } 2264004Sgblack@eecs.umich.edu 2274004Sgblack@eecs.umich.edu /** Unschedule tick event, regardless of its current state. */ 2284004Sgblack@eecs.umich.edu void unscheduleTickEvent() 2294004Sgblack@eecs.umich.edu { 2304004Sgblack@eecs.umich.edu if (tickEvent.scheduled()) 2314004Sgblack@eecs.umich.edu tickEvent.squash(); 2324004Sgblack@eecs.umich.edu } 2334004Sgblack@eecs.umich.edu 2344004Sgblack@eecs.umich.edu /** 2354004Sgblack@eecs.umich.edu * Check if the pipeline has drained and signal drain done. 2364004Sgblack@eecs.umich.edu * 2374004Sgblack@eecs.umich.edu * This method checks if a drain has been requested and if the CPU 2384004Sgblack@eecs.umich.edu * has drained successfully (i.e., there are no instructions in 2394004Sgblack@eecs.umich.edu * the pipeline). If the CPU has drained, it deschedules the tick 2404004Sgblack@eecs.umich.edu * event and signals the drain manager. 2414004Sgblack@eecs.umich.edu * 2424004Sgblack@eecs.umich.edu * @return False if a drain hasn't been requested or the CPU 2434004Sgblack@eecs.umich.edu * hasn't drained, true otherwise. 2444004Sgblack@eecs.umich.edu */ 2454004Sgblack@eecs.umich.edu bool tryDrain(); 2464004Sgblack@eecs.umich.edu 2474004Sgblack@eecs.umich.edu /** 2482469SN/A * Perform sanity checks after a drain. 2492944Sgblack@eecs.umich.edu * 2503928Ssaidi@eecs.umich.edu * This method is called from drain() when it has determined that 2513928Ssaidi@eecs.umich.edu * the CPU is fully drained when gem5 is compiled with the NDEBUG 2523928Ssaidi@eecs.umich.edu * macro undefined. The intention of this method is to do more 2533928Ssaidi@eecs.umich.edu * extensive tests than the isDrained() method to weed out any 2542516SN/A * draining bugs. 2552469SN/A */ 2562469SN/A void drainSanityCheck() const; 2572482SN/A 2582482SN/A /** Check if a system is in a drained state. */ 2592974Sgblack@eecs.umich.edu bool isDrained() const; 2602974Sgblack@eecs.umich.edu 2612974Sgblack@eecs.umich.edu public: 2622526SN/A /** Constructs a CPU with the given parameters. */ 2632974Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2642974Sgblack@eecs.umich.edu /** Destructor. */ 2652974Sgblack@eecs.umich.edu ~FullO3CPU(); 2662646Ssaidi@eecs.umich.edu 2672974Sgblack@eecs.umich.edu /** Registers statistics. */ 2682469SN/A void regStats() override; 2692516SN/A 2702646Ssaidi@eecs.umich.edu ProbePointArg<PacketPtr> *ppInstAccessComplete; 2712482SN/A ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 2722469SN/A 2733931Ssaidi@eecs.umich.edu /** Register probe points. */ 2743900Ssaidi@eecs.umich.edu void regProbePoints() override; 2752482SN/A 2762954Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2772469SN/A { 2782516SN/A this->itb->demapPage(vaddr, asn); 2792516SN/A this->dtb->demapPage(vaddr, asn); 2802482SN/A } 2812469SN/A 2822516SN/A void demapInstPage(Addr vaddr, uint64_t asn) 2832482SN/A { 2842482SN/A this->itb->demapPage(vaddr, asn); 2852646Ssaidi@eecs.umich.edu } 2862482SN/A 2872482SN/A void demapDataPage(Addr vaddr, uint64_t asn) 2882482SN/A { 2892482SN/A this->dtb->demapPage(vaddr, asn); 2902482SN/A } 2912615SN/A 2922469SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2932469SN/A * activity to see if the CPU should deschedule itself. 2942482SN/A */ 2952646Ssaidi@eecs.umich.edu void tick(); 2963929Ssaidi@eecs.umich.edu 2972482SN/A /** Initialize the CPU */ 2983929Ssaidi@eecs.umich.edu void init() override; 2993929Ssaidi@eecs.umich.edu 3002482SN/A void startup() override; 3012526SN/A 3022469SN/A /** Returns the Number of Active Threads in the CPU */ 3032482SN/A int numActiveThreads() 3042469SN/A { return activeThreads.size(); } 3052516SN/A 3062469SN/A /** Add Thread to Active Threads List */ 3072580SN/A void activateThread(ThreadID tid); 3082469SN/A 3092580SN/A /** Remove Thread from Active Threads List */ 3102469SN/A void deactivateThread(ThreadID tid); 3112526SN/A 3122482SN/A /** Setup CPU to insert a thread's context */ 3132482SN/A void insertThread(ThreadID tid); 3142482SN/A 3152469SN/A /** Remove all of a thread's context from CPU */ 3162580SN/A void removeThread(ThreadID tid); 3172580SN/A 3182580SN/A /** Count the Total Instructions Committed in the CPU. */ 3192580SN/A Counter totalInsts() const override; 3202580SN/A 3212580SN/A /** Count the Total Ops (including micro ops) committed in the CPU. */ 3222580SN/A Counter totalOps() const override; 3232526SN/A 3242482SN/A /** Add Thread to Active Threads List. */ 3252482SN/A void activateContext(ThreadID tid) override; 3262482SN/A 3272469SN/A /** Remove Thread from Active Threads List */ 3282516SN/A void suspendContext(ThreadID tid) override; 3292646Ssaidi@eecs.umich.edu 3302469SN/A /** Remove Thread from Active Threads List && 3312580SN/A * Remove Thread Context from CPU. 3322469SN/A */ 3333931Ssaidi@eecs.umich.edu void haltContext(ThreadID tid) override; 3342469SN/A 3352526SN/A /** Update The Order In Which We Process Threads. */ 3363765Sgblack@eecs.umich.edu void updateThreadPriority(); 3372615SN/A 3382615SN/A /** Is the CPU draining? */ 3393765Sgblack@eecs.umich.edu bool isDraining() const { return drainState() == DrainState::Draining; } 3403765Sgblack@eecs.umich.edu 3412615SN/A void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 3423931Ssaidi@eecs.umich.edu void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 3433765Sgblack@eecs.umich.edu 3442469SN/A public: 3452516SN/A /** Executes a syscall. 3462646Ssaidi@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3472954Sgblack@eecs.umich.edu */ 3483931Ssaidi@eecs.umich.edu void syscall(int64_t callnum, ThreadID tid); 3492469SN/A 3503931Ssaidi@eecs.umich.edu /** Starts draining the CPU's pipeline of all instructions in 3512469SN/A * order to stop all memory accesses. */ 3522526SN/A DrainState drain() override; 3533765Sgblack@eecs.umich.edu 3542615SN/A /** Resumes execution after a drain. */ 3553765Sgblack@eecs.umich.edu void drainResume() override; 3562469SN/A 3572615SN/A /** 3582989Ssaidi@eecs.umich.edu * Commit has reached a safe point to drain a thread. 3592469SN/A * 3602469SN/A * Commit calls this method to inform the pipeline that it has 3612224SN/A * reached a point where it is not executed microcode and is about 3622646Ssaidi@eecs.umich.edu * to squash uncommitted instructions to fully drain the pipeline. 3632516SN/A */ 3642516SN/A void commitDrained(ThreadID tid); 3652516SN/A 3662469SN/A /** Switches out this CPU. */ 3672469SN/A void switchOut() override; 3682469SN/A 3692469SN/A /** Takes over from another CPU. */ 3702469SN/A void takeOverFrom(BaseCPU *oldCPU) override; 3712526SN/A 3722469SN/A void verifyMemoryMode() const override; 3732996Sgblack@eecs.umich.edu 3742996Sgblack@eecs.umich.edu /** Get the current instruction sequence number, and increment it. */ 3752469SN/A InstSeqNum getAndIncrementInstSeq() 3762469SN/A { return globalSeqNum++; } 3772469SN/A 3782996Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3793929Ssaidi@eecs.umich.edu void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 3803929Ssaidi@eecs.umich.edu 3812996Sgblack@eecs.umich.edu /** HW return from error interrupt. */ 3823929Ssaidi@eecs.umich.edu Fault hwrei(ThreadID tid); 3832469SN/A 3842469SN/A bool simPalCheck(int palFunc, ThreadID tid); 3852469SN/A 3862469SN/A /** Returns the Fault for any valid interrupt. */ 3872469SN/A Fault getInterrupts(); 3882526SN/A 3892469SN/A /** Processes any an interrupt fault. */ 3902516SN/A void processInterrupts(const Fault &interrupt); 3912469SN/A 3922469SN/A /** Halts the CPU. */ 3933753Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3942469SN/A 3952469SN/A /** Register accessors. Index refers to the physical register index. */ 3962469SN/A 3972526SN/A /** Reads a miscellaneous register. */ 3982469SN/A TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 3992516SN/A 4002469SN/A /** Reads a misc. register, including any side effects the read 4012469SN/A * might have as defined by the architecture. 4023753Sgblack@eecs.umich.edu */ 4032469SN/A TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4042469SN/A 4052469SN/A /** Sets a miscellaneous register. */ 4062526SN/A void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4072469SN/A ThreadID tid); 4082996Sgblack@eecs.umich.edu 4092996Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4102954Sgblack@eecs.umich.edu * might have as defined by the architecture. 4112954Sgblack@eecs.umich.edu */ 4122469SN/A void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4133753Sgblack@eecs.umich.edu ThreadID tid); 4142469SN/A 4152469SN/A uint64_t readIntReg(int reg_idx); 4162996Sgblack@eecs.umich.edu 4172526SN/A TheISA::FloatReg readFloatReg(int reg_idx); 4182469SN/A 4192516SN/A TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4202469SN/A 4212469SN/A TheISA::CCReg readCCReg(int reg_idx); 4222469SN/A 4233753Sgblack@eecs.umich.edu void setIntReg(int reg_idx, uint64_t val); 4242469SN/A 4252469SN/A void setFloatReg(int reg_idx, TheISA::FloatReg val); 4262469SN/A 4272526SN/A void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4282469SN/A 4292516SN/A void setCCReg(int reg_idx, TheISA::CCReg val); 4302469SN/A 4312469SN/A uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4322516SN/A 4333753Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4342646Ssaidi@eecs.umich.edu 4352469SN/A uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4362469SN/A 4372646Ssaidi@eecs.umich.edu TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 4383753Sgblack@eecs.umich.edu 4392469SN/A /** Architectural register accessors. Looks up in the commit 4402469SN/A * rename table to obtain the true physical index of the 4412469SN/A * architected register first, then accesses that physical 4422526SN/A * register. 4432526SN/A */ 4442526SN/A void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4452526SN/A 4462526SN/A void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4472526SN/A 4482526SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4492469SN/A 4502526SN/A void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 4512526SN/A 4522526SN/A /** Sets the commit PC state of a specific thread. */ 4532526SN/A void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4542526SN/A 4552526SN/A /** Reads the commit PC state of a specific thread. */ 4562526SN/A TheISA::PCState pcState(ThreadID tid); 4572526SN/A 4582954Sgblack@eecs.umich.edu /** Reads the commit PC of a specific thread. */ 4593929Ssaidi@eecs.umich.edu Addr instAddr(ThreadID tid); 4603587Sgblack@eecs.umich.edu 4613587Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4623587Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4633823Ssaidi@eecs.umich.edu 4643587Sgblack@eecs.umich.edu /** Reads the next PC of a specific thread. */ 4653587Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4663587Sgblack@eecs.umich.edu 4673587Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4683587Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4693587Sgblack@eecs.umich.edu * state through the TC. 4703587Sgblack@eecs.umich.edu */ 4713587Sgblack@eecs.umich.edu void squashFromTC(ThreadID tid); 4723587Sgblack@eecs.umich.edu 4733587Sgblack@eecs.umich.edu /** Function to add instruction onto the head of the list of the 4743587Sgblack@eecs.umich.edu * instructions. Used when new instructions are fetched. 4754040Ssaidi@eecs.umich.edu */ 4764040Ssaidi@eecs.umich.edu ListIt addInst(DynInstPtr &inst); 4772954Sgblack@eecs.umich.edu 4783587Sgblack@eecs.umich.edu /** Function to tell the CPU that an instruction has completed. */ 4793587Sgblack@eecs.umich.edu void instDone(ThreadID tid, DynInstPtr &inst); 4803587Sgblack@eecs.umich.edu 4813587Sgblack@eecs.umich.edu /** Remove an instruction from the front end of the list. There's 4824010Ssaidi@eecs.umich.edu * no restriction on location of the instruction. 4834010Ssaidi@eecs.umich.edu */ 4844010Ssaidi@eecs.umich.edu void removeFrontInst(DynInstPtr &inst); 4854010Ssaidi@eecs.umich.edu 4862954Sgblack@eecs.umich.edu /** Remove all instructions that are not currently in the ROB. 4873587Sgblack@eecs.umich.edu * There's also an option to not squash delay slot instructions.*/ 4883587Sgblack@eecs.umich.edu void removeInstsNotInROB(ThreadID tid); 4893823Ssaidi@eecs.umich.edu 4903823Ssaidi@eecs.umich.edu /** Remove all instructions younger than the given sequence number. */ 4913823Ssaidi@eecs.umich.edu void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 4923598Sgblack@eecs.umich.edu 4933598Sgblack@eecs.umich.edu /** Removes the instruction pointed to by the iterator. */ 4943598Sgblack@eecs.umich.edu inline void squashInstIt(const ListIt &instIt, ThreadID tid); 4953598Sgblack@eecs.umich.edu 4963598Sgblack@eecs.umich.edu /** Cleans up all instructions on the remove list. */ 4973598Sgblack@eecs.umich.edu void cleanUpRemovedInsts(); 4983598Sgblack@eecs.umich.edu 4993598Sgblack@eecs.umich.edu /** Debug function to print all instructions on the list. */ 5003598Sgblack@eecs.umich.edu void dumpInsts(); 5012954Sgblack@eecs.umich.edu 5023587Sgblack@eecs.umich.edu public: 5033587Sgblack@eecs.umich.edu#ifndef NDEBUG 5043587Sgblack@eecs.umich.edu /** Count of total number of dynamic instructions in flight. */ 5053587Sgblack@eecs.umich.edu int instcount; 5063587Sgblack@eecs.umich.edu#endif 5073587Sgblack@eecs.umich.edu 5083587Sgblack@eecs.umich.edu /** List of all the instructions in flight. */ 5093587Sgblack@eecs.umich.edu std::list<DynInstPtr> instList; 5103587Sgblack@eecs.umich.edu 5113587Sgblack@eecs.umich.edu /** List of all the instructions that will be removed at the end of this 5123587Sgblack@eecs.umich.edu * cycle. 5133587Sgblack@eecs.umich.edu */ 5143587Sgblack@eecs.umich.edu std::queue<ListIt> removeList; 5153823Ssaidi@eecs.umich.edu 5163587Sgblack@eecs.umich.edu#ifdef DEBUG 5173587Sgblack@eecs.umich.edu /** Debug structure to keep track of the sequence numbers still in 5183587Sgblack@eecs.umich.edu * flight. 5193587Sgblack@eecs.umich.edu */ 5203587Sgblack@eecs.umich.edu std::set<InstSeqNum> snList; 5213587Sgblack@eecs.umich.edu#endif 5223587Sgblack@eecs.umich.edu 5233587Sgblack@eecs.umich.edu /** Records if instructions need to be removed this cycle due to 5243587Sgblack@eecs.umich.edu * being retired or squashed. 5253587Sgblack@eecs.umich.edu */ 5263587Sgblack@eecs.umich.edu bool removeInstsThisCycle; 5273587Sgblack@eecs.umich.edu 5283587Sgblack@eecs.umich.edu protected: 5293587Sgblack@eecs.umich.edu /** The fetch stage. */ 5303587Sgblack@eecs.umich.edu typename CPUPolicy::Fetch fetch; 5313587Sgblack@eecs.umich.edu 5323587Sgblack@eecs.umich.edu /** The decode stage. */ 5333587Sgblack@eecs.umich.edu typename CPUPolicy::Decode decode; 5343587Sgblack@eecs.umich.edu 5353587Sgblack@eecs.umich.edu /** The dispatch stage. */ 5363587Sgblack@eecs.umich.edu typename CPUPolicy::Rename rename; 5373587Sgblack@eecs.umich.edu 5383823Ssaidi@eecs.umich.edu /** The issue/execute/writeback stages. */ 5393587Sgblack@eecs.umich.edu typename CPUPolicy::IEW iew; 5403587Sgblack@eecs.umich.edu 5413587Sgblack@eecs.umich.edu /** The commit stage. */ 5423587Sgblack@eecs.umich.edu typename CPUPolicy::Commit commit; 5433587Sgblack@eecs.umich.edu 5443587Sgblack@eecs.umich.edu /** The register file. */ 5453587Sgblack@eecs.umich.edu PhysRegFile regFile; 5463587Sgblack@eecs.umich.edu 5473587Sgblack@eecs.umich.edu /** The free list. */ 5483587Sgblack@eecs.umich.edu typename CPUPolicy::FreeList freeList; 5493587Sgblack@eecs.umich.edu 5503587Sgblack@eecs.umich.edu /** The rename map. */ 5513587Sgblack@eecs.umich.edu typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5523587Sgblack@eecs.umich.edu 5532526SN/A /** The commit rename map. */ 5543911Ssaidi@eecs.umich.edu typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5552526SN/A 5562526SN/A /** The re-order buffer. */ 5573909Ssaidi@eecs.umich.edu typename CPUPolicy::ROB rob; 5582526SN/A 5593909Ssaidi@eecs.umich.edu /** Active Threads List */ 5602526SN/A std::list<ThreadID> activeThreads; 5612526SN/A 5622526SN/A /** Integer Register Scoreboard */ 5632469SN/A Scoreboard scoreboard; 5642526SN/A 5652526SN/A std::vector<TheISA::ISA *> isa; 5662526SN/A 5672526SN/A /** Instruction port. Note that it has to appear after the fetch stage. */ 5682646Ssaidi@eecs.umich.edu IcachePort icachePort; 5692591SN/A 5702591SN/A /** Data port. Note that it has to appear after the iew stages */ 5712591SN/A DcachePort dcachePort; 5722526SN/A 5732526SN/A public: 5742646Ssaidi@eecs.umich.edu /** Enum to give each stage a specific index, so when calling 5752591SN/A * activateStage() or deactivateStage(), they can specify which stage 5762591SN/A * is being activated/deactivated. 5772591SN/A */ 5782526SN/A enum StageIdx { 5792224SN/A FetchIdx, 5802526SN/A DecodeIdx, 5812526SN/A RenameIdx, 5822615SN/A IEWIdx, 5832615SN/A CommitIdx, 5842526SN/A NumStages }; 5853941Ssaidi@eecs.umich.edu 5862526SN/A /** Typedefs from the Impl to get the structs that each of the 5872526SN/A * time buffers should use. 5882615SN/A */ 5892615SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5902615SN/A 5912615SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5922615SN/A 5932615SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5942526SN/A 5953587Sgblack@eecs.umich.edu typedef typename CPUPolicy::RenameStruct RenameStruct; 5963929Ssaidi@eecs.umich.edu 5973587Sgblack@eecs.umich.edu typedef typename CPUPolicy::IEWStruct IEWStruct; 5983587Sgblack@eecs.umich.edu 5993826Ssaidi@eecs.umich.edu /** The main time buffer to do backwards communication. */ 6003587Sgblack@eecs.umich.edu TimeBuffer<TimeStruct> timeBuffer; 6013587Sgblack@eecs.umich.edu 6023587Sgblack@eecs.umich.edu /** The fetch stage's instruction queue. */ 6033587Sgblack@eecs.umich.edu TimeBuffer<FetchStruct> fetchQueue; 6043587Sgblack@eecs.umich.edu 6053587Sgblack@eecs.umich.edu /** The decode stage's instruction queue. */ 6063587Sgblack@eecs.umich.edu TimeBuffer<DecodeStruct> decodeQueue; 6073587Sgblack@eecs.umich.edu 6083587Sgblack@eecs.umich.edu /** The rename stage's instruction queue. */ 6093587Sgblack@eecs.umich.edu TimeBuffer<RenameStruct> renameQueue; 6103587Sgblack@eecs.umich.edu 6113587Sgblack@eecs.umich.edu /** The IEW stage's instruction queue. */ 6123587Sgblack@eecs.umich.edu TimeBuffer<IEWStruct> iewQueue; 6133587Sgblack@eecs.umich.edu 6143587Sgblack@eecs.umich.edu private: 6153823Ssaidi@eecs.umich.edu /** The activity recorder; used to tell if the CPU has any 6163587Sgblack@eecs.umich.edu * activity remaining or if it can go to idle and deschedule 6173587Sgblack@eecs.umich.edu * itself. 6183587Sgblack@eecs.umich.edu */ 6193823Ssaidi@eecs.umich.edu ActivityRecorder activityRec; 6203587Sgblack@eecs.umich.edu 6213823Ssaidi@eecs.umich.edu public: 6223598Sgblack@eecs.umich.edu /** Records that there was time buffer activity this cycle. */ 6233598Sgblack@eecs.umich.edu void activityThisCycle() { activityRec.activity(); } 6243598Sgblack@eecs.umich.edu 6253598Sgblack@eecs.umich.edu /** Changes a stage's status to active within the activity recorder. */ 6263598Sgblack@eecs.umich.edu void activateStage(const StageIdx idx) 6273598Sgblack@eecs.umich.edu { activityRec.activateStage(idx); } 6283598Sgblack@eecs.umich.edu 6293598Sgblack@eecs.umich.edu /** Changes a stage's status to inactive within the activity recorder. */ 6303598Sgblack@eecs.umich.edu void deactivateStage(const StageIdx idx) 6313598Sgblack@eecs.umich.edu { activityRec.deactivateStage(idx); } 6323587Sgblack@eecs.umich.edu 6332526SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6343417Sgblack@eecs.umich.edu void wakeCPU(); 6353417Sgblack@eecs.umich.edu 6363417Sgblack@eecs.umich.edu virtual void wakeup(ThreadID tid) override; 6373417Sgblack@eecs.umich.edu 6383417Sgblack@eecs.umich.edu /** Gets a free thread id. Use if thread ids change across system. */ 6393417Sgblack@eecs.umich.edu ThreadID getFreeTid(); 6403417Sgblack@eecs.umich.edu 6413417Sgblack@eecs.umich.edu public: 6423417Sgblack@eecs.umich.edu /** Returns a pointer to a thread context. */ 6433598Sgblack@eecs.umich.edu ThreadContext * 6443417Sgblack@eecs.umich.edu tcBase(ThreadID tid) 6453417Sgblack@eecs.umich.edu { 6463417Sgblack@eecs.umich.edu return thread[tid]->getTC(); 6473417Sgblack@eecs.umich.edu } 6483417Sgblack@eecs.umich.edu 6493417Sgblack@eecs.umich.edu /** The global sequence number counter. */ 6503417Sgblack@eecs.umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6513928Ssaidi@eecs.umich.edu 6523928Ssaidi@eecs.umich.edu /** Pointer to the checker, which can dynamically verify 6533928Ssaidi@eecs.umich.edu * instruction results at run time. This can be set to NULL if it 6543417Sgblack@eecs.umich.edu * is not being used. 6552526SN/A */ 6563587Sgblack@eecs.umich.edu Checker<Impl> *checker; 6573587Sgblack@eecs.umich.edu 6583587Sgblack@eecs.umich.edu /** Pointer to the system. */ 6593587Sgblack@eecs.umich.edu System *system; 6603587Sgblack@eecs.umich.edu 6613587Sgblack@eecs.umich.edu /** Pointers to all of the threads in the CPU. */ 6623587Sgblack@eecs.umich.edu std::vector<Thread *> thread; 6633587Sgblack@eecs.umich.edu 6643587Sgblack@eecs.umich.edu /** Threads Scheduled to Enter CPU */ 6653587Sgblack@eecs.umich.edu std::list<int> cpuWaitList; 6663587Sgblack@eecs.umich.edu 6673587Sgblack@eecs.umich.edu /** The cycle that the CPU was last running, used for statistics. */ 6683587Sgblack@eecs.umich.edu Cycles lastRunningCycle; 6693587Sgblack@eecs.umich.edu 6703587Sgblack@eecs.umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6713587Sgblack@eecs.umich.edu Tick lastActivatedCycle; 6723587Sgblack@eecs.umich.edu 6733587Sgblack@eecs.umich.edu /** Mapping for system thread id to cpu id */ 6743587Sgblack@eecs.umich.edu std::map<ThreadID, unsigned> threadMap; 6753587Sgblack@eecs.umich.edu 6763587Sgblack@eecs.umich.edu /** Available thread ids in the cpu*/ 6773587Sgblack@eecs.umich.edu std::vector<ThreadID> tids; 6783587Sgblack@eecs.umich.edu 6793587Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 6803587Sgblack@eecs.umich.edu Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6813823Ssaidi@eecs.umich.edu int load_idx) 6823587Sgblack@eecs.umich.edu { 6833587Sgblack@eecs.umich.edu return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 6843587Sgblack@eecs.umich.edu } 6853587Sgblack@eecs.umich.edu 6863587Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 6873587Sgblack@eecs.umich.edu Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6883587Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 6893587Sgblack@eecs.umich.edu { 6903587Sgblack@eecs.umich.edu return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 6913587Sgblack@eecs.umich.edu data, store_idx); 6923587Sgblack@eecs.umich.edu } 6933587Sgblack@eecs.umich.edu 6943587Sgblack@eecs.umich.edu /** Used by the fetch unit to get a hold of the instruction port. */ 6953587Sgblack@eecs.umich.edu MasterPort &getInstPort() override { return icachePort; } 6963587Sgblack@eecs.umich.edu 6973587Sgblack@eecs.umich.edu /** Get the dcache port (used to find block size for translations). */ 6983587Sgblack@eecs.umich.edu MasterPort &getDataPort() override { return dcachePort; } 6993587Sgblack@eecs.umich.edu 7003587Sgblack@eecs.umich.edu /** Stat for total number of times the CPU is descheduled. */ 7013587Sgblack@eecs.umich.edu Stats::Scalar timesIdled; 7023587Sgblack@eecs.umich.edu /** Stat for total number of cycles the CPU spends descheduled. */ 7033587Sgblack@eecs.umich.edu Stats::Scalar idleCycles; 7043587Sgblack@eecs.umich.edu /** Stat for total number of cycles the CPU spends descheduled due to a 7053587Sgblack@eecs.umich.edu * quiesce operation or waiting for an interrupt. */ 7063587Sgblack@eecs.umich.edu Stats::Scalar quiesceCycles; 7073587Sgblack@eecs.umich.edu /** Stat for the number of committed instructions per thread. */ 7083587Sgblack@eecs.umich.edu Stats::Vector committedInsts; 7093587Sgblack@eecs.umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 7103587Sgblack@eecs.umich.edu Stats::Vector committedOps; 7113587Sgblack@eecs.umich.edu /** Stat for the CPI per thread. */ 7123587Sgblack@eecs.umich.edu Stats::Formula cpi; 7133587Sgblack@eecs.umich.edu /** Stat for the total CPI. */ 7143587Sgblack@eecs.umich.edu Stats::Formula totalCpi; 7153587Sgblack@eecs.umich.edu /** Stat for the IPC per thread. */ 7163587Sgblack@eecs.umich.edu Stats::Formula ipc; 7173587Sgblack@eecs.umich.edu /** Stat for the total IPC. */ 7183823Ssaidi@eecs.umich.edu Stats::Formula totalIpc; 7193587Sgblack@eecs.umich.edu 7202954Sgblack@eecs.umich.edu //number of integer register file accesses 7214008Ssaidi@eecs.umich.edu Stats::Scalar intRegfileReads; 7222963Sgblack@eecs.umich.edu Stats::Scalar intRegfileWrites; 7233279Sgblack@eecs.umich.edu //number of float register file accesses 7242963Sgblack@eecs.umich.edu Stats::Scalar fpRegfileReads; 7252963Sgblack@eecs.umich.edu Stats::Scalar fpRegfileWrites; 7262963Sgblack@eecs.umich.edu //number of CC register file accesses 7272963Sgblack@eecs.umich.edu Stats::Scalar ccRegfileReads; 7282963Sgblack@eecs.umich.edu Stats::Scalar ccRegfileWrites; 7293057Sgblack@eecs.umich.edu //number of misc 7302963Sgblack@eecs.umich.edu Stats::Scalar miscRegfileReads; 7312963Sgblack@eecs.umich.edu Stats::Scalar miscRegfileWrites; 7322963Sgblack@eecs.umich.edu}; 7332963Sgblack@eecs.umich.edu 7343995Sgblack@eecs.umich.edu#endif // __CPU_O3_CPU_HH__ 7352963Sgblack@eecs.umich.edu