cpu.hh revision 10698
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/types.hh" 57#include "base/statistics.hh" 58#include "config/the_isa.hh" 59#include "cpu/o3/comm.hh" 60#include "cpu/o3/cpu_policy.hh" 61#include "cpu/o3/scoreboard.hh" 62#include "cpu/o3/thread_state.hh" 63#include "cpu/activity.hh" 64#include "cpu/base.hh" 65#include "cpu/simple_thread.hh" 66#include "cpu/timebuf.hh" 67//#include "cpu/o3/thread_context.hh" 68#include "params/DerivO3CPU.hh" 69#include "sim/process.hh" 70 71template <class> 72class Checker; 73class ThreadContext; 74template <class> 75class O3ThreadContext; 76 77class Checkpoint; 78class MemObject; 79class Process; 80 81struct BaseCPUParams; 82 83class BaseO3CPU : public BaseCPU 84{ 85 //Stuff that's pretty ISA independent will go here. 86 public: 87 BaseO3CPU(BaseCPUParams *params); 88 89 void regStats(); 90}; 91 92/** 93 * FullO3CPU class, has each of the stages (fetch through commit) 94 * within it, as well as all of the time buffers between stages. The 95 * tick() function for the CPU is defined here. 96 */ 97template <class Impl> 98class FullO3CPU : public BaseO3CPU 99{ 100 public: 101 // Typedefs from the Impl here. 102 typedef typename Impl::CPUPol CPUPolicy; 103 typedef typename Impl::DynInstPtr DynInstPtr; 104 typedef typename Impl::O3CPU O3CPU; 105 106 typedef O3ThreadState<Impl> ImplState; 107 typedef O3ThreadState<Impl> Thread; 108 109 typedef typename std::list<DynInstPtr>::iterator ListIt; 110 111 friend class O3ThreadContext<Impl>; 112 113 public: 114 enum Status { 115 Running, 116 Idle, 117 Halted, 118 Blocked, 119 SwitchedOut 120 }; 121 122 TheISA::TLB * itb; 123 TheISA::TLB * dtb; 124 125 /** Overall CPU status. */ 126 Status _status; 127 128 private: 129 130 /** 131 * IcachePort class for instruction fetch. 132 */ 133 class IcachePort : public MasterPort 134 { 135 protected: 136 /** Pointer to fetch. */ 137 DefaultFetch<Impl> *fetch; 138 139 public: 140 /** Default constructor. */ 141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 143 { } 144 145 protected: 146 147 /** Timing version of receive. Handles setting fetch to the 148 * proper status to start fetching. */ 149 virtual bool recvTimingResp(PacketPtr pkt); 150 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 151 152 /** Handles doing a retry of a failed fetch. */ 153 virtual void recvRetry(); 154 }; 155 156 /** 157 * DcachePort class for the load/store queue. 158 */ 159 class DcachePort : public MasterPort 160 { 161 protected: 162 163 /** Pointer to LSQ. */ 164 LSQ<Impl> *lsq; 165 FullO3CPU<Impl> *cpu; 166 167 public: 168 /** Default constructor. */ 169 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 170 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 171 cpu(_cpu) 172 { } 173 174 protected: 175 176 /** Timing version of receive. Handles writing back and 177 * completing the load or store that has returned from 178 * memory. */ 179 virtual bool recvTimingResp(PacketPtr pkt); 180 virtual void recvTimingSnoopReq(PacketPtr pkt); 181 182 virtual void recvFunctionalSnoop(PacketPtr pkt) 183 { 184 // @todo: Is there a need for potential invalidation here? 185 } 186 187 /** Handles doing a retry of the previous send. */ 188 virtual void recvRetry(); 189 190 /** 191 * As this CPU requires snooping to maintain the load store queue 192 * change the behaviour from the base CPU port. 193 * 194 * @return true since we have to snoop 195 */ 196 virtual bool isSnooping() const { return true; } 197 }; 198 199 class TickEvent : public Event 200 { 201 private: 202 /** Pointer to the CPU. */ 203 FullO3CPU<Impl> *cpu; 204 205 public: 206 /** Constructs a tick event. */ 207 TickEvent(FullO3CPU<Impl> *c); 208 209 /** Processes a tick event, calling tick() on the CPU. */ 210 void process(); 211 /** Returns the description of the tick event. */ 212 const char *description() const; 213 }; 214 215 /** The tick event used for scheduling CPU ticks. */ 216 TickEvent tickEvent; 217 218 /** Schedule tick event, regardless of its current state. */ 219 void scheduleTickEvent(Cycles delay) 220 { 221 if (tickEvent.squashed()) 222 reschedule(tickEvent, clockEdge(delay)); 223 else if (!tickEvent.scheduled()) 224 schedule(tickEvent, clockEdge(delay)); 225 } 226 227 /** Unschedule tick event, regardless of its current state. */ 228 void unscheduleTickEvent() 229 { 230 if (tickEvent.scheduled()) 231 tickEvent.squash(); 232 } 233 234 /** 235 * Check if the pipeline has drained and signal the DrainManager. 236 * 237 * This method checks if a drain has been requested and if the CPU 238 * has drained successfully (i.e., there are no instructions in 239 * the pipeline). If the CPU has drained, it deschedules the tick 240 * event and signals the drain manager. 241 * 242 * @return False if a drain hasn't been requested or the CPU 243 * hasn't drained, true otherwise. 244 */ 245 bool tryDrain(); 246 247 /** 248 * Perform sanity checks after a drain. 249 * 250 * This method is called from drain() when it has determined that 251 * the CPU is fully drained when gem5 is compiled with the NDEBUG 252 * macro undefined. The intention of this method is to do more 253 * extensive tests than the isDrained() method to weed out any 254 * draining bugs. 255 */ 256 void drainSanityCheck() const; 257 258 /** Check if a system is in a drained state. */ 259 bool isDrained() const; 260 261 public: 262 /** Constructs a CPU with the given parameters. */ 263 FullO3CPU(DerivO3CPUParams *params); 264 /** Destructor. */ 265 ~FullO3CPU(); 266 267 /** Registers statistics. */ 268 void regStats(); 269 270 ProbePointArg<PacketPtr> *ppInstAccessComplete; 271 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 272 273 /** Register probe points. */ 274 void regProbePoints(); 275 276 void demapPage(Addr vaddr, uint64_t asn) 277 { 278 this->itb->demapPage(vaddr, asn); 279 this->dtb->demapPage(vaddr, asn); 280 } 281 282 void demapInstPage(Addr vaddr, uint64_t asn) 283 { 284 this->itb->demapPage(vaddr, asn); 285 } 286 287 void demapDataPage(Addr vaddr, uint64_t asn) 288 { 289 this->dtb->demapPage(vaddr, asn); 290 } 291 292 /** Ticks CPU, calling tick() on each stage, and checking the overall 293 * activity to see if the CPU should deschedule itself. 294 */ 295 void tick(); 296 297 /** Initialize the CPU */ 298 void init(); 299 300 void startup(); 301 302 /** Returns the Number of Active Threads in the CPU */ 303 int numActiveThreads() 304 { return activeThreads.size(); } 305 306 /** Add Thread to Active Threads List */ 307 void activateThread(ThreadID tid); 308 309 /** Remove Thread from Active Threads List */ 310 void deactivateThread(ThreadID tid); 311 312 /** Setup CPU to insert a thread's context */ 313 void insertThread(ThreadID tid); 314 315 /** Remove all of a thread's context from CPU */ 316 void removeThread(ThreadID tid); 317 318 /** Count the Total Instructions Committed in the CPU. */ 319 virtual Counter totalInsts() const; 320 321 /** Count the Total Ops (including micro ops) committed in the CPU. */ 322 virtual Counter totalOps() const; 323 324 /** Add Thread to Active Threads List. */ 325 void activateContext(ThreadID tid); 326 327 /** Remove Thread from Active Threads List */ 328 void suspendContext(ThreadID tid); 329 330 /** Remove Thread from Active Threads List && 331 * Remove Thread Context from CPU. 332 */ 333 void haltContext(ThreadID tid); 334 335 /** Update The Order In Which We Process Threads. */ 336 void updateThreadPriority(); 337 338 /** Is the CPU draining? */ 339 bool isDraining() const { return getDrainState() == Drainable::Draining; } 340 341 void serializeThread(std::ostream &os, ThreadID tid); 342 343 void unserializeThread(Checkpoint *cp, const std::string §ion, 344 ThreadID tid); 345 346 public: 347 /** Executes a syscall. 348 * @todo: Determine if this needs to be virtual. 349 */ 350 void syscall(int64_t callnum, ThreadID tid); 351 352 /** Starts draining the CPU's pipeline of all instructions in 353 * order to stop all memory accesses. */ 354 unsigned int drain(DrainManager *drain_manager); 355 356 /** Resumes execution after a drain. */ 357 void drainResume(); 358 359 /** 360 * Commit has reached a safe point to drain a thread. 361 * 362 * Commit calls this method to inform the pipeline that it has 363 * reached a point where it is not executed microcode and is about 364 * to squash uncommitted instructions to fully drain the pipeline. 365 */ 366 void commitDrained(ThreadID tid); 367 368 /** Switches out this CPU. */ 369 virtual void switchOut(); 370 371 /** Takes over from another CPU. */ 372 virtual void takeOverFrom(BaseCPU *oldCPU); 373 374 void verifyMemoryMode() const; 375 376 /** Get the current instruction sequence number, and increment it. */ 377 InstSeqNum getAndIncrementInstSeq() 378 { return globalSeqNum++; } 379 380 /** Traps to handle given fault. */ 381 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 382 383 /** HW return from error interrupt. */ 384 Fault hwrei(ThreadID tid); 385 386 bool simPalCheck(int palFunc, ThreadID tid); 387 388 /** Returns the Fault for any valid interrupt. */ 389 Fault getInterrupts(); 390 391 /** Processes any an interrupt fault. */ 392 void processInterrupts(const Fault &interrupt); 393 394 /** Halts the CPU. */ 395 void halt() { panic("Halt not implemented!\n"); } 396 397 /** Check if this address is a valid instruction address. */ 398 bool validInstAddr(Addr addr) { return true; } 399 400 /** Check if this address is a valid data address. */ 401 bool validDataAddr(Addr addr) { return true; } 402 403 /** Register accessors. Index refers to the physical register index. */ 404 405 /** Reads a miscellaneous register. */ 406 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 407 408 /** Reads a misc. register, including any side effects the read 409 * might have as defined by the architecture. 410 */ 411 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 412 413 /** Sets a miscellaneous register. */ 414 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 415 ThreadID tid); 416 417 /** Sets a misc. register, including any side effects the write 418 * might have as defined by the architecture. 419 */ 420 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 421 ThreadID tid); 422 423 uint64_t readIntReg(int reg_idx); 424 425 TheISA::FloatReg readFloatReg(int reg_idx); 426 427 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 428 429 TheISA::CCReg readCCReg(int reg_idx); 430 431 void setIntReg(int reg_idx, uint64_t val); 432 433 void setFloatReg(int reg_idx, TheISA::FloatReg val); 434 435 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 436 437 void setCCReg(int reg_idx, TheISA::CCReg val); 438 439 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 440 441 float readArchFloatReg(int reg_idx, ThreadID tid); 442 443 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 444 445 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 446 447 /** Architectural register accessors. Looks up in the commit 448 * rename table to obtain the true physical index of the 449 * architected register first, then accesses that physical 450 * register. 451 */ 452 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 453 454 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 455 456 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 457 458 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 459 460 /** Sets the commit PC state of a specific thread. */ 461 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 462 463 /** Reads the commit PC state of a specific thread. */ 464 TheISA::PCState pcState(ThreadID tid); 465 466 /** Reads the commit PC of a specific thread. */ 467 Addr instAddr(ThreadID tid); 468 469 /** Reads the commit micro PC of a specific thread. */ 470 MicroPC microPC(ThreadID tid); 471 472 /** Reads the next PC of a specific thread. */ 473 Addr nextInstAddr(ThreadID tid); 474 475 /** Initiates a squash of all in-flight instructions for a given 476 * thread. The source of the squash is an external update of 477 * state through the TC. 478 */ 479 void squashFromTC(ThreadID tid); 480 481 /** Function to add instruction onto the head of the list of the 482 * instructions. Used when new instructions are fetched. 483 */ 484 ListIt addInst(DynInstPtr &inst); 485 486 /** Function to tell the CPU that an instruction has completed. */ 487 void instDone(ThreadID tid, DynInstPtr &inst); 488 489 /** Remove an instruction from the front end of the list. There's 490 * no restriction on location of the instruction. 491 */ 492 void removeFrontInst(DynInstPtr &inst); 493 494 /** Remove all instructions that are not currently in the ROB. 495 * There's also an option to not squash delay slot instructions.*/ 496 void removeInstsNotInROB(ThreadID tid); 497 498 /** Remove all instructions younger than the given sequence number. */ 499 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 500 501 /** Removes the instruction pointed to by the iterator. */ 502 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 503 504 /** Cleans up all instructions on the remove list. */ 505 void cleanUpRemovedInsts(); 506 507 /** Debug function to print all instructions on the list. */ 508 void dumpInsts(); 509 510 public: 511#ifndef NDEBUG 512 /** Count of total number of dynamic instructions in flight. */ 513 int instcount; 514#endif 515 516 /** List of all the instructions in flight. */ 517 std::list<DynInstPtr> instList; 518 519 /** List of all the instructions that will be removed at the end of this 520 * cycle. 521 */ 522 std::queue<ListIt> removeList; 523 524#ifdef DEBUG 525 /** Debug structure to keep track of the sequence numbers still in 526 * flight. 527 */ 528 std::set<InstSeqNum> snList; 529#endif 530 531 /** Records if instructions need to be removed this cycle due to 532 * being retired or squashed. 533 */ 534 bool removeInstsThisCycle; 535 536 protected: 537 /** The fetch stage. */ 538 typename CPUPolicy::Fetch fetch; 539 540 /** The decode stage. */ 541 typename CPUPolicy::Decode decode; 542 543 /** The dispatch stage. */ 544 typename CPUPolicy::Rename rename; 545 546 /** The issue/execute/writeback stages. */ 547 typename CPUPolicy::IEW iew; 548 549 /** The commit stage. */ 550 typename CPUPolicy::Commit commit; 551 552 /** The register file. */ 553 PhysRegFile regFile; 554 555 /** The free list. */ 556 typename CPUPolicy::FreeList freeList; 557 558 /** The rename map. */ 559 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 560 561 /** The commit rename map. */ 562 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 563 564 /** The re-order buffer. */ 565 typename CPUPolicy::ROB rob; 566 567 /** Active Threads List */ 568 std::list<ThreadID> activeThreads; 569 570 /** Integer Register Scoreboard */ 571 Scoreboard scoreboard; 572 573 std::vector<TheISA::ISA *> isa; 574 575 /** Instruction port. Note that it has to appear after the fetch stage. */ 576 IcachePort icachePort; 577 578 /** Data port. Note that it has to appear after the iew stages */ 579 DcachePort dcachePort; 580 581 public: 582 /** Enum to give each stage a specific index, so when calling 583 * activateStage() or deactivateStage(), they can specify which stage 584 * is being activated/deactivated. 585 */ 586 enum StageIdx { 587 FetchIdx, 588 DecodeIdx, 589 RenameIdx, 590 IEWIdx, 591 CommitIdx, 592 NumStages }; 593 594 /** Typedefs from the Impl to get the structs that each of the 595 * time buffers should use. 596 */ 597 typedef typename CPUPolicy::TimeStruct TimeStruct; 598 599 typedef typename CPUPolicy::FetchStruct FetchStruct; 600 601 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 602 603 typedef typename CPUPolicy::RenameStruct RenameStruct; 604 605 typedef typename CPUPolicy::IEWStruct IEWStruct; 606 607 /** The main time buffer to do backwards communication. */ 608 TimeBuffer<TimeStruct> timeBuffer; 609 610 /** The fetch stage's instruction queue. */ 611 TimeBuffer<FetchStruct> fetchQueue; 612 613 /** The decode stage's instruction queue. */ 614 TimeBuffer<DecodeStruct> decodeQueue; 615 616 /** The rename stage's instruction queue. */ 617 TimeBuffer<RenameStruct> renameQueue; 618 619 /** The IEW stage's instruction queue. */ 620 TimeBuffer<IEWStruct> iewQueue; 621 622 private: 623 /** The activity recorder; used to tell if the CPU has any 624 * activity remaining or if it can go to idle and deschedule 625 * itself. 626 */ 627 ActivityRecorder activityRec; 628 629 public: 630 /** Records that there was time buffer activity this cycle. */ 631 void activityThisCycle() { activityRec.activity(); } 632 633 /** Changes a stage's status to active within the activity recorder. */ 634 void activateStage(const StageIdx idx) 635 { activityRec.activateStage(idx); } 636 637 /** Changes a stage's status to inactive within the activity recorder. */ 638 void deactivateStage(const StageIdx idx) 639 { activityRec.deactivateStage(idx); } 640 641 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 642 void wakeCPU(); 643 644 virtual void wakeup(); 645 646 /** Gets a free thread id. Use if thread ids change across system. */ 647 ThreadID getFreeTid(); 648 649 public: 650 /** Returns a pointer to a thread context. */ 651 ThreadContext * 652 tcBase(ThreadID tid) 653 { 654 return thread[tid]->getTC(); 655 } 656 657 /** The global sequence number counter. */ 658 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 659 660 /** Pointer to the checker, which can dynamically verify 661 * instruction results at run time. This can be set to NULL if it 662 * is not being used. 663 */ 664 Checker<Impl> *checker; 665 666 /** Pointer to the system. */ 667 System *system; 668 669 /** DrainManager to notify when draining has completed. */ 670 DrainManager *drainManager; 671 672 /** Pointers to all of the threads in the CPU. */ 673 std::vector<Thread *> thread; 674 675 /** Threads Scheduled to Enter CPU */ 676 std::list<int> cpuWaitList; 677 678 /** The cycle that the CPU was last running, used for statistics. */ 679 Cycles lastRunningCycle; 680 681 /** The cycle that the CPU was last activated by a new thread*/ 682 Tick lastActivatedCycle; 683 684 /** Mapping for system thread id to cpu id */ 685 std::map<ThreadID, unsigned> threadMap; 686 687 /** Available thread ids in the cpu*/ 688 std::vector<ThreadID> tids; 689 690 /** CPU read function, forwards read to LSQ. */ 691 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 692 uint8_t *data, int load_idx) 693 { 694 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 695 data, load_idx); 696 } 697 698 /** CPU write function, forwards write to LSQ. */ 699 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 700 uint8_t *data, int store_idx) 701 { 702 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 703 data, store_idx); 704 } 705 706 /** Used by the fetch unit to get a hold of the instruction port. */ 707 virtual MasterPort &getInstPort() { return icachePort; } 708 709 /** Get the dcache port (used to find block size for translations). */ 710 virtual MasterPort &getDataPort() { return dcachePort; } 711 712 /** Stat for total number of times the CPU is descheduled. */ 713 Stats::Scalar timesIdled; 714 /** Stat for total number of cycles the CPU spends descheduled. */ 715 Stats::Scalar idleCycles; 716 /** Stat for total number of cycles the CPU spends descheduled due to a 717 * quiesce operation or waiting for an interrupt. */ 718 Stats::Scalar quiesceCycles; 719 /** Stat for the number of committed instructions per thread. */ 720 Stats::Vector committedInsts; 721 /** Stat for the number of committed ops (including micro ops) per thread. */ 722 Stats::Vector committedOps; 723 /** Stat for the CPI per thread. */ 724 Stats::Formula cpi; 725 /** Stat for the total CPI. */ 726 Stats::Formula totalCpi; 727 /** Stat for the IPC per thread. */ 728 Stats::Formula ipc; 729 /** Stat for the total IPC. */ 730 Stats::Formula totalIpc; 731 732 //number of integer register file accesses 733 Stats::Scalar intRegfileReads; 734 Stats::Scalar intRegfileWrites; 735 //number of float register file accesses 736 Stats::Scalar fpRegfileReads; 737 Stats::Scalar fpRegfileWrites; 738 //number of CC register file accesses 739 Stats::Scalar ccRegfileReads; 740 Stats::Scalar ccRegfileWrites; 741 //number of misc 742 Stats::Scalar miscRegfileReads; 743 Stats::Scalar miscRegfileWrites; 744}; 745 746#endif // __CPU_O3_CPU_HH__ 747