cpu.hh revision 10225:01df075d9f93
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55 56#include "arch/types.hh" 57#include "base/statistics.hh" 58#include "config/the_isa.hh" 59#include "cpu/o3/comm.hh" 60#include "cpu/o3/cpu_policy.hh" 61#include "cpu/o3/scoreboard.hh" 62#include "cpu/o3/thread_state.hh" 63#include "cpu/activity.hh" 64#include "cpu/base.hh" 65#include "cpu/simple_thread.hh" 66#include "cpu/timebuf.hh" 67//#include "cpu/o3/thread_context.hh" 68#include "params/DerivO3CPU.hh" 69#include "sim/process.hh" 70 71template <class> 72class Checker; 73class ThreadContext; 74template <class> 75class O3ThreadContext; 76 77class Checkpoint; 78class MemObject; 79class Process; 80 81struct BaseCPUParams; 82 83class BaseO3CPU : public BaseCPU 84{ 85 //Stuff that's pretty ISA independent will go here. 86 public: 87 BaseO3CPU(BaseCPUParams *params); 88 89 void regStats(); 90}; 91 92/** 93 * FullO3CPU class, has each of the stages (fetch through commit) 94 * within it, as well as all of the time buffers between stages. The 95 * tick() function for the CPU is defined here. 96 */ 97template <class Impl> 98class FullO3CPU : public BaseO3CPU 99{ 100 public: 101 // Typedefs from the Impl here. 102 typedef typename Impl::CPUPol CPUPolicy; 103 typedef typename Impl::DynInstPtr DynInstPtr; 104 typedef typename Impl::O3CPU O3CPU; 105 106 typedef O3ThreadState<Impl> ImplState; 107 typedef O3ThreadState<Impl> Thread; 108 109 typedef typename std::list<DynInstPtr>::iterator ListIt; 110 111 friend class O3ThreadContext<Impl>; 112 113 public: 114 enum Status { 115 Running, 116 Idle, 117 Halted, 118 Blocked, 119 SwitchedOut 120 }; 121 122 TheISA::TLB * itb; 123 TheISA::TLB * dtb; 124 125 /** Overall CPU status. */ 126 Status _status; 127 128 private: 129 130 /** 131 * IcachePort class for instruction fetch. 132 */ 133 class IcachePort : public MasterPort 134 { 135 protected: 136 /** Pointer to fetch. */ 137 DefaultFetch<Impl> *fetch; 138 139 public: 140 /** Default constructor. */ 141 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 143 { } 144 145 protected: 146 147 /** Timing version of receive. Handles setting fetch to the 148 * proper status to start fetching. */ 149 virtual bool recvTimingResp(PacketPtr pkt); 150 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 151 152 /** Handles doing a retry of a failed fetch. */ 153 virtual void recvRetry(); 154 }; 155 156 /** 157 * DcachePort class for the load/store queue. 158 */ 159 class DcachePort : public MasterPort 160 { 161 protected: 162 163 /** Pointer to LSQ. */ 164 LSQ<Impl> *lsq; 165 166 public: 167 /** Default constructor. */ 168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 170 { } 171 172 protected: 173 174 /** Timing version of receive. Handles writing back and 175 * completing the load or store that has returned from 176 * memory. */ 177 virtual bool recvTimingResp(PacketPtr pkt); 178 virtual void recvTimingSnoopReq(PacketPtr pkt); 179 180 virtual void recvFunctionalSnoop(PacketPtr pkt) 181 { 182 // @todo: Is there a need for potential invalidation here? 183 } 184 185 /** Handles doing a retry of the previous send. */ 186 virtual void recvRetry(); 187 188 /** 189 * As this CPU requires snooping to maintain the load store queue 190 * change the behaviour from the base CPU port. 191 * 192 * @return true since we have to snoop 193 */ 194 virtual bool isSnooping() const { return true; } 195 }; 196 197 class TickEvent : public Event 198 { 199 private: 200 /** Pointer to the CPU. */ 201 FullO3CPU<Impl> *cpu; 202 203 public: 204 /** Constructs a tick event. */ 205 TickEvent(FullO3CPU<Impl> *c); 206 207 /** Processes a tick event, calling tick() on the CPU. */ 208 void process(); 209 /** Returns the description of the tick event. */ 210 const char *description() const; 211 }; 212 213 /** The tick event used for scheduling CPU ticks. */ 214 TickEvent tickEvent; 215 216 /** Schedule tick event, regardless of its current state. */ 217 void scheduleTickEvent(Cycles delay) 218 { 219 if (tickEvent.squashed()) 220 reschedule(tickEvent, clockEdge(delay)); 221 else if (!tickEvent.scheduled()) 222 schedule(tickEvent, clockEdge(delay)); 223 } 224 225 /** Unschedule tick event, regardless of its current state. */ 226 void unscheduleTickEvent() 227 { 228 if (tickEvent.scheduled()) 229 tickEvent.squash(); 230 } 231 232 class ActivateThreadEvent : public Event 233 { 234 private: 235 /** Number of Thread to Activate */ 236 ThreadID tid; 237 238 /** Pointer to the CPU. */ 239 FullO3CPU<Impl> *cpu; 240 241 public: 242 /** Constructs the event. */ 243 ActivateThreadEvent(); 244 245 /** Initialize Event */ 246 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 247 248 /** Processes the event, calling activateThread() on the CPU. */ 249 void process(); 250 251 /** Returns the description of the event. */ 252 const char *description() const; 253 }; 254 255 /** Schedule thread to activate , regardless of its current state. */ 256 void 257 scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 258 { 259 // Schedule thread to activate, regardless of its current state. 260 if (activateThreadEvent[tid].squashed()) 261 reschedule(activateThreadEvent[tid], 262 clockEdge(delay)); 263 else if (!activateThreadEvent[tid].scheduled()) { 264 Tick when = clockEdge(delay); 265 266 // Check if the deallocateEvent is also scheduled, and make 267 // sure they do not happen at same time causing a sleep that 268 // is never woken from. 269 if (deallocateContextEvent[tid].scheduled() && 270 deallocateContextEvent[tid].when() == when) { 271 when++; 272 } 273 274 schedule(activateThreadEvent[tid], when); 275 } 276 } 277 278 /** Unschedule actiavte thread event, regardless of its current state. */ 279 void 280 unscheduleActivateThreadEvent(ThreadID tid) 281 { 282 if (activateThreadEvent[tid].scheduled()) 283 activateThreadEvent[tid].squash(); 284 } 285 286 /** The tick event used for scheduling CPU ticks. */ 287 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 288 289 class DeallocateContextEvent : public Event 290 { 291 private: 292 /** Number of Thread to deactivate */ 293 ThreadID tid; 294 295 /** Should the thread be removed from the CPU? */ 296 bool remove; 297 298 /** Pointer to the CPU. */ 299 FullO3CPU<Impl> *cpu; 300 301 public: 302 /** Constructs the event. */ 303 DeallocateContextEvent(); 304 305 /** Initialize Event */ 306 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 307 308 /** Processes the event, calling activateThread() on the CPU. */ 309 void process(); 310 311 /** Sets whether the thread should also be removed from the CPU. */ 312 void setRemove(bool _remove) { remove = _remove; } 313 314 /** Returns the description of the event. */ 315 const char *description() const; 316 }; 317 318 /** Schedule cpu to deallocate thread context.*/ 319 void 320 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 321 { 322 // Schedule thread to activate, regardless of its current state. 323 if (deallocateContextEvent[tid].squashed()) 324 reschedule(deallocateContextEvent[tid], 325 clockEdge(delay)); 326 else if (!deallocateContextEvent[tid].scheduled()) 327 schedule(deallocateContextEvent[tid], 328 clockEdge(delay)); 329 } 330 331 /** Unschedule thread deallocation in CPU */ 332 void 333 unscheduleDeallocateContextEvent(ThreadID tid) 334 { 335 if (deallocateContextEvent[tid].scheduled()) 336 deallocateContextEvent[tid].squash(); 337 } 338 339 /** The tick event used for scheduling CPU ticks. */ 340 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 341 342 /** 343 * Check if the pipeline has drained and signal the DrainManager. 344 * 345 * This method checks if a drain has been requested and if the CPU 346 * has drained successfully (i.e., there are no instructions in 347 * the pipeline). If the CPU has drained, it deschedules the tick 348 * event and signals the drain manager. 349 * 350 * @return False if a drain hasn't been requested or the CPU 351 * hasn't drained, true otherwise. 352 */ 353 bool tryDrain(); 354 355 /** 356 * Perform sanity checks after a drain. 357 * 358 * This method is called from drain() when it has determined that 359 * the CPU is fully drained when gem5 is compiled with the NDEBUG 360 * macro undefined. The intention of this method is to do more 361 * extensive tests than the isDrained() method to weed out any 362 * draining bugs. 363 */ 364 void drainSanityCheck() const; 365 366 /** Check if a system is in a drained state. */ 367 bool isDrained() const; 368 369 public: 370 /** Constructs a CPU with the given parameters. */ 371 FullO3CPU(DerivO3CPUParams *params); 372 /** Destructor. */ 373 ~FullO3CPU(); 374 375 /** Registers statistics. */ 376 void regStats(); 377 378 ProbePointArg<PacketPtr> *ppInstAccessComplete; 379 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 380 381 /** Register probe points. */ 382 void regProbePoints(); 383 384 void demapPage(Addr vaddr, uint64_t asn) 385 { 386 this->itb->demapPage(vaddr, asn); 387 this->dtb->demapPage(vaddr, asn); 388 } 389 390 void demapInstPage(Addr vaddr, uint64_t asn) 391 { 392 this->itb->demapPage(vaddr, asn); 393 } 394 395 void demapDataPage(Addr vaddr, uint64_t asn) 396 { 397 this->dtb->demapPage(vaddr, asn); 398 } 399 400 /** Ticks CPU, calling tick() on each stage, and checking the overall 401 * activity to see if the CPU should deschedule itself. 402 */ 403 void tick(); 404 405 /** Initialize the CPU */ 406 void init(); 407 408 void startup(); 409 410 /** Returns the Number of Active Threads in the CPU */ 411 int numActiveThreads() 412 { return activeThreads.size(); } 413 414 /** Add Thread to Active Threads List */ 415 void activateThread(ThreadID tid); 416 417 /** Remove Thread from Active Threads List */ 418 void deactivateThread(ThreadID tid); 419 420 /** Setup CPU to insert a thread's context */ 421 void insertThread(ThreadID tid); 422 423 /** Remove all of a thread's context from CPU */ 424 void removeThread(ThreadID tid); 425 426 /** Count the Total Instructions Committed in the CPU. */ 427 virtual Counter totalInsts() const; 428 429 /** Count the Total Ops (including micro ops) committed in the CPU. */ 430 virtual Counter totalOps() const; 431 432 /** Add Thread to Active Threads List. */ 433 void activateContext(ThreadID tid, Cycles delay); 434 435 /** Remove Thread from Active Threads List */ 436 void suspendContext(ThreadID tid); 437 438 /** Remove Thread from Active Threads List && 439 * Possibly Remove Thread Context from CPU. 440 */ 441 bool scheduleDeallocateContext(ThreadID tid, bool remove, 442 Cycles delay = Cycles(1)); 443 444 /** Remove Thread from Active Threads List && 445 * Remove Thread Context from CPU. 446 */ 447 void haltContext(ThreadID tid); 448 449 /** Activate a Thread When CPU Resources are Available. */ 450 void activateWhenReady(ThreadID tid); 451 452 /** Add or Remove a Thread Context in the CPU. */ 453 void doContextSwitch(); 454 455 /** Update The Order In Which We Process Threads. */ 456 void updateThreadPriority(); 457 458 /** Is the CPU draining? */ 459 bool isDraining() const { return getDrainState() == Drainable::Draining; } 460 461 void serializeThread(std::ostream &os, ThreadID tid); 462 463 void unserializeThread(Checkpoint *cp, const std::string §ion, 464 ThreadID tid); 465 466 public: 467 /** Executes a syscall. 468 * @todo: Determine if this needs to be virtual. 469 */ 470 void syscall(int64_t callnum, ThreadID tid); 471 472 /** Starts draining the CPU's pipeline of all instructions in 473 * order to stop all memory accesses. */ 474 unsigned int drain(DrainManager *drain_manager); 475 476 /** Resumes execution after a drain. */ 477 void drainResume(); 478 479 /** 480 * Commit has reached a safe point to drain a thread. 481 * 482 * Commit calls this method to inform the pipeline that it has 483 * reached a point where it is not executed microcode and is about 484 * to squash uncommitted instructions to fully drain the pipeline. 485 */ 486 void commitDrained(ThreadID tid); 487 488 /** Switches out this CPU. */ 489 virtual void switchOut(); 490 491 /** Takes over from another CPU. */ 492 virtual void takeOverFrom(BaseCPU *oldCPU); 493 494 void verifyMemoryMode() const; 495 496 /** Get the current instruction sequence number, and increment it. */ 497 InstSeqNum getAndIncrementInstSeq() 498 { return globalSeqNum++; } 499 500 /** Traps to handle given fault. */ 501 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 502 503 /** HW return from error interrupt. */ 504 Fault hwrei(ThreadID tid); 505 506 bool simPalCheck(int palFunc, ThreadID tid); 507 508 /** Returns the Fault for any valid interrupt. */ 509 Fault getInterrupts(); 510 511 /** Processes any an interrupt fault. */ 512 void processInterrupts(Fault interrupt); 513 514 /** Halts the CPU. */ 515 void halt() { panic("Halt not implemented!\n"); } 516 517 /** Check if this address is a valid instruction address. */ 518 bool validInstAddr(Addr addr) { return true; } 519 520 /** Check if this address is a valid data address. */ 521 bool validDataAddr(Addr addr) { return true; } 522 523 /** Register accessors. Index refers to the physical register index. */ 524 525 /** Reads a miscellaneous register. */ 526 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 527 528 /** Reads a misc. register, including any side effects the read 529 * might have as defined by the architecture. 530 */ 531 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 532 533 /** Sets a miscellaneous register. */ 534 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 535 ThreadID tid); 536 537 /** Sets a misc. register, including any side effects the write 538 * might have as defined by the architecture. 539 */ 540 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 541 ThreadID tid); 542 543 uint64_t readIntReg(int reg_idx); 544 545 TheISA::FloatReg readFloatReg(int reg_idx); 546 547 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 548 549 TheISA::CCReg readCCReg(int reg_idx); 550 551 void setIntReg(int reg_idx, uint64_t val); 552 553 void setFloatReg(int reg_idx, TheISA::FloatReg val); 554 555 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 556 557 void setCCReg(int reg_idx, TheISA::CCReg val); 558 559 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 560 561 float readArchFloatReg(int reg_idx, ThreadID tid); 562 563 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 564 565 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 566 567 /** Architectural register accessors. Looks up in the commit 568 * rename table to obtain the true physical index of the 569 * architected register first, then accesses that physical 570 * register. 571 */ 572 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 573 574 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 575 576 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 577 578 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 579 580 /** Sets the commit PC state of a specific thread. */ 581 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 582 583 /** Reads the commit PC state of a specific thread. */ 584 TheISA::PCState pcState(ThreadID tid); 585 586 /** Reads the commit PC of a specific thread. */ 587 Addr instAddr(ThreadID tid); 588 589 /** Reads the commit micro PC of a specific thread. */ 590 MicroPC microPC(ThreadID tid); 591 592 /** Reads the next PC of a specific thread. */ 593 Addr nextInstAddr(ThreadID tid); 594 595 /** Initiates a squash of all in-flight instructions for a given 596 * thread. The source of the squash is an external update of 597 * state through the TC. 598 */ 599 void squashFromTC(ThreadID tid); 600 601 /** Function to add instruction onto the head of the list of the 602 * instructions. Used when new instructions are fetched. 603 */ 604 ListIt addInst(DynInstPtr &inst); 605 606 /** Function to tell the CPU that an instruction has completed. */ 607 void instDone(ThreadID tid, DynInstPtr &inst); 608 609 /** Remove an instruction from the front end of the list. There's 610 * no restriction on location of the instruction. 611 */ 612 void removeFrontInst(DynInstPtr &inst); 613 614 /** Remove all instructions that are not currently in the ROB. 615 * There's also an option to not squash delay slot instructions.*/ 616 void removeInstsNotInROB(ThreadID tid); 617 618 /** Remove all instructions younger than the given sequence number. */ 619 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 620 621 /** Removes the instruction pointed to by the iterator. */ 622 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 623 624 /** Cleans up all instructions on the remove list. */ 625 void cleanUpRemovedInsts(); 626 627 /** Debug function to print all instructions on the list. */ 628 void dumpInsts(); 629 630 public: 631#ifndef NDEBUG 632 /** Count of total number of dynamic instructions in flight. */ 633 int instcount; 634#endif 635 636 /** List of all the instructions in flight. */ 637 std::list<DynInstPtr> instList; 638 639 /** List of all the instructions that will be removed at the end of this 640 * cycle. 641 */ 642 std::queue<ListIt> removeList; 643 644#ifdef DEBUG 645 /** Debug structure to keep track of the sequence numbers still in 646 * flight. 647 */ 648 std::set<InstSeqNum> snList; 649#endif 650 651 /** Records if instructions need to be removed this cycle due to 652 * being retired or squashed. 653 */ 654 bool removeInstsThisCycle; 655 656 protected: 657 /** The fetch stage. */ 658 typename CPUPolicy::Fetch fetch; 659 660 /** The decode stage. */ 661 typename CPUPolicy::Decode decode; 662 663 /** The dispatch stage. */ 664 typename CPUPolicy::Rename rename; 665 666 /** The issue/execute/writeback stages. */ 667 typename CPUPolicy::IEW iew; 668 669 /** The commit stage. */ 670 typename CPUPolicy::Commit commit; 671 672 /** The register file. */ 673 PhysRegFile regFile; 674 675 /** The free list. */ 676 typename CPUPolicy::FreeList freeList; 677 678 /** The rename map. */ 679 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 680 681 /** The commit rename map. */ 682 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 683 684 /** The re-order buffer. */ 685 typename CPUPolicy::ROB rob; 686 687 /** Active Threads List */ 688 std::list<ThreadID> activeThreads; 689 690 /** Integer Register Scoreboard */ 691 Scoreboard scoreboard; 692 693 std::vector<TheISA::ISA *> isa; 694 695 /** Instruction port. Note that it has to appear after the fetch stage. */ 696 IcachePort icachePort; 697 698 /** Data port. Note that it has to appear after the iew stages */ 699 DcachePort dcachePort; 700 701 public: 702 /** Enum to give each stage a specific index, so when calling 703 * activateStage() or deactivateStage(), they can specify which stage 704 * is being activated/deactivated. 705 */ 706 enum StageIdx { 707 FetchIdx, 708 DecodeIdx, 709 RenameIdx, 710 IEWIdx, 711 CommitIdx, 712 NumStages }; 713 714 /** Typedefs from the Impl to get the structs that each of the 715 * time buffers should use. 716 */ 717 typedef typename CPUPolicy::TimeStruct TimeStruct; 718 719 typedef typename CPUPolicy::FetchStruct FetchStruct; 720 721 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 722 723 typedef typename CPUPolicy::RenameStruct RenameStruct; 724 725 typedef typename CPUPolicy::IEWStruct IEWStruct; 726 727 /** The main time buffer to do backwards communication. */ 728 TimeBuffer<TimeStruct> timeBuffer; 729 730 /** The fetch stage's instruction queue. */ 731 TimeBuffer<FetchStruct> fetchQueue; 732 733 /** The decode stage's instruction queue. */ 734 TimeBuffer<DecodeStruct> decodeQueue; 735 736 /** The rename stage's instruction queue. */ 737 TimeBuffer<RenameStruct> renameQueue; 738 739 /** The IEW stage's instruction queue. */ 740 TimeBuffer<IEWStruct> iewQueue; 741 742 private: 743 /** The activity recorder; used to tell if the CPU has any 744 * activity remaining or if it can go to idle and deschedule 745 * itself. 746 */ 747 ActivityRecorder activityRec; 748 749 public: 750 /** Records that there was time buffer activity this cycle. */ 751 void activityThisCycle() { activityRec.activity(); } 752 753 /** Changes a stage's status to active within the activity recorder. */ 754 void activateStage(const StageIdx idx) 755 { activityRec.activateStage(idx); } 756 757 /** Changes a stage's status to inactive within the activity recorder. */ 758 void deactivateStage(const StageIdx idx) 759 { activityRec.deactivateStage(idx); } 760 761 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 762 void wakeCPU(); 763 764 virtual void wakeup(); 765 766 /** Gets a free thread id. Use if thread ids change across system. */ 767 ThreadID getFreeTid(); 768 769 public: 770 /** Returns a pointer to a thread context. */ 771 ThreadContext * 772 tcBase(ThreadID tid) 773 { 774 return thread[tid]->getTC(); 775 } 776 777 /** The global sequence number counter. */ 778 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 779 780 /** Pointer to the checker, which can dynamically verify 781 * instruction results at run time. This can be set to NULL if it 782 * is not being used. 783 */ 784 Checker<Impl> *checker; 785 786 /** Pointer to the system. */ 787 System *system; 788 789 /** DrainManager to notify when draining has completed. */ 790 DrainManager *drainManager; 791 792 /** Pointers to all of the threads in the CPU. */ 793 std::vector<Thread *> thread; 794 795 /** Is there a context switch pending? */ 796 bool contextSwitch; 797 798 /** Threads Scheduled to Enter CPU */ 799 std::list<int> cpuWaitList; 800 801 /** The cycle that the CPU was last running, used for statistics. */ 802 Cycles lastRunningCycle; 803 804 /** The cycle that the CPU was last activated by a new thread*/ 805 Tick lastActivatedCycle; 806 807 /** Mapping for system thread id to cpu id */ 808 std::map<ThreadID, unsigned> threadMap; 809 810 /** Available thread ids in the cpu*/ 811 std::vector<ThreadID> tids; 812 813 /** CPU read function, forwards read to LSQ. */ 814 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 815 uint8_t *data, int load_idx) 816 { 817 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 818 data, load_idx); 819 } 820 821 /** CPU write function, forwards write to LSQ. */ 822 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 823 uint8_t *data, int store_idx) 824 { 825 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 826 data, store_idx); 827 } 828 829 /** Used by the fetch unit to get a hold of the instruction port. */ 830 virtual MasterPort &getInstPort() { return icachePort; } 831 832 /** Get the dcache port (used to find block size for translations). */ 833 virtual MasterPort &getDataPort() { return dcachePort; } 834 835 /** Stat for total number of times the CPU is descheduled. */ 836 Stats::Scalar timesIdled; 837 /** Stat for total number of cycles the CPU spends descheduled. */ 838 Stats::Scalar idleCycles; 839 /** Stat for total number of cycles the CPU spends descheduled due to a 840 * quiesce operation or waiting for an interrupt. */ 841 Stats::Scalar quiesceCycles; 842 /** Stat for the number of committed instructions per thread. */ 843 Stats::Vector committedInsts; 844 /** Stat for the number of committed ops (including micro ops) per thread. */ 845 Stats::Vector committedOps; 846 /** Stat for the CPI per thread. */ 847 Stats::Formula cpi; 848 /** Stat for the total CPI. */ 849 Stats::Formula totalCpi; 850 /** Stat for the IPC per thread. */ 851 Stats::Formula ipc; 852 /** Stat for the total IPC. */ 853 Stats::Formula totalIpc; 854 855 //number of integer register file accesses 856 Stats::Scalar intRegfileReads; 857 Stats::Scalar intRegfileWrites; 858 //number of float register file accesses 859 Stats::Scalar fpRegfileReads; 860 Stats::Scalar fpRegfileWrites; 861 //number of CC register file accesses 862 Stats::Scalar ccRegfileReads; 863 Stats::Scalar ccRegfileWrites; 864 //number of misc 865 Stats::Scalar miscRegfileReads; 866 Stats::Scalar miscRegfileWrites; 867}; 868 869#endif // __CPU_O3_CPU_HH__ 870