cpu.hh revision 9427
110447Snilay@cs.wisc.edu/* 210447Snilay@cs.wisc.edu * Copyright (c) 2011 ARM Limited 310447Snilay@cs.wisc.edu * All rights reserved 410447Snilay@cs.wisc.edu * 510447Snilay@cs.wisc.edu * The license below extends only to copyright in the software and shall 610447Snilay@cs.wisc.edu * not be construed as granting a license to any other intellectual 710447Snilay@cs.wisc.edu * property including but not limited to intellectual property relating 810447Snilay@cs.wisc.edu * to a hardware implementation of the functionality of the software 910447Snilay@cs.wisc.edu * licensed hereunder. You may use the software subject to the license 1010447Snilay@cs.wisc.edu * terms below provided that you ensure that this notice is replicated 1110447Snilay@cs.wisc.edu * unmodified and in its entirety in all distributions of the software, 1210447Snilay@cs.wisc.edu * modified or unmodified, in source code or in binary form. 1310447Snilay@cs.wisc.edu * 1410447Snilay@cs.wisc.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 1510447Snilay@cs.wisc.edu * Copyright (c) 2011 Regents of the University of California 1610447Snilay@cs.wisc.edu * All rights reserved. 1710447Snilay@cs.wisc.edu * 1810447Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 1910447Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 2010447Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 2110447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 2210447Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 2310447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 2410447Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 2510447Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 2610447Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 2710447Snilay@cs.wisc.edu * this software without specific prior written permission. 2810447Snilay@cs.wisc.edu * 2910447Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010447Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110447Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210447Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310447Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410447Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510447Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610447Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710447Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810447Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910447Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010447Snilay@cs.wisc.edu * 4110447Snilay@cs.wisc.edu * Authors: Kevin Lim 4210447Snilay@cs.wisc.edu * Korey Sewell 4310447Snilay@cs.wisc.edu * Rick Strong 4410447Snilay@cs.wisc.edu */ 4510447Snilay@cs.wisc.edu 4610447Snilay@cs.wisc.edu#ifndef __CPU_O3_CPU_HH__ 4710447Snilay@cs.wisc.edu#define __CPU_O3_CPU_HH__ 4810447Snilay@cs.wisc.edu 4910447Snilay@cs.wisc.edu#include <iostream> 5010447Snilay@cs.wisc.edu#include <list> 5110447Snilay@cs.wisc.edu#include <queue> 5210447Snilay@cs.wisc.edu#include <set> 5310447Snilay@cs.wisc.edu#include <vector> 5410447Snilay@cs.wisc.edu 5510447Snilay@cs.wisc.edu#include "arch/types.hh" 5610447Snilay@cs.wisc.edu#include "base/statistics.hh" 5710447Snilay@cs.wisc.edu#include "config/the_isa.hh" 5810447Snilay@cs.wisc.edu#include "cpu/o3/comm.hh" 5910447Snilay@cs.wisc.edu#include "cpu/o3/cpu_policy.hh" 6010447Snilay@cs.wisc.edu#include "cpu/o3/scoreboard.hh" 6110447Snilay@cs.wisc.edu#include "cpu/o3/thread_state.hh" 6210447Snilay@cs.wisc.edu#include "cpu/activity.hh" 6310447Snilay@cs.wisc.edu#include "cpu/base.hh" 6410447Snilay@cs.wisc.edu#include "cpu/simple_thread.hh" 6510447Snilay@cs.wisc.edu#include "cpu/timebuf.hh" 6610447Snilay@cs.wisc.edu//#include "cpu/o3/thread_context.hh" 6710447Snilay@cs.wisc.edu#include "params/DerivO3CPU.hh" 6810447Snilay@cs.wisc.edu#include "sim/process.hh" 6910447Snilay@cs.wisc.edu 7010447Snilay@cs.wisc.edutemplate <class> 7110447Snilay@cs.wisc.educlass Checker; 7210447Snilay@cs.wisc.educlass ThreadContext; 7310447Snilay@cs.wisc.edutemplate <class> 7410447Snilay@cs.wisc.educlass O3ThreadContext; 7510447Snilay@cs.wisc.edu 7610447Snilay@cs.wisc.educlass Checkpoint; 7710447Snilay@cs.wisc.educlass MemObject; 7810447Snilay@cs.wisc.educlass Process; 7910447Snilay@cs.wisc.edu 8010447Snilay@cs.wisc.edustruct BaseCPUParams; 8110447Snilay@cs.wisc.edu 8210447Snilay@cs.wisc.educlass BaseO3CPU : public BaseCPU 8310447Snilay@cs.wisc.edu{ 8410447Snilay@cs.wisc.edu //Stuff that's pretty ISA independent will go here. 8510447Snilay@cs.wisc.edu public: 8610447Snilay@cs.wisc.edu BaseO3CPU(BaseCPUParams *params); 8710447Snilay@cs.wisc.edu 8810447Snilay@cs.wisc.edu void regStats(); 8910447Snilay@cs.wisc.edu}; 9010447Snilay@cs.wisc.edu 9110447Snilay@cs.wisc.edu/** 9210447Snilay@cs.wisc.edu * FullO3CPU class, has each of the stages (fetch through commit) 9310447Snilay@cs.wisc.edu * within it, as well as all of the time buffers between stages. The 9410447Snilay@cs.wisc.edu * tick() function for the CPU is defined here. 9510447Snilay@cs.wisc.edu */ 9610447Snilay@cs.wisc.edutemplate <class Impl> 9710447Snilay@cs.wisc.educlass FullO3CPU : public BaseO3CPU 9810447Snilay@cs.wisc.edu{ 9910447Snilay@cs.wisc.edu public: 10010447Snilay@cs.wisc.edu // Typedefs from the Impl here. 10110447Snilay@cs.wisc.edu typedef typename Impl::CPUPol CPUPolicy; 10210447Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 10310447Snilay@cs.wisc.edu typedef typename Impl::O3CPU O3CPU; 10410447Snilay@cs.wisc.edu 10510447Snilay@cs.wisc.edu typedef O3ThreadState<Impl> ImplState; 10610447Snilay@cs.wisc.edu typedef O3ThreadState<Impl> Thread; 10710447Snilay@cs.wisc.edu 10810447Snilay@cs.wisc.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 10910447Snilay@cs.wisc.edu 11010447Snilay@cs.wisc.edu friend class O3ThreadContext<Impl>; 11110447Snilay@cs.wisc.edu 11210447Snilay@cs.wisc.edu public: 11310447Snilay@cs.wisc.edu enum Status { 11410447Snilay@cs.wisc.edu Running, 11510447Snilay@cs.wisc.edu Idle, 11610447Snilay@cs.wisc.edu Halted, 11710447Snilay@cs.wisc.edu Blocked, 11810447Snilay@cs.wisc.edu SwitchedOut 11910447Snilay@cs.wisc.edu }; 12010447Snilay@cs.wisc.edu 12110447Snilay@cs.wisc.edu TheISA::TLB * itb; 12210447Snilay@cs.wisc.edu TheISA::TLB * dtb; 12310447Snilay@cs.wisc.edu 12410447Snilay@cs.wisc.edu /** Overall CPU status. */ 12510447Snilay@cs.wisc.edu Status _status; 12610447Snilay@cs.wisc.edu 12710447Snilay@cs.wisc.edu /** Per-thread status in CPU, used for SMT. */ 12810447Snilay@cs.wisc.edu Status _threadStatus[Impl::MaxThreads]; 12910447Snilay@cs.wisc.edu 13010447Snilay@cs.wisc.edu private: 13110447Snilay@cs.wisc.edu 13210447Snilay@cs.wisc.edu /** 13310447Snilay@cs.wisc.edu * IcachePort class for instruction fetch. 13410447Snilay@cs.wisc.edu */ 13510447Snilay@cs.wisc.edu class IcachePort : public CpuPort 13610447Snilay@cs.wisc.edu { 13710447Snilay@cs.wisc.edu protected: 13810447Snilay@cs.wisc.edu /** Pointer to fetch. */ 13910447Snilay@cs.wisc.edu DefaultFetch<Impl> *fetch; 14010447Snilay@cs.wisc.edu 14110447Snilay@cs.wisc.edu public: 14210447Snilay@cs.wisc.edu /** Default constructor. */ 14310447Snilay@cs.wisc.edu IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 14410447Snilay@cs.wisc.edu : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 14510447Snilay@cs.wisc.edu { } 14610447Snilay@cs.wisc.edu 14710447Snilay@cs.wisc.edu protected: 14810447Snilay@cs.wisc.edu 14910447Snilay@cs.wisc.edu /** Timing version of receive. Handles setting fetch to the 15010447Snilay@cs.wisc.edu * proper status to start fetching. */ 15110447Snilay@cs.wisc.edu virtual bool recvTimingResp(PacketPtr pkt); 15210447Snilay@cs.wisc.edu virtual void recvTimingSnoopReq(PacketPtr pkt) { } 15310447Snilay@cs.wisc.edu 15410447Snilay@cs.wisc.edu /** Handles doing a retry of a failed fetch. */ 15510447Snilay@cs.wisc.edu virtual void recvRetry(); 15610447Snilay@cs.wisc.edu }; 15710447Snilay@cs.wisc.edu 15810447Snilay@cs.wisc.edu /** 15910447Snilay@cs.wisc.edu * DcachePort class for the load/store queue. 16010447Snilay@cs.wisc.edu */ 16110447Snilay@cs.wisc.edu class DcachePort : public CpuPort 16210447Snilay@cs.wisc.edu { 16310447Snilay@cs.wisc.edu protected: 16410447Snilay@cs.wisc.edu 16510447Snilay@cs.wisc.edu /** Pointer to LSQ. */ 16610447Snilay@cs.wisc.edu LSQ<Impl> *lsq; 16710447Snilay@cs.wisc.edu 16810447Snilay@cs.wisc.edu public: 16910447Snilay@cs.wisc.edu /** Default constructor. */ 17010447Snilay@cs.wisc.edu DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 17110447Snilay@cs.wisc.edu : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 17210447Snilay@cs.wisc.edu { } 17310447Snilay@cs.wisc.edu 17410447Snilay@cs.wisc.edu protected: 17510447Snilay@cs.wisc.edu 17610447Snilay@cs.wisc.edu /** Timing version of receive. Handles writing back and 17710447Snilay@cs.wisc.edu * completing the load or store that has returned from 17810447Snilay@cs.wisc.edu * memory. */ 17910447Snilay@cs.wisc.edu virtual bool recvTimingResp(PacketPtr pkt); 18010447Snilay@cs.wisc.edu virtual void recvTimingSnoopReq(PacketPtr pkt); 18110447Snilay@cs.wisc.edu 18210447Snilay@cs.wisc.edu /** Handles doing a retry of the previous send. */ 18310447Snilay@cs.wisc.edu virtual void recvRetry(); 18410447Snilay@cs.wisc.edu 18510447Snilay@cs.wisc.edu /** 18610447Snilay@cs.wisc.edu * As this CPU requires snooping to maintain the load store queue 18710447Snilay@cs.wisc.edu * change the behaviour from the base CPU port. 18810447Snilay@cs.wisc.edu * 18910447Snilay@cs.wisc.edu * @return true since we have to snoop 19010447Snilay@cs.wisc.edu */ 19110447Snilay@cs.wisc.edu virtual bool isSnooping() const { return true; } 19210447Snilay@cs.wisc.edu }; 19310447Snilay@cs.wisc.edu 19410447Snilay@cs.wisc.edu class TickEvent : public Event 19510447Snilay@cs.wisc.edu { 19610447Snilay@cs.wisc.edu private: 19710447Snilay@cs.wisc.edu /** Pointer to the CPU. */ 19810447Snilay@cs.wisc.edu FullO3CPU<Impl> *cpu; 19910447Snilay@cs.wisc.edu 20010447Snilay@cs.wisc.edu public: 20110447Snilay@cs.wisc.edu /** Constructs a tick event. */ 20210447Snilay@cs.wisc.edu TickEvent(FullO3CPU<Impl> *c); 20310447Snilay@cs.wisc.edu 20410447Snilay@cs.wisc.edu /** Processes a tick event, calling tick() on the CPU. */ 20510447Snilay@cs.wisc.edu void process(); 20610447Snilay@cs.wisc.edu /** Returns the description of the tick event. */ 20710447Snilay@cs.wisc.edu const char *description() const; 20810447Snilay@cs.wisc.edu }; 20910447Snilay@cs.wisc.edu 21010447Snilay@cs.wisc.edu /** The tick event used for scheduling CPU ticks. */ 21110447Snilay@cs.wisc.edu TickEvent tickEvent; 21210447Snilay@cs.wisc.edu 21310447Snilay@cs.wisc.edu /** Schedule tick event, regardless of its current state. */ 21410447Snilay@cs.wisc.edu void scheduleTickEvent(Cycles delay) 21510447Snilay@cs.wisc.edu { 21610447Snilay@cs.wisc.edu if (tickEvent.squashed()) 21710447Snilay@cs.wisc.edu reschedule(tickEvent, clockEdge(delay)); 21810447Snilay@cs.wisc.edu else if (!tickEvent.scheduled()) 21910447Snilay@cs.wisc.edu schedule(tickEvent, clockEdge(delay)); 22010447Snilay@cs.wisc.edu } 22110447Snilay@cs.wisc.edu 22210447Snilay@cs.wisc.edu /** Unschedule tick event, regardless of its current state. */ 22310447Snilay@cs.wisc.edu void unscheduleTickEvent() 22410447Snilay@cs.wisc.edu { 22510447Snilay@cs.wisc.edu if (tickEvent.scheduled()) 22610447Snilay@cs.wisc.edu tickEvent.squash(); 22710447Snilay@cs.wisc.edu } 22810447Snilay@cs.wisc.edu 22910447Snilay@cs.wisc.edu class ActivateThreadEvent : public Event 23010447Snilay@cs.wisc.edu { 23110447Snilay@cs.wisc.edu private: 23210447Snilay@cs.wisc.edu /** Number of Thread to Activate */ 23310447Snilay@cs.wisc.edu ThreadID tid; 23410447Snilay@cs.wisc.edu 23510447Snilay@cs.wisc.edu /** Pointer to the CPU. */ 23610447Snilay@cs.wisc.edu FullO3CPU<Impl> *cpu; 23710447Snilay@cs.wisc.edu 23810447Snilay@cs.wisc.edu public: 23910447Snilay@cs.wisc.edu /** Constructs the event. */ 24010447Snilay@cs.wisc.edu ActivateThreadEvent(); 24110447Snilay@cs.wisc.edu 24210447Snilay@cs.wisc.edu /** Initialize Event */ 24310447Snilay@cs.wisc.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 24410447Snilay@cs.wisc.edu 24510447Snilay@cs.wisc.edu /** Processes the event, calling activateThread() on the CPU. */ 24610447Snilay@cs.wisc.edu void process(); 24710447Snilay@cs.wisc.edu 24810447Snilay@cs.wisc.edu /** Returns the description of the event. */ 24910447Snilay@cs.wisc.edu const char *description() const; 25010447Snilay@cs.wisc.edu }; 25110447Snilay@cs.wisc.edu 25210447Snilay@cs.wisc.edu /** Schedule thread to activate , regardless of its current state. */ 25310447Snilay@cs.wisc.edu void 25410447Snilay@cs.wisc.edu scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 25510447Snilay@cs.wisc.edu { 25610447Snilay@cs.wisc.edu // Schedule thread to activate, regardless of its current state. 25710447Snilay@cs.wisc.edu if (activateThreadEvent[tid].squashed()) 25810447Snilay@cs.wisc.edu reschedule(activateThreadEvent[tid], 25910447Snilay@cs.wisc.edu clockEdge(delay)); 26010447Snilay@cs.wisc.edu else if (!activateThreadEvent[tid].scheduled()) { 26110447Snilay@cs.wisc.edu Tick when = clockEdge(delay); 26210447Snilay@cs.wisc.edu 26310447Snilay@cs.wisc.edu // Check if the deallocateEvent is also scheduled, and make 26410447Snilay@cs.wisc.edu // sure they do not happen at same time causing a sleep that 26510447Snilay@cs.wisc.edu // is never woken from. 26610447Snilay@cs.wisc.edu if (deallocateContextEvent[tid].scheduled() && 26710447Snilay@cs.wisc.edu deallocateContextEvent[tid].when() == when) { 26810447Snilay@cs.wisc.edu when++; 26910447Snilay@cs.wisc.edu } 27010447Snilay@cs.wisc.edu 27110447Snilay@cs.wisc.edu schedule(activateThreadEvent[tid], when); 27210447Snilay@cs.wisc.edu } 27310447Snilay@cs.wisc.edu } 27410447Snilay@cs.wisc.edu 27510447Snilay@cs.wisc.edu /** Unschedule actiavte thread event, regardless of its current state. */ 27610447Snilay@cs.wisc.edu void 27710447Snilay@cs.wisc.edu unscheduleActivateThreadEvent(ThreadID tid) 27810447Snilay@cs.wisc.edu { 27910447Snilay@cs.wisc.edu if (activateThreadEvent[tid].scheduled()) 28010447Snilay@cs.wisc.edu activateThreadEvent[tid].squash(); 28110447Snilay@cs.wisc.edu } 28210447Snilay@cs.wisc.edu 28310447Snilay@cs.wisc.edu /** The tick event used for scheduling CPU ticks. */ 28410447Snilay@cs.wisc.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 28510447Snilay@cs.wisc.edu 28610447Snilay@cs.wisc.edu class DeallocateContextEvent : public Event 28710447Snilay@cs.wisc.edu { 28810447Snilay@cs.wisc.edu private: 28910447Snilay@cs.wisc.edu /** Number of Thread to deactivate */ 29010447Snilay@cs.wisc.edu ThreadID tid; 29110447Snilay@cs.wisc.edu 29210447Snilay@cs.wisc.edu /** Should the thread be removed from the CPU? */ 29310447Snilay@cs.wisc.edu bool remove; 29410447Snilay@cs.wisc.edu 29510447Snilay@cs.wisc.edu /** Pointer to the CPU. */ 29610447Snilay@cs.wisc.edu FullO3CPU<Impl> *cpu; 29710447Snilay@cs.wisc.edu 29810447Snilay@cs.wisc.edu public: 29910447Snilay@cs.wisc.edu /** Constructs the event. */ 30010447Snilay@cs.wisc.edu DeallocateContextEvent(); 30110447Snilay@cs.wisc.edu 30210447Snilay@cs.wisc.edu /** Initialize Event */ 30310447Snilay@cs.wisc.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 30410447Snilay@cs.wisc.edu 30510447Snilay@cs.wisc.edu /** Processes the event, calling activateThread() on the CPU. */ 30610447Snilay@cs.wisc.edu void process(); 30710447Snilay@cs.wisc.edu 30810447Snilay@cs.wisc.edu /** Sets whether the thread should also be removed from the CPU. */ 30910447Snilay@cs.wisc.edu void setRemove(bool _remove) { remove = _remove; } 31010447Snilay@cs.wisc.edu 31110447Snilay@cs.wisc.edu /** Returns the description of the event. */ 31210447Snilay@cs.wisc.edu const char *description() const; 31310447Snilay@cs.wisc.edu }; 31410447Snilay@cs.wisc.edu 31510447Snilay@cs.wisc.edu /** Schedule cpu to deallocate thread context.*/ 31610447Snilay@cs.wisc.edu void 31710447Snilay@cs.wisc.edu scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 31810447Snilay@cs.wisc.edu { 31910447Snilay@cs.wisc.edu // Schedule thread to activate, regardless of its current state. 32010447Snilay@cs.wisc.edu if (deallocateContextEvent[tid].squashed()) 32110447Snilay@cs.wisc.edu reschedule(deallocateContextEvent[tid], 32210447Snilay@cs.wisc.edu clockEdge(delay)); 32310447Snilay@cs.wisc.edu else if (!deallocateContextEvent[tid].scheduled()) 32410447Snilay@cs.wisc.edu schedule(deallocateContextEvent[tid], 32510447Snilay@cs.wisc.edu clockEdge(delay)); 32610447Snilay@cs.wisc.edu } 32710447Snilay@cs.wisc.edu 32810447Snilay@cs.wisc.edu /** Unschedule thread deallocation in CPU */ 32910447Snilay@cs.wisc.edu void 33010447Snilay@cs.wisc.edu unscheduleDeallocateContextEvent(ThreadID tid) 33110447Snilay@cs.wisc.edu { 33210447Snilay@cs.wisc.edu if (deallocateContextEvent[tid].scheduled()) 33310447Snilay@cs.wisc.edu deallocateContextEvent[tid].squash(); 33410447Snilay@cs.wisc.edu } 33510447Snilay@cs.wisc.edu 33610447Snilay@cs.wisc.edu /** The tick event used for scheduling CPU ticks. */ 33710447Snilay@cs.wisc.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 33810447Snilay@cs.wisc.edu 339 public: 340 /** Constructs a CPU with the given parameters. */ 341 FullO3CPU(DerivO3CPUParams *params); 342 /** Destructor. */ 343 ~FullO3CPU(); 344 345 /** Registers statistics. */ 346 void regStats(); 347 348 void demapPage(Addr vaddr, uint64_t asn) 349 { 350 this->itb->demapPage(vaddr, asn); 351 this->dtb->demapPage(vaddr, asn); 352 } 353 354 void demapInstPage(Addr vaddr, uint64_t asn) 355 { 356 this->itb->demapPage(vaddr, asn); 357 } 358 359 void demapDataPage(Addr vaddr, uint64_t asn) 360 { 361 this->dtb->demapPage(vaddr, asn); 362 } 363 364 /** Ticks CPU, calling tick() on each stage, and checking the overall 365 * activity to see if the CPU should deschedule itself. 366 */ 367 void tick(); 368 369 /** Initialize the CPU */ 370 void init(); 371 372 void startup(); 373 374 /** Returns the Number of Active Threads in the CPU */ 375 int numActiveThreads() 376 { return activeThreads.size(); } 377 378 /** Add Thread to Active Threads List */ 379 void activateThread(ThreadID tid); 380 381 /** Remove Thread from Active Threads List */ 382 void deactivateThread(ThreadID tid); 383 384 /** Setup CPU to insert a thread's context */ 385 void insertThread(ThreadID tid); 386 387 /** Remove all of a thread's context from CPU */ 388 void removeThread(ThreadID tid); 389 390 /** Count the Total Instructions Committed in the CPU. */ 391 virtual Counter totalInsts() const; 392 393 /** Count the Total Ops (including micro ops) committed in the CPU. */ 394 virtual Counter totalOps() const; 395 396 /** Add Thread to Active Threads List. */ 397 void activateContext(ThreadID tid, Cycles delay); 398 399 /** Remove Thread from Active Threads List */ 400 void suspendContext(ThreadID tid); 401 402 /** Remove Thread from Active Threads List && 403 * Possibly Remove Thread Context from CPU. 404 */ 405 bool scheduleDeallocateContext(ThreadID tid, bool remove, 406 Cycles delay = Cycles(1)); 407 408 /** Remove Thread from Active Threads List && 409 * Remove Thread Context from CPU. 410 */ 411 void haltContext(ThreadID tid); 412 413 /** Activate a Thread When CPU Resources are Available. */ 414 void activateWhenReady(ThreadID tid); 415 416 /** Add or Remove a Thread Context in the CPU. */ 417 void doContextSwitch(); 418 419 /** Update The Order In Which We Process Threads. */ 420 void updateThreadPriority(); 421 422 /** Serialize state. */ 423 virtual void serialize(std::ostream &os); 424 425 /** Unserialize from a checkpoint. */ 426 virtual void unserialize(Checkpoint *cp, const std::string §ion); 427 428 public: 429 /** Executes a syscall. 430 * @todo: Determine if this needs to be virtual. 431 */ 432 void syscall(int64_t callnum, ThreadID tid); 433 434 /** Starts draining the CPU's pipeline of all instructions in 435 * order to stop all memory accesses. */ 436 unsigned int drain(DrainManager *drain_manager); 437 438 /** Resumes execution after a drain. */ 439 void drainResume(); 440 441 /** Signals to this CPU that a stage has completed switching out. */ 442 void signalDrained(); 443 444 /** Switches out this CPU. */ 445 virtual void switchOut(); 446 447 /** Takes over from another CPU. */ 448 virtual void takeOverFrom(BaseCPU *oldCPU); 449 450 /** Get the current instruction sequence number, and increment it. */ 451 InstSeqNum getAndIncrementInstSeq() 452 { return globalSeqNum++; } 453 454 /** Traps to handle given fault. */ 455 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 456 457 /** HW return from error interrupt. */ 458 Fault hwrei(ThreadID tid); 459 460 bool simPalCheck(int palFunc, ThreadID tid); 461 462 /** Returns the Fault for any valid interrupt. */ 463 Fault getInterrupts(); 464 465 /** Processes any an interrupt fault. */ 466 void processInterrupts(Fault interrupt); 467 468 /** Halts the CPU. */ 469 void halt() { panic("Halt not implemented!\n"); } 470 471 /** Check if this address is a valid instruction address. */ 472 bool validInstAddr(Addr addr) { return true; } 473 474 /** Check if this address is a valid data address. */ 475 bool validDataAddr(Addr addr) { return true; } 476 477 /** Register accessors. Index refers to the physical register index. */ 478 479 /** Reads a miscellaneous register. */ 480 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 481 482 /** Reads a misc. register, including any side effects the read 483 * might have as defined by the architecture. 484 */ 485 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 486 487 /** Sets a miscellaneous register. */ 488 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 489 ThreadID tid); 490 491 /** Sets a misc. register, including any side effects the write 492 * might have as defined by the architecture. 493 */ 494 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 495 ThreadID tid); 496 497 uint64_t readIntReg(int reg_idx); 498 499 TheISA::FloatReg readFloatReg(int reg_idx); 500 501 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 502 503 void setIntReg(int reg_idx, uint64_t val); 504 505 void setFloatReg(int reg_idx, TheISA::FloatReg val); 506 507 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 508 509 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 510 511 float readArchFloatReg(int reg_idx, ThreadID tid); 512 513 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 514 515 /** Architectural register accessors. Looks up in the commit 516 * rename table to obtain the true physical index of the 517 * architected register first, then accesses that physical 518 * register. 519 */ 520 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 521 522 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 523 524 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 525 526 /** Sets the commit PC state of a specific thread. */ 527 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 528 529 /** Reads the commit PC state of a specific thread. */ 530 TheISA::PCState pcState(ThreadID tid); 531 532 /** Reads the commit PC of a specific thread. */ 533 Addr instAddr(ThreadID tid); 534 535 /** Reads the commit micro PC of a specific thread. */ 536 MicroPC microPC(ThreadID tid); 537 538 /** Reads the next PC of a specific thread. */ 539 Addr nextInstAddr(ThreadID tid); 540 541 /** Initiates a squash of all in-flight instructions for a given 542 * thread. The source of the squash is an external update of 543 * state through the TC. 544 */ 545 void squashFromTC(ThreadID tid); 546 547 /** Function to add instruction onto the head of the list of the 548 * instructions. Used when new instructions are fetched. 549 */ 550 ListIt addInst(DynInstPtr &inst); 551 552 /** Function to tell the CPU that an instruction has completed. */ 553 void instDone(ThreadID tid, DynInstPtr &inst); 554 555 /** Remove an instruction from the front end of the list. There's 556 * no restriction on location of the instruction. 557 */ 558 void removeFrontInst(DynInstPtr &inst); 559 560 /** Remove all instructions that are not currently in the ROB. 561 * There's also an option to not squash delay slot instructions.*/ 562 void removeInstsNotInROB(ThreadID tid); 563 564 /** Remove all instructions younger than the given sequence number. */ 565 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 566 567 /** Removes the instruction pointed to by the iterator. */ 568 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 569 570 /** Cleans up all instructions on the remove list. */ 571 void cleanUpRemovedInsts(); 572 573 /** Debug function to print all instructions on the list. */ 574 void dumpInsts(); 575 576 public: 577#ifndef NDEBUG 578 /** Count of total number of dynamic instructions in flight. */ 579 int instcount; 580#endif 581 582 /** List of all the instructions in flight. */ 583 std::list<DynInstPtr> instList; 584 585 /** List of all the instructions that will be removed at the end of this 586 * cycle. 587 */ 588 std::queue<ListIt> removeList; 589 590#ifdef DEBUG 591 /** Debug structure to keep track of the sequence numbers still in 592 * flight. 593 */ 594 std::set<InstSeqNum> snList; 595#endif 596 597 /** Records if instructions need to be removed this cycle due to 598 * being retired or squashed. 599 */ 600 bool removeInstsThisCycle; 601 602 protected: 603 /** The fetch stage. */ 604 typename CPUPolicy::Fetch fetch; 605 606 /** The decode stage. */ 607 typename CPUPolicy::Decode decode; 608 609 /** The dispatch stage. */ 610 typename CPUPolicy::Rename rename; 611 612 /** The issue/execute/writeback stages. */ 613 typename CPUPolicy::IEW iew; 614 615 /** The commit stage. */ 616 typename CPUPolicy::Commit commit; 617 618 /** The register file. */ 619 typename CPUPolicy::RegFile regFile; 620 621 /** The free list. */ 622 typename CPUPolicy::FreeList freeList; 623 624 /** The rename map. */ 625 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 626 627 /** The commit rename map. */ 628 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 629 630 /** The re-order buffer. */ 631 typename CPUPolicy::ROB rob; 632 633 /** Active Threads List */ 634 std::list<ThreadID> activeThreads; 635 636 /** Integer Register Scoreboard */ 637 Scoreboard scoreboard; 638 639 std::vector<TheISA::ISA *> isa; 640 641 /** Instruction port. Note that it has to appear after the fetch stage. */ 642 IcachePort icachePort; 643 644 /** Data port. Note that it has to appear after the iew stages */ 645 DcachePort dcachePort; 646 647 public: 648 /** Enum to give each stage a specific index, so when calling 649 * activateStage() or deactivateStage(), they can specify which stage 650 * is being activated/deactivated. 651 */ 652 enum StageIdx { 653 FetchIdx, 654 DecodeIdx, 655 RenameIdx, 656 IEWIdx, 657 CommitIdx, 658 NumStages }; 659 660 /** Typedefs from the Impl to get the structs that each of the 661 * time buffers should use. 662 */ 663 typedef typename CPUPolicy::TimeStruct TimeStruct; 664 665 typedef typename CPUPolicy::FetchStruct FetchStruct; 666 667 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 668 669 typedef typename CPUPolicy::RenameStruct RenameStruct; 670 671 typedef typename CPUPolicy::IEWStruct IEWStruct; 672 673 /** The main time buffer to do backwards communication. */ 674 TimeBuffer<TimeStruct> timeBuffer; 675 676 /** The fetch stage's instruction queue. */ 677 TimeBuffer<FetchStruct> fetchQueue; 678 679 /** The decode stage's instruction queue. */ 680 TimeBuffer<DecodeStruct> decodeQueue; 681 682 /** The rename stage's instruction queue. */ 683 TimeBuffer<RenameStruct> renameQueue; 684 685 /** The IEW stage's instruction queue. */ 686 TimeBuffer<IEWStruct> iewQueue; 687 688 private: 689 /** The activity recorder; used to tell if the CPU has any 690 * activity remaining or if it can go to idle and deschedule 691 * itself. 692 */ 693 ActivityRecorder activityRec; 694 695 public: 696 /** Records that there was time buffer activity this cycle. */ 697 void activityThisCycle() { activityRec.activity(); } 698 699 /** Changes a stage's status to active within the activity recorder. */ 700 void activateStage(const StageIdx idx) 701 { activityRec.activateStage(idx); } 702 703 /** Changes a stage's status to inactive within the activity recorder. */ 704 void deactivateStage(const StageIdx idx) 705 { activityRec.deactivateStage(idx); } 706 707 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 708 void wakeCPU(); 709 710 virtual void wakeup(); 711 712 /** Gets a free thread id. Use if thread ids change across system. */ 713 ThreadID getFreeTid(); 714 715 public: 716 /** Returns a pointer to a thread context. */ 717 ThreadContext * 718 tcBase(ThreadID tid) 719 { 720 return thread[tid]->getTC(); 721 } 722 723 /** The global sequence number counter. */ 724 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 725 726 /** Pointer to the checker, which can dynamically verify 727 * instruction results at run time. This can be set to NULL if it 728 * is not being used. 729 */ 730 Checker<Impl> *checker; 731 732 /** Pointer to the system. */ 733 System *system; 734 735 /** DrainManager to notify when draining has completed. */ 736 DrainManager *drainManager; 737 738 /** Counter of how many stages have completed draining. */ 739 int drainCount; 740 741 /** Pointers to all of the threads in the CPU. */ 742 std::vector<Thread *> thread; 743 744 /** Whether or not the CPU should defer its registration. */ 745 bool deferRegistration; 746 747 /** Is there a context switch pending? */ 748 bool contextSwitch; 749 750 /** Threads Scheduled to Enter CPU */ 751 std::list<int> cpuWaitList; 752 753 /** The cycle that the CPU was last running, used for statistics. */ 754 Cycles lastRunningCycle; 755 756 /** The cycle that the CPU was last activated by a new thread*/ 757 Tick lastActivatedCycle; 758 759 /** Mapping for system thread id to cpu id */ 760 std::map<ThreadID, unsigned> threadMap; 761 762 /** Available thread ids in the cpu*/ 763 std::vector<ThreadID> tids; 764 765 /** CPU read function, forwards read to LSQ. */ 766 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 767 uint8_t *data, int load_idx) 768 { 769 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 770 data, load_idx); 771 } 772 773 /** CPU write function, forwards write to LSQ. */ 774 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 775 uint8_t *data, int store_idx) 776 { 777 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 778 data, store_idx); 779 } 780 781 /** Used by the fetch unit to get a hold of the instruction port. */ 782 virtual CpuPort &getInstPort() { return icachePort; } 783 784 /** Get the dcache port (used to find block size for translations). */ 785 virtual CpuPort &getDataPort() { return dcachePort; } 786 787 Addr lockAddr; 788 789 /** Temporary fix for the lock flag, works in the UP case. */ 790 bool lockFlag; 791 792 /** Stat for total number of times the CPU is descheduled. */ 793 Stats::Scalar timesIdled; 794 /** Stat for total number of cycles the CPU spends descheduled. */ 795 Stats::Scalar idleCycles; 796 /** Stat for total number of cycles the CPU spends descheduled due to a 797 * quiesce operation or waiting for an interrupt. */ 798 Stats::Scalar quiesceCycles; 799 /** Stat for the number of committed instructions per thread. */ 800 Stats::Vector committedInsts; 801 /** Stat for the number of committed ops (including micro ops) per thread. */ 802 Stats::Vector committedOps; 803 /** Stat for the total number of committed instructions. */ 804 Stats::Scalar totalCommittedInsts; 805 /** Stat for the CPI per thread. */ 806 Stats::Formula cpi; 807 /** Stat for the total CPI. */ 808 Stats::Formula totalCpi; 809 /** Stat for the IPC per thread. */ 810 Stats::Formula ipc; 811 /** Stat for the total IPC. */ 812 Stats::Formula totalIpc; 813 814 //number of integer register file accesses 815 Stats::Scalar intRegfileReads; 816 Stats::Scalar intRegfileWrites; 817 //number of float register file accesses 818 Stats::Scalar fpRegfileReads; 819 Stats::Scalar fpRegfileWrites; 820 //number of misc 821 Stats::Scalar miscRegfileReads; 822 Stats::Scalar miscRegfileWrites; 823}; 824 825#endif // __CPU_O3_CPU_HH__ 826