cpu.hh revision 8707
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 462325SN/A#ifndef __CPU_O3_CPU_HH__ 472325SN/A#define __CPU_O3_CPU_HH__ 481060SN/A 491060SN/A#include <iostream> 501060SN/A#include <list> 512292SN/A#include <queue> 522292SN/A#include <set> 531681SN/A#include <vector> 541060SN/A 552980Sgblack@eecs.umich.edu#include "arch/types.hh" 561060SN/A#include "base/statistics.hh" 571858SN/A#include "config/full_system.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 594598Sbinkertn@umich.edu#include "config/use_checker.hh" 601717SN/A#include "cpu/o3/comm.hh" 611717SN/A#include "cpu/o3/cpu_policy.hh" 622292SN/A#include "cpu/o3/scoreboard.hh" 632292SN/A#include "cpu/o3/thread_state.hh" 648229Snate@binkert.org#include "cpu/activity.hh" 658229Snate@binkert.org#include "cpu/base.hh" 668229Snate@binkert.org#include "cpu/simple_thread.hh" 678229Snate@binkert.org#include "cpu/timebuf.hh" 682817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 698229Snate@binkert.org#include "params/DerivO3CPU.hh" 701060SN/A#include "sim/process.hh" 711060SN/A 722316SN/Atemplate <class> 732316SN/Aclass Checker; 742680Sktlim@umich.educlass ThreadContext; 752817Sksewell@umich.edutemplate <class> 762817Sksewell@umich.educlass O3ThreadContext; 772843Sktlim@umich.edu 782843Sktlim@umich.educlass Checkpoint; 792669Sktlim@umich.educlass MemObject; 801060SN/Aclass Process; 811060SN/A 825529Snate@binkert.orgclass BaseCPUParams; 835529Snate@binkert.org 842733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 851060SN/A{ 861060SN/A //Stuff that's pretty ISA independent will go here. 871060SN/A public: 885529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 892292SN/A 902292SN/A void regStats(); 911060SN/A}; 921060SN/A 932348SN/A/** 942348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 952348SN/A * within it, as well as all of the time buffers between stages. The 962348SN/A * tick() function for the CPU is defined here. 972348SN/A */ 981060SN/Atemplate <class Impl> 992733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 1001060SN/A{ 1011060SN/A public: 1022325SN/A // Typedefs from the Impl here. 1031060SN/A typedef typename Impl::CPUPol CPUPolicy; 1041061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1054329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1061060SN/A 1075595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1082292SN/A typedef O3ThreadState<Impl> Thread; 1092292SN/A 1102292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1112292SN/A 1122817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1132829Sksewell@umich.edu 1141060SN/A public: 1151060SN/A enum Status { 1161060SN/A Running, 1171060SN/A Idle, 1181060SN/A Halted, 1192307SN/A Blocked, 1202307SN/A SwitchedOut 1211060SN/A }; 1221060SN/A 1236022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1246022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1253781Sgblack@eecs.umich.edu 1262292SN/A /** Overall CPU status. */ 1271060SN/A Status _status; 1281060SN/A 1292829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1302829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1312829Sksewell@umich.edu 1321060SN/A private: 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com /** 1358707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1368707Sandreas.hansson@arm.com */ 1378707Sandreas.hansson@arm.com class IcachePort : public CpuPort 1388707Sandreas.hansson@arm.com { 1398707Sandreas.hansson@arm.com protected: 1408707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1418707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1428707Sandreas.hansson@arm.com 1438707Sandreas.hansson@arm.com public: 1448707Sandreas.hansson@arm.com /** Default constructor. */ 1458707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1468707Sandreas.hansson@arm.com : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) 1478707Sandreas.hansson@arm.com { } 1488707Sandreas.hansson@arm.com 1498707Sandreas.hansson@arm.com protected: 1508707Sandreas.hansson@arm.com 1518707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1528707Sandreas.hansson@arm.com * proper status to start fetching. */ 1538707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1548707Sandreas.hansson@arm.com 1558707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 1568707Sandreas.hansson@arm.com virtual void recvRetry(); 1578707Sandreas.hansson@arm.com }; 1588707Sandreas.hansson@arm.com 1598707Sandreas.hansson@arm.com /** 1608707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1618707Sandreas.hansson@arm.com */ 1628707Sandreas.hansson@arm.com class DcachePort : public CpuPort 1638707Sandreas.hansson@arm.com { 1648707Sandreas.hansson@arm.com protected: 1658707Sandreas.hansson@arm.com 1668707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1678707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 1688707Sandreas.hansson@arm.com 1698707Sandreas.hansson@arm.com public: 1708707Sandreas.hansson@arm.com /** Default constructor. */ 1718707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1728707Sandreas.hansson@arm.com : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq) 1738707Sandreas.hansson@arm.com { } 1748707Sandreas.hansson@arm.com 1758707Sandreas.hansson@arm.com protected: 1768707Sandreas.hansson@arm.com 1778707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1788707Sandreas.hansson@arm.com * completing the load or store that has returned from 1798707Sandreas.hansson@arm.com * memory. */ 1808707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1818707Sandreas.hansson@arm.com 1828707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 1838707Sandreas.hansson@arm.com virtual void recvRetry(); 1848707Sandreas.hansson@arm.com 1858707Sandreas.hansson@arm.com /** 1868707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1878707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1888707Sandreas.hansson@arm.com * 1898707Sandreas.hansson@arm.com * @param resp list of ranges this port responds to 1908707Sandreas.hansson@arm.com * @param snoop indicating if the port snoops or not 1918707Sandreas.hansson@arm.com */ 1928707Sandreas.hansson@arm.com virtual void getDeviceAddressRanges(AddrRangeList& resp, 1938707Sandreas.hansson@arm.com bool& snoop) 1948707Sandreas.hansson@arm.com { resp.clear(); snoop = true; } 1958707Sandreas.hansson@arm.com }; 1968707Sandreas.hansson@arm.com 1971060SN/A class TickEvent : public Event 1981060SN/A { 1991060SN/A private: 2002292SN/A /** Pointer to the CPU. */ 2011755SN/A FullO3CPU<Impl> *cpu; 2021060SN/A 2031060SN/A public: 2042292SN/A /** Constructs a tick event. */ 2051755SN/A TickEvent(FullO3CPU<Impl> *c); 2062292SN/A 2072292SN/A /** Processes a tick event, calling tick() on the CPU. */ 2081060SN/A void process(); 2092292SN/A /** Returns the description of the tick event. */ 2105336Shines@cs.fsu.edu const char *description() const; 2111060SN/A }; 2121060SN/A 2132292SN/A /** The tick event used for scheduling CPU ticks. */ 2141060SN/A TickEvent tickEvent; 2151060SN/A 2162292SN/A /** Schedule tick event, regardless of its current state. */ 2171060SN/A void scheduleTickEvent(int delay) 2181060SN/A { 2191060SN/A if (tickEvent.squashed()) 2207823Ssteve.reinhardt@amd.com reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2211060SN/A else if (!tickEvent.scheduled()) 2227823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2231060SN/A } 2241060SN/A 2252292SN/A /** Unschedule tick event, regardless of its current state. */ 2261060SN/A void unscheduleTickEvent() 2271060SN/A { 2281060SN/A if (tickEvent.scheduled()) 2291060SN/A tickEvent.squash(); 2301060SN/A } 2311060SN/A 2322829Sksewell@umich.edu class ActivateThreadEvent : public Event 2332829Sksewell@umich.edu { 2342829Sksewell@umich.edu private: 2352829Sksewell@umich.edu /** Number of Thread to Activate */ 2366221Snate@binkert.org ThreadID tid; 2372829Sksewell@umich.edu 2382829Sksewell@umich.edu /** Pointer to the CPU. */ 2392829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2402829Sksewell@umich.edu 2412829Sksewell@umich.edu public: 2422829Sksewell@umich.edu /** Constructs the event. */ 2432829Sksewell@umich.edu ActivateThreadEvent(); 2442829Sksewell@umich.edu 2452829Sksewell@umich.edu /** Initialize Event */ 2462829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2472829Sksewell@umich.edu 2482829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2492829Sksewell@umich.edu void process(); 2502829Sksewell@umich.edu 2512829Sksewell@umich.edu /** Returns the description of the event. */ 2525336Shines@cs.fsu.edu const char *description() const; 2532829Sksewell@umich.edu }; 2542829Sksewell@umich.edu 2552829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 2566221Snate@binkert.org void 2576221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 2582829Sksewell@umich.edu { 2592829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2602829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 2615606Snate@binkert.org reschedule(activateThreadEvent[tid], 2627823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2638518Sgeoffrey.blake@arm.com else if (!activateThreadEvent[tid].scheduled()) { 2648518Sgeoffrey.blake@arm.com Tick when = nextCycle(curTick() + ticks(delay)); 2658518Sgeoffrey.blake@arm.com 2668518Sgeoffrey.blake@arm.com // Check if the deallocateEvent is also scheduled, and make 2678518Sgeoffrey.blake@arm.com // sure they do not happen at same time causing a sleep that 2688518Sgeoffrey.blake@arm.com // is never woken from. 2698518Sgeoffrey.blake@arm.com if (deallocateContextEvent[tid].scheduled() && 2708518Sgeoffrey.blake@arm.com deallocateContextEvent[tid].when() == when) { 2718518Sgeoffrey.blake@arm.com when++; 2728518Sgeoffrey.blake@arm.com } 2738518Sgeoffrey.blake@arm.com 2748518Sgeoffrey.blake@arm.com schedule(activateThreadEvent[tid], when); 2758518Sgeoffrey.blake@arm.com } 2762829Sksewell@umich.edu } 2772829Sksewell@umich.edu 2782829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 2796221Snate@binkert.org void 2806221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 2812829Sksewell@umich.edu { 2822829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2832829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2842829Sksewell@umich.edu } 2852829Sksewell@umich.edu 2862829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2872829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2882829Sksewell@umich.edu 2892875Sksewell@umich.edu class DeallocateContextEvent : public Event 2902875Sksewell@umich.edu { 2912875Sksewell@umich.edu private: 2923221Sktlim@umich.edu /** Number of Thread to deactivate */ 2936221Snate@binkert.org ThreadID tid; 2942875Sksewell@umich.edu 2953221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2963221Sktlim@umich.edu bool remove; 2973221Sktlim@umich.edu 2982875Sksewell@umich.edu /** Pointer to the CPU. */ 2992875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 3002875Sksewell@umich.edu 3012875Sksewell@umich.edu public: 3022875Sksewell@umich.edu /** Constructs the event. */ 3032875Sksewell@umich.edu DeallocateContextEvent(); 3042875Sksewell@umich.edu 3052875Sksewell@umich.edu /** Initialize Event */ 3062875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 3072875Sksewell@umich.edu 3082875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 3092875Sksewell@umich.edu void process(); 3102875Sksewell@umich.edu 3113221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 3123221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 3133221Sktlim@umich.edu 3142875Sksewell@umich.edu /** Returns the description of the event. */ 3155336Shines@cs.fsu.edu const char *description() const; 3162875Sksewell@umich.edu }; 3172875Sksewell@umich.edu 3182875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 3196221Snate@binkert.org void 3206221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 3212875Sksewell@umich.edu { 3222875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 3232875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 3245606Snate@binkert.org reschedule(deallocateContextEvent[tid], 3257823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 3262875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 3275606Snate@binkert.org schedule(deallocateContextEvent[tid], 3287823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 3292875Sksewell@umich.edu } 3302875Sksewell@umich.edu 3312875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 3326221Snate@binkert.org void 3336221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 3342875Sksewell@umich.edu { 3352875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 3362875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 3372875Sksewell@umich.edu } 3382875Sksewell@umich.edu 3392875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 3402875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 3412875Sksewell@umich.edu 3421060SN/A public: 3432292SN/A /** Constructs a CPU with the given parameters. */ 3445595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 3452292SN/A /** Destructor. */ 3461755SN/A ~FullO3CPU(); 3471060SN/A 3482292SN/A /** Registers statistics. */ 3495595Sgblack@eecs.umich.edu void regStats(); 3501684SN/A 3515358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3525358Sgblack@eecs.umich.edu { 3535358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3545358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3555358Sgblack@eecs.umich.edu } 3565358Sgblack@eecs.umich.edu 3575358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3585358Sgblack@eecs.umich.edu { 3595358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3605358Sgblack@eecs.umich.edu } 3615358Sgblack@eecs.umich.edu 3625358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3635358Sgblack@eecs.umich.edu { 3645358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3655358Sgblack@eecs.umich.edu } 3665358Sgblack@eecs.umich.edu 3672871Sktlim@umich.edu /** Returns a specific port. */ 3682871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 3692871Sktlim@umich.edu 3702292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3712292SN/A * activity to see if the CPU should deschedule itself. 3722292SN/A */ 3731684SN/A void tick(); 3741684SN/A 3752292SN/A /** Initialize the CPU */ 3761060SN/A void init(); 3771060SN/A 3782834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3792834Sksewell@umich.edu int numActiveThreads() 3802834Sksewell@umich.edu { return activeThreads.size(); } 3812834Sksewell@umich.edu 3822829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3836221Snate@binkert.org void activateThread(ThreadID tid); 3842875Sksewell@umich.edu 3852875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3866221Snate@binkert.org void deactivateThread(ThreadID tid); 3872829Sksewell@umich.edu 3882292SN/A /** Setup CPU to insert a thread's context */ 3896221Snate@binkert.org void insertThread(ThreadID tid); 3901060SN/A 3912292SN/A /** Remove all of a thread's context from CPU */ 3926221Snate@binkert.org void removeThread(ThreadID tid); 3932292SN/A 3942292SN/A /** Count the Total Instructions Committed in the CPU. */ 3956221Snate@binkert.org virtual Counter totalInstructions() const; 3962292SN/A 3972292SN/A /** Add Thread to Active Threads List. */ 3986221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3992292SN/A 4002292SN/A /** Remove Thread from Active Threads List */ 4016221Snate@binkert.org void suspendContext(ThreadID tid); 4022292SN/A 4032292SN/A /** Remove Thread from Active Threads List && 4043221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 4052292SN/A */ 4066221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 4072292SN/A 4082292SN/A /** Remove Thread from Active Threads List && 4092292SN/A * Remove Thread Context from CPU. 4102292SN/A */ 4116221Snate@binkert.org void haltContext(ThreadID tid); 4122292SN/A 4132292SN/A /** Activate a Thread When CPU Resources are Available. */ 4146221Snate@binkert.org void activateWhenReady(ThreadID tid); 4152292SN/A 4162292SN/A /** Add or Remove a Thread Context in the CPU. */ 4172292SN/A void doContextSwitch(); 4182292SN/A 4192292SN/A /** Update The Order In Which We Process Threads. */ 4202292SN/A void updateThreadPriority(); 4212292SN/A 4222864Sktlim@umich.edu /** Serialize state. */ 4232864Sktlim@umich.edu virtual void serialize(std::ostream &os); 4242864Sktlim@umich.edu 4252864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 4262864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 4272864Sktlim@umich.edu 4282864Sktlim@umich.edu public: 4295595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4305595Sgblack@eecs.umich.edu /** Executes a syscall. 4315595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 4322292SN/A */ 4336221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 4345595Sgblack@eecs.umich.edu#endif 4352292SN/A 4362843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 4372843Sktlim@umich.edu * order to stop all memory accesses. */ 4382905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 4392843Sktlim@umich.edu 4402843Sktlim@umich.edu /** Resumes execution after a drain. */ 4412843Sktlim@umich.edu virtual void resume(); 4422292SN/A 4432348SN/A /** Signals to this CPU that a stage has completed switching out. */ 4442843Sktlim@umich.edu void signalDrained(); 4452843Sktlim@umich.edu 4462843Sktlim@umich.edu /** Switches out this CPU. */ 4472843Sktlim@umich.edu virtual void switchOut(); 4482316SN/A 4492348SN/A /** Takes over from another CPU. */ 4502843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 4511060SN/A 4521060SN/A /** Get the current instruction sequence number, and increment it. */ 4532316SN/A InstSeqNum getAndIncrementInstSeq() 4542316SN/A { return globalSeqNum++; } 4551060SN/A 4565595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 4577684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 4585595Sgblack@eecs.umich.edu 4591858SN/A#if FULL_SYSTEM 4605702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 4616221Snate@binkert.org Fault hwrei(ThreadID tid); 4625702Ssaidi@eecs.umich.edu 4636221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 4645702Ssaidi@eecs.umich.edu 4655595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 4665595Sgblack@eecs.umich.edu Fault getInterrupts(); 4675595Sgblack@eecs.umich.edu 4685595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 4695595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 4705595Sgblack@eecs.umich.edu 4715595Sgblack@eecs.umich.edu /** Halts the CPU. */ 4725595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 4735595Sgblack@eecs.umich.edu 4741060SN/A /** Check if this address is a valid instruction address. */ 4751060SN/A bool validInstAddr(Addr addr) { return true; } 4761060SN/A 4771060SN/A /** Check if this address is a valid data address. */ 4781060SN/A bool validDataAddr(Addr addr) { return true; } 4791060SN/A#endif 4801060SN/A 4812348SN/A /** Register accessors. Index refers to the physical register index. */ 4825595Sgblack@eecs.umich.edu 4835595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4846221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4855595Sgblack@eecs.umich.edu 4865595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4875595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4885595Sgblack@eecs.umich.edu */ 4896221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4905595Sgblack@eecs.umich.edu 4915595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4926221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4936221Snate@binkert.org ThreadID tid); 4945595Sgblack@eecs.umich.edu 4955595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4965595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4975595Sgblack@eecs.umich.edu */ 4985595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4996221Snate@binkert.org ThreadID tid); 5005595Sgblack@eecs.umich.edu 5011060SN/A uint64_t readIntReg(int reg_idx); 5021060SN/A 5033781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 5041060SN/A 5053781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 5062455SN/A 5071060SN/A void setIntReg(int reg_idx, uint64_t val); 5081060SN/A 5093781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 5101060SN/A 5113781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 5122455SN/A 5136221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 5141060SN/A 5156314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 5162292SN/A 5176221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 5182292SN/A 5192348SN/A /** Architectural register accessors. Looks up in the commit 5202348SN/A * rename table to obtain the true physical index of the 5212348SN/A * architected register first, then accesses that physical 5222348SN/A * register. 5232348SN/A */ 5246221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 5252292SN/A 5266314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 5272292SN/A 5286221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 5292292SN/A 5307720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 5317720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 5327720Sgblack@eecs.umich.edu 5337720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 5347720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 5357720Sgblack@eecs.umich.edu 5362348SN/A /** Reads the commit PC of a specific thread. */ 5377720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 5382292SN/A 5394636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5407720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 5414636Sgblack@eecs.umich.edu 5422348SN/A /** Reads the next PC of a specific thread. */ 5437720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 5442756Sksewell@umich.edu 5455595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5465595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5475595Sgblack@eecs.umich.edu * state through the TC. 5485595Sgblack@eecs.umich.edu */ 5496221Snate@binkert.org void squashFromTC(ThreadID tid); 5505595Sgblack@eecs.umich.edu 5511060SN/A /** Function to add instruction onto the head of the list of the 5521060SN/A * instructions. Used when new instructions are fetched. 5531060SN/A */ 5542292SN/A ListIt addInst(DynInstPtr &inst); 5551060SN/A 5561060SN/A /** Function to tell the CPU that an instruction has completed. */ 5576221Snate@binkert.org void instDone(ThreadID tid); 5581060SN/A 5592325SN/A /** Remove an instruction from the front end of the list. There's 5602325SN/A * no restriction on location of the instruction. 5611060SN/A */ 5621061SN/A void removeFrontInst(DynInstPtr &inst); 5631060SN/A 5642935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5652935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5666221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5671060SN/A 5681062SN/A /** Remove all instructions younger than the given sequence number. */ 5696221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5702292SN/A 5712348SN/A /** Removes the instruction pointed to by the iterator. */ 5726221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5732292SN/A 5742348SN/A /** Cleans up all instructions on the remove list. */ 5752292SN/A void cleanUpRemovedInsts(); 5761062SN/A 5772348SN/A /** Debug function to print all instructions on the list. */ 5781060SN/A void dumpInsts(); 5791060SN/A 5801060SN/A public: 5815737Scws3k@cs.virginia.edu#ifndef NDEBUG 5825737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5835737Scws3k@cs.virginia.edu int instcount; 5845737Scws3k@cs.virginia.edu#endif 5855737Scws3k@cs.virginia.edu 5861060SN/A /** List of all the instructions in flight. */ 5872292SN/A std::list<DynInstPtr> instList; 5881060SN/A 5892292SN/A /** List of all the instructions that will be removed at the end of this 5902292SN/A * cycle. 5912292SN/A */ 5922292SN/A std::queue<ListIt> removeList; 5932292SN/A 5942325SN/A#ifdef DEBUG 5952348SN/A /** Debug structure to keep track of the sequence numbers still in 5962348SN/A * flight. 5972348SN/A */ 5982292SN/A std::set<InstSeqNum> snList; 5992325SN/A#endif 6002292SN/A 6012325SN/A /** Records if instructions need to be removed this cycle due to 6022325SN/A * being retired or squashed. 6032292SN/A */ 6042292SN/A bool removeInstsThisCycle; 6052292SN/A 6061060SN/A protected: 6071060SN/A /** The fetch stage. */ 6081060SN/A typename CPUPolicy::Fetch fetch; 6091060SN/A 6101060SN/A /** The decode stage. */ 6111060SN/A typename CPUPolicy::Decode decode; 6121060SN/A 6131060SN/A /** The dispatch stage. */ 6141060SN/A typename CPUPolicy::Rename rename; 6151060SN/A 6161060SN/A /** The issue/execute/writeback stages. */ 6171060SN/A typename CPUPolicy::IEW iew; 6181060SN/A 6191060SN/A /** The commit stage. */ 6201060SN/A typename CPUPolicy::Commit commit; 6211060SN/A 6221060SN/A /** The register file. */ 6231060SN/A typename CPUPolicy::RegFile regFile; 6241060SN/A 6251060SN/A /** The free list. */ 6261060SN/A typename CPUPolicy::FreeList freeList; 6271060SN/A 6281060SN/A /** The rename map. */ 6292292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6302292SN/A 6312292SN/A /** The commit rename map. */ 6322292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6331060SN/A 6341060SN/A /** The re-order buffer. */ 6351060SN/A typename CPUPolicy::ROB rob; 6361060SN/A 6372292SN/A /** Active Threads List */ 6386221Snate@binkert.org std::list<ThreadID> activeThreads; 6392292SN/A 6402292SN/A /** Integer Register Scoreboard */ 6412292SN/A Scoreboard scoreboard; 6422292SN/A 6436313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 6446313Sgblack@eecs.umich.edu 6458707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 6468707Sandreas.hansson@arm.com IcachePort icachePort; 6478707Sandreas.hansson@arm.com 6488707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 6498707Sandreas.hansson@arm.com DcachePort dcachePort; 6508707Sandreas.hansson@arm.com 6511060SN/A public: 6522292SN/A /** Enum to give each stage a specific index, so when calling 6532292SN/A * activateStage() or deactivateStage(), they can specify which stage 6542292SN/A * is being activated/deactivated. 6552292SN/A */ 6562292SN/A enum StageIdx { 6572292SN/A FetchIdx, 6582292SN/A DecodeIdx, 6592292SN/A RenameIdx, 6602292SN/A IEWIdx, 6612292SN/A CommitIdx, 6622292SN/A NumStages }; 6632292SN/A 6641060SN/A /** Typedefs from the Impl to get the structs that each of the 6651060SN/A * time buffers should use. 6661060SN/A */ 6671061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6681060SN/A 6691061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6701060SN/A 6711061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6721060SN/A 6731061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6741060SN/A 6751061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6761060SN/A 6771060SN/A /** The main time buffer to do backwards communication. */ 6781060SN/A TimeBuffer<TimeStruct> timeBuffer; 6791060SN/A 6801060SN/A /** The fetch stage's instruction queue. */ 6811060SN/A TimeBuffer<FetchStruct> fetchQueue; 6821060SN/A 6831060SN/A /** The decode stage's instruction queue. */ 6841060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6851060SN/A 6861060SN/A /** The rename stage's instruction queue. */ 6871060SN/A TimeBuffer<RenameStruct> renameQueue; 6881060SN/A 6891060SN/A /** The IEW stage's instruction queue. */ 6901060SN/A TimeBuffer<IEWStruct> iewQueue; 6911060SN/A 6922348SN/A private: 6932348SN/A /** The activity recorder; used to tell if the CPU has any 6942348SN/A * activity remaining or if it can go to idle and deschedule 6952348SN/A * itself. 6962348SN/A */ 6972325SN/A ActivityRecorder activityRec; 6981060SN/A 6992348SN/A public: 7002348SN/A /** Records that there was time buffer activity this cycle. */ 7012325SN/A void activityThisCycle() { activityRec.activity(); } 7022292SN/A 7032348SN/A /** Changes a stage's status to active within the activity recorder. */ 7042325SN/A void activateStage(const StageIdx idx) 7052325SN/A { activityRec.activateStage(idx); } 7062292SN/A 7072348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 7082325SN/A void deactivateStage(const StageIdx idx) 7092325SN/A { activityRec.deactivateStage(idx); } 7102292SN/A 7112292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7122292SN/A void wakeCPU(); 7132260SN/A 7145807Snate@binkert.org#if FULL_SYSTEM 7155807Snate@binkert.org virtual void wakeup(); 7165807Snate@binkert.org#endif 7175807Snate@binkert.org 7182292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7196221Snate@binkert.org ThreadID getFreeTid(); 7202292SN/A 7212292SN/A public: 7222680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7236221Snate@binkert.org ThreadContext * 7246221Snate@binkert.org tcBase(ThreadID tid) 7251681SN/A { 7262680Sktlim@umich.edu return thread[tid]->getTC(); 7272190SN/A } 7282190SN/A 7292292SN/A /** The global sequence number counter. */ 7303093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7311060SN/A 7324598Sbinkertn@umich.edu#if USE_CHECKER 7332348SN/A /** Pointer to the checker, which can dynamically verify 7342348SN/A * instruction results at run time. This can be set to NULL if it 7352348SN/A * is not being used. 7362348SN/A */ 7372316SN/A Checker<DynInstPtr> *checker; 7384598Sbinkertn@umich.edu#endif 7392316SN/A 7402292SN/A /** Pointer to the system. */ 7411060SN/A System *system; 7421060SN/A 7432843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 7442843Sktlim@umich.edu Event *drainEvent; 7452843Sktlim@umich.edu 7462843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 7472843Sktlim@umich.edu int drainCount; 7482316SN/A 7492348SN/A /** Pointers to all of the threads in the CPU. */ 7502292SN/A std::vector<Thread *> thread; 7512260SN/A 7522292SN/A /** Whether or not the CPU should defer its registration. */ 7531060SN/A bool deferRegistration; 7541060SN/A 7552292SN/A /** Is there a context switch pending? */ 7562292SN/A bool contextSwitch; 7571060SN/A 7582292SN/A /** Threads Scheduled to Enter CPU */ 7592292SN/A std::list<int> cpuWaitList; 7602292SN/A 7612292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7622292SN/A Tick lastRunningCycle; 7632292SN/A 7642829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7652829Sksewell@umich.edu Tick lastActivatedCycle; 7662829Sksewell@umich.edu 7672292SN/A /** Mapping for system thread id to cpu id */ 7686221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7692292SN/A 7702292SN/A /** Available thread ids in the cpu*/ 7716221Snate@binkert.org std::vector<ThreadID> tids; 7722292SN/A 7735595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7746974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7757520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 7765595Sgblack@eecs.umich.edu { 7776974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 7786974Stjones1@inf.ed.ac.uk data, load_idx); 7795595Sgblack@eecs.umich.edu } 7805595Sgblack@eecs.umich.edu 7815595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7826974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7837520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7845595Sgblack@eecs.umich.edu { 7856974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7866974Stjones1@inf.ed.ac.uk data, store_idx); 7875595Sgblack@eecs.umich.edu } 7885595Sgblack@eecs.umich.edu 7898707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 7908707Sandreas.hansson@arm.com Port* getIcachePort() { return &icachePort; } 7918707Sandreas.hansson@arm.com 7926974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7938707Sandreas.hansson@arm.com Port* getDcachePort() { return &dcachePort; } 7946974Stjones1@inf.ed.ac.uk 7955595Sgblack@eecs.umich.edu Addr lockAddr; 7965595Sgblack@eecs.umich.edu 7975595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7985595Sgblack@eecs.umich.edu bool lockFlag; 7995595Sgblack@eecs.umich.edu 8002292SN/A /** Stat for total number of times the CPU is descheduled. */ 8015999Snate@binkert.org Stats::Scalar timesIdled; 8022292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 8035999Snate@binkert.org Stats::Scalar idleCycles; 8048627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 8058627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 8068627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 8072292SN/A /** Stat for the number of committed instructions per thread. */ 8085999Snate@binkert.org Stats::Vector committedInsts; 8092292SN/A /** Stat for the total number of committed instructions. */ 8105999Snate@binkert.org Stats::Scalar totalCommittedInsts; 8112292SN/A /** Stat for the CPI per thread. */ 8122292SN/A Stats::Formula cpi; 8132292SN/A /** Stat for the total CPI. */ 8142292SN/A Stats::Formula totalCpi; 8152292SN/A /** Stat for the IPC per thread. */ 8162292SN/A Stats::Formula ipc; 8172292SN/A /** Stat for the total IPC. */ 8182292SN/A Stats::Formula totalIpc; 8197897Shestness@cs.utexas.edu 8207897Shestness@cs.utexas.edu //number of integer register file accesses 8217897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 8227897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 8237897Shestness@cs.utexas.edu //number of float register file accesses 8247897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 8257897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 8267897Shestness@cs.utexas.edu //number of misc 8277897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 8287897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 8291060SN/A}; 8301060SN/A 8312325SN/A#endif // __CPU_O3_CPU_HH__ 832