cpu.hh revision 8627
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302756Sksewell@umich.edu * Korey Sewell 317897Shestness@cs.utexas.edu * Rick Strong 321689SN/A */ 331689SN/A 342325SN/A#ifndef __CPU_O3_CPU_HH__ 352325SN/A#define __CPU_O3_CPU_HH__ 361060SN/A 371060SN/A#include <iostream> 381060SN/A#include <list> 392292SN/A#include <queue> 402292SN/A#include <set> 411681SN/A#include <vector> 421060SN/A 432980Sgblack@eecs.umich.edu#include "arch/types.hh" 441060SN/A#include "base/statistics.hh" 451858SN/A#include "config/full_system.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 474598Sbinkertn@umich.edu#include "config/use_checker.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 528229Snate@binkert.org#include "cpu/activity.hh" 538229Snate@binkert.org#include "cpu/base.hh" 548229Snate@binkert.org#include "cpu/simple_thread.hh" 558229Snate@binkert.org#include "cpu/timebuf.hh" 562817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 578229Snate@binkert.org#include "params/DerivO3CPU.hh" 581060SN/A#include "sim/process.hh" 591060SN/A 602316SN/Atemplate <class> 612316SN/Aclass Checker; 622680Sktlim@umich.educlass ThreadContext; 632817Sksewell@umich.edutemplate <class> 642817Sksewell@umich.educlass O3ThreadContext; 652843Sktlim@umich.edu 662843Sktlim@umich.educlass Checkpoint; 672669Sktlim@umich.educlass MemObject; 681060SN/Aclass Process; 691060SN/A 705529Snate@binkert.orgclass BaseCPUParams; 715529Snate@binkert.org 722733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 731060SN/A{ 741060SN/A //Stuff that's pretty ISA independent will go here. 751060SN/A public: 765529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 772292SN/A 782292SN/A void regStats(); 791060SN/A}; 801060SN/A 812348SN/A/** 822348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 832348SN/A * within it, as well as all of the time buffers between stages. The 842348SN/A * tick() function for the CPU is defined here. 852348SN/A */ 861060SN/Atemplate <class Impl> 872733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 881060SN/A{ 891060SN/A public: 902325SN/A // Typedefs from the Impl here. 911060SN/A typedef typename Impl::CPUPol CPUPolicy; 921061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 934329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 941060SN/A 955595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 962292SN/A typedef O3ThreadState<Impl> Thread; 972292SN/A 982292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 992292SN/A 1002817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1012829Sksewell@umich.edu 1021060SN/A public: 1031060SN/A enum Status { 1041060SN/A Running, 1051060SN/A Idle, 1061060SN/A Halted, 1072307SN/A Blocked, 1082307SN/A SwitchedOut 1091060SN/A }; 1101060SN/A 1116022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1126022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1133781Sgblack@eecs.umich.edu 1142292SN/A /** Overall CPU status. */ 1151060SN/A Status _status; 1161060SN/A 1172829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1182829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1192829Sksewell@umich.edu 1201060SN/A private: 1211060SN/A class TickEvent : public Event 1221060SN/A { 1231060SN/A private: 1242292SN/A /** Pointer to the CPU. */ 1251755SN/A FullO3CPU<Impl> *cpu; 1261060SN/A 1271060SN/A public: 1282292SN/A /** Constructs a tick event. */ 1291755SN/A TickEvent(FullO3CPU<Impl> *c); 1302292SN/A 1312292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1321060SN/A void process(); 1332292SN/A /** Returns the description of the tick event. */ 1345336Shines@cs.fsu.edu const char *description() const; 1351060SN/A }; 1361060SN/A 1372292SN/A /** The tick event used for scheduling CPU ticks. */ 1381060SN/A TickEvent tickEvent; 1391060SN/A 1402292SN/A /** Schedule tick event, regardless of its current state. */ 1411060SN/A void scheduleTickEvent(int delay) 1421060SN/A { 1431060SN/A if (tickEvent.squashed()) 1447823Ssteve.reinhardt@amd.com reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 1451060SN/A else if (!tickEvent.scheduled()) 1467823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 1471060SN/A } 1481060SN/A 1492292SN/A /** Unschedule tick event, regardless of its current state. */ 1501060SN/A void unscheduleTickEvent() 1511060SN/A { 1521060SN/A if (tickEvent.scheduled()) 1531060SN/A tickEvent.squash(); 1541060SN/A } 1551060SN/A 1562829Sksewell@umich.edu class ActivateThreadEvent : public Event 1572829Sksewell@umich.edu { 1582829Sksewell@umich.edu private: 1592829Sksewell@umich.edu /** Number of Thread to Activate */ 1606221Snate@binkert.org ThreadID tid; 1612829Sksewell@umich.edu 1622829Sksewell@umich.edu /** Pointer to the CPU. */ 1632829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1642829Sksewell@umich.edu 1652829Sksewell@umich.edu public: 1662829Sksewell@umich.edu /** Constructs the event. */ 1672829Sksewell@umich.edu ActivateThreadEvent(); 1682829Sksewell@umich.edu 1692829Sksewell@umich.edu /** Initialize Event */ 1702829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1712829Sksewell@umich.edu 1722829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1732829Sksewell@umich.edu void process(); 1742829Sksewell@umich.edu 1752829Sksewell@umich.edu /** Returns the description of the event. */ 1765336Shines@cs.fsu.edu const char *description() const; 1772829Sksewell@umich.edu }; 1782829Sksewell@umich.edu 1792829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1806221Snate@binkert.org void 1816221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 1822829Sksewell@umich.edu { 1832829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1842829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1855606Snate@binkert.org reschedule(activateThreadEvent[tid], 1867823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 1878518Sgeoffrey.blake@arm.com else if (!activateThreadEvent[tid].scheduled()) { 1888518Sgeoffrey.blake@arm.com Tick when = nextCycle(curTick() + ticks(delay)); 1898518Sgeoffrey.blake@arm.com 1908518Sgeoffrey.blake@arm.com // Check if the deallocateEvent is also scheduled, and make 1918518Sgeoffrey.blake@arm.com // sure they do not happen at same time causing a sleep that 1928518Sgeoffrey.blake@arm.com // is never woken from. 1938518Sgeoffrey.blake@arm.com if (deallocateContextEvent[tid].scheduled() && 1948518Sgeoffrey.blake@arm.com deallocateContextEvent[tid].when() == when) { 1958518Sgeoffrey.blake@arm.com when++; 1968518Sgeoffrey.blake@arm.com } 1978518Sgeoffrey.blake@arm.com 1988518Sgeoffrey.blake@arm.com schedule(activateThreadEvent[tid], when); 1998518Sgeoffrey.blake@arm.com } 2002829Sksewell@umich.edu } 2012829Sksewell@umich.edu 2022829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 2036221Snate@binkert.org void 2046221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 2052829Sksewell@umich.edu { 2062829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2072829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2082829Sksewell@umich.edu } 2092829Sksewell@umich.edu 2102829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2112829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2122829Sksewell@umich.edu 2132875Sksewell@umich.edu class DeallocateContextEvent : public Event 2142875Sksewell@umich.edu { 2152875Sksewell@umich.edu private: 2163221Sktlim@umich.edu /** Number of Thread to deactivate */ 2176221Snate@binkert.org ThreadID tid; 2182875Sksewell@umich.edu 2193221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2203221Sktlim@umich.edu bool remove; 2213221Sktlim@umich.edu 2222875Sksewell@umich.edu /** Pointer to the CPU. */ 2232875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2242875Sksewell@umich.edu 2252875Sksewell@umich.edu public: 2262875Sksewell@umich.edu /** Constructs the event. */ 2272875Sksewell@umich.edu DeallocateContextEvent(); 2282875Sksewell@umich.edu 2292875Sksewell@umich.edu /** Initialize Event */ 2302875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2312875Sksewell@umich.edu 2322875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2332875Sksewell@umich.edu void process(); 2342875Sksewell@umich.edu 2353221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2363221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2373221Sktlim@umich.edu 2382875Sksewell@umich.edu /** Returns the description of the event. */ 2395336Shines@cs.fsu.edu const char *description() const; 2402875Sksewell@umich.edu }; 2412875Sksewell@umich.edu 2422875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2436221Snate@binkert.org void 2446221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 2452875Sksewell@umich.edu { 2462875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2472875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2485606Snate@binkert.org reschedule(deallocateContextEvent[tid], 2497823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2502875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2515606Snate@binkert.org schedule(deallocateContextEvent[tid], 2527823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2532875Sksewell@umich.edu } 2542875Sksewell@umich.edu 2552875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2566221Snate@binkert.org void 2576221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 2582875Sksewell@umich.edu { 2592875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2602875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2612875Sksewell@umich.edu } 2622875Sksewell@umich.edu 2632875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2642875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2652875Sksewell@umich.edu 2661060SN/A public: 2672292SN/A /** Constructs a CPU with the given parameters. */ 2685595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2692292SN/A /** Destructor. */ 2701755SN/A ~FullO3CPU(); 2711060SN/A 2722292SN/A /** Registers statistics. */ 2735595Sgblack@eecs.umich.edu void regStats(); 2741684SN/A 2755358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2765358Sgblack@eecs.umich.edu { 2775358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2785358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2795358Sgblack@eecs.umich.edu } 2805358Sgblack@eecs.umich.edu 2815358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2825358Sgblack@eecs.umich.edu { 2835358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2845358Sgblack@eecs.umich.edu } 2855358Sgblack@eecs.umich.edu 2865358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2875358Sgblack@eecs.umich.edu { 2885358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2895358Sgblack@eecs.umich.edu } 2905358Sgblack@eecs.umich.edu 2912871Sktlim@umich.edu /** Returns a specific port. */ 2922871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2932871Sktlim@umich.edu 2942292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2952292SN/A * activity to see if the CPU should deschedule itself. 2962292SN/A */ 2971684SN/A void tick(); 2981684SN/A 2992292SN/A /** Initialize the CPU */ 3001060SN/A void init(); 3011060SN/A 3022834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3032834Sksewell@umich.edu int numActiveThreads() 3042834Sksewell@umich.edu { return activeThreads.size(); } 3052834Sksewell@umich.edu 3062829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3076221Snate@binkert.org void activateThread(ThreadID tid); 3082875Sksewell@umich.edu 3092875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3106221Snate@binkert.org void deactivateThread(ThreadID tid); 3112829Sksewell@umich.edu 3122292SN/A /** Setup CPU to insert a thread's context */ 3136221Snate@binkert.org void insertThread(ThreadID tid); 3141060SN/A 3152292SN/A /** Remove all of a thread's context from CPU */ 3166221Snate@binkert.org void removeThread(ThreadID tid); 3172292SN/A 3182292SN/A /** Count the Total Instructions Committed in the CPU. */ 3196221Snate@binkert.org virtual Counter totalInstructions() const; 3202292SN/A 3212292SN/A /** Add Thread to Active Threads List. */ 3226221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3232292SN/A 3242292SN/A /** Remove Thread from Active Threads List */ 3256221Snate@binkert.org void suspendContext(ThreadID tid); 3262292SN/A 3272292SN/A /** Remove Thread from Active Threads List && 3283221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3292292SN/A */ 3306221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 3312292SN/A 3322292SN/A /** Remove Thread from Active Threads List && 3332292SN/A * Remove Thread Context from CPU. 3342292SN/A */ 3356221Snate@binkert.org void haltContext(ThreadID tid); 3362292SN/A 3372292SN/A /** Activate a Thread When CPU Resources are Available. */ 3386221Snate@binkert.org void activateWhenReady(ThreadID tid); 3392292SN/A 3402292SN/A /** Add or Remove a Thread Context in the CPU. */ 3412292SN/A void doContextSwitch(); 3422292SN/A 3432292SN/A /** Update The Order In Which We Process Threads. */ 3442292SN/A void updateThreadPriority(); 3452292SN/A 3462864Sktlim@umich.edu /** Serialize state. */ 3472864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3482864Sktlim@umich.edu 3492864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3502864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3512864Sktlim@umich.edu 3522864Sktlim@umich.edu public: 3535595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3545595Sgblack@eecs.umich.edu /** Executes a syscall. 3555595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3562292SN/A */ 3576221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 3585595Sgblack@eecs.umich.edu#endif 3592292SN/A 3602843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3612843Sktlim@umich.edu * order to stop all memory accesses. */ 3622905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3632843Sktlim@umich.edu 3642843Sktlim@umich.edu /** Resumes execution after a drain. */ 3652843Sktlim@umich.edu virtual void resume(); 3662292SN/A 3672348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3682843Sktlim@umich.edu void signalDrained(); 3692843Sktlim@umich.edu 3702843Sktlim@umich.edu /** Switches out this CPU. */ 3712843Sktlim@umich.edu virtual void switchOut(); 3722316SN/A 3732348SN/A /** Takes over from another CPU. */ 3742843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3751060SN/A 3761060SN/A /** Get the current instruction sequence number, and increment it. */ 3772316SN/A InstSeqNum getAndIncrementInstSeq() 3782316SN/A { return globalSeqNum++; } 3791060SN/A 3805595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3817684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 3825595Sgblack@eecs.umich.edu 3831858SN/A#if FULL_SYSTEM 3845702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3856221Snate@binkert.org Fault hwrei(ThreadID tid); 3865702Ssaidi@eecs.umich.edu 3876221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3885702Ssaidi@eecs.umich.edu 3895595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3905595Sgblack@eecs.umich.edu Fault getInterrupts(); 3915595Sgblack@eecs.umich.edu 3925595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 3935595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3965595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3975595Sgblack@eecs.umich.edu 3984192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3994192Sktlim@umich.edu * reflect change in memory connections. */ 4004192Sktlim@umich.edu void updateMemPorts(); 4014192Sktlim@umich.edu 4021060SN/A /** Check if this address is a valid instruction address. */ 4031060SN/A bool validInstAddr(Addr addr) { return true; } 4041060SN/A 4051060SN/A /** Check if this address is a valid data address. */ 4061060SN/A bool validDataAddr(Addr addr) { return true; } 4071060SN/A#endif 4081060SN/A 4092348SN/A /** Register accessors. Index refers to the physical register index. */ 4105595Sgblack@eecs.umich.edu 4115595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4126221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4135595Sgblack@eecs.umich.edu 4145595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4155595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4165595Sgblack@eecs.umich.edu */ 4176221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4185595Sgblack@eecs.umich.edu 4195595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4206221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4216221Snate@binkert.org ThreadID tid); 4225595Sgblack@eecs.umich.edu 4235595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4245595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4255595Sgblack@eecs.umich.edu */ 4265595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4276221Snate@binkert.org ThreadID tid); 4285595Sgblack@eecs.umich.edu 4291060SN/A uint64_t readIntReg(int reg_idx); 4301060SN/A 4313781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4321060SN/A 4333781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4342455SN/A 4351060SN/A void setIntReg(int reg_idx, uint64_t val); 4361060SN/A 4373781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4381060SN/A 4393781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4402455SN/A 4416221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4421060SN/A 4436314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4442292SN/A 4456221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4462292SN/A 4472348SN/A /** Architectural register accessors. Looks up in the commit 4482348SN/A * rename table to obtain the true physical index of the 4492348SN/A * architected register first, then accesses that physical 4502348SN/A * register. 4512348SN/A */ 4526221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4532292SN/A 4546314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4552292SN/A 4566221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4572292SN/A 4587720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 4597720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4607720Sgblack@eecs.umich.edu 4617720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 4627720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 4637720Sgblack@eecs.umich.edu 4642348SN/A /** Reads the commit PC of a specific thread. */ 4657720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 4662292SN/A 4674636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4687720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4694636Sgblack@eecs.umich.edu 4702348SN/A /** Reads the next PC of a specific thread. */ 4717720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4722756Sksewell@umich.edu 4735595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4745595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4755595Sgblack@eecs.umich.edu * state through the TC. 4765595Sgblack@eecs.umich.edu */ 4776221Snate@binkert.org void squashFromTC(ThreadID tid); 4785595Sgblack@eecs.umich.edu 4791060SN/A /** Function to add instruction onto the head of the list of the 4801060SN/A * instructions. Used when new instructions are fetched. 4811060SN/A */ 4822292SN/A ListIt addInst(DynInstPtr &inst); 4831060SN/A 4841060SN/A /** Function to tell the CPU that an instruction has completed. */ 4856221Snate@binkert.org void instDone(ThreadID tid); 4861060SN/A 4872325SN/A /** Remove an instruction from the front end of the list. There's 4882325SN/A * no restriction on location of the instruction. 4891060SN/A */ 4901061SN/A void removeFrontInst(DynInstPtr &inst); 4911060SN/A 4922935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4932935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4946221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 4951060SN/A 4961062SN/A /** Remove all instructions younger than the given sequence number. */ 4976221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 4982292SN/A 4992348SN/A /** Removes the instruction pointed to by the iterator. */ 5006221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5012292SN/A 5022348SN/A /** Cleans up all instructions on the remove list. */ 5032292SN/A void cleanUpRemovedInsts(); 5041062SN/A 5052348SN/A /** Debug function to print all instructions on the list. */ 5061060SN/A void dumpInsts(); 5071060SN/A 5081060SN/A public: 5095737Scws3k@cs.virginia.edu#ifndef NDEBUG 5105737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5115737Scws3k@cs.virginia.edu int instcount; 5125737Scws3k@cs.virginia.edu#endif 5135737Scws3k@cs.virginia.edu 5141060SN/A /** List of all the instructions in flight. */ 5152292SN/A std::list<DynInstPtr> instList; 5161060SN/A 5172292SN/A /** List of all the instructions that will be removed at the end of this 5182292SN/A * cycle. 5192292SN/A */ 5202292SN/A std::queue<ListIt> removeList; 5212292SN/A 5222325SN/A#ifdef DEBUG 5232348SN/A /** Debug structure to keep track of the sequence numbers still in 5242348SN/A * flight. 5252348SN/A */ 5262292SN/A std::set<InstSeqNum> snList; 5272325SN/A#endif 5282292SN/A 5292325SN/A /** Records if instructions need to be removed this cycle due to 5302325SN/A * being retired or squashed. 5312292SN/A */ 5322292SN/A bool removeInstsThisCycle; 5332292SN/A 5341060SN/A protected: 5351060SN/A /** The fetch stage. */ 5361060SN/A typename CPUPolicy::Fetch fetch; 5371060SN/A 5381060SN/A /** The decode stage. */ 5391060SN/A typename CPUPolicy::Decode decode; 5401060SN/A 5411060SN/A /** The dispatch stage. */ 5421060SN/A typename CPUPolicy::Rename rename; 5431060SN/A 5441060SN/A /** The issue/execute/writeback stages. */ 5451060SN/A typename CPUPolicy::IEW iew; 5461060SN/A 5471060SN/A /** The commit stage. */ 5481060SN/A typename CPUPolicy::Commit commit; 5491060SN/A 5501060SN/A /** The register file. */ 5511060SN/A typename CPUPolicy::RegFile regFile; 5521060SN/A 5531060SN/A /** The free list. */ 5541060SN/A typename CPUPolicy::FreeList freeList; 5551060SN/A 5561060SN/A /** The rename map. */ 5572292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5582292SN/A 5592292SN/A /** The commit rename map. */ 5602292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5611060SN/A 5621060SN/A /** The re-order buffer. */ 5631060SN/A typename CPUPolicy::ROB rob; 5641060SN/A 5652292SN/A /** Active Threads List */ 5666221Snate@binkert.org std::list<ThreadID> activeThreads; 5672292SN/A 5682292SN/A /** Integer Register Scoreboard */ 5692292SN/A Scoreboard scoreboard; 5702292SN/A 5716313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 5726313Sgblack@eecs.umich.edu 5731060SN/A public: 5742292SN/A /** Enum to give each stage a specific index, so when calling 5752292SN/A * activateStage() or deactivateStage(), they can specify which stage 5762292SN/A * is being activated/deactivated. 5772292SN/A */ 5782292SN/A enum StageIdx { 5792292SN/A FetchIdx, 5802292SN/A DecodeIdx, 5812292SN/A RenameIdx, 5822292SN/A IEWIdx, 5832292SN/A CommitIdx, 5842292SN/A NumStages }; 5852292SN/A 5861060SN/A /** Typedefs from the Impl to get the structs that each of the 5871060SN/A * time buffers should use. 5881060SN/A */ 5891061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5901060SN/A 5911061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5921060SN/A 5931061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5941060SN/A 5951061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5961060SN/A 5971061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5981060SN/A 5991060SN/A /** The main time buffer to do backwards communication. */ 6001060SN/A TimeBuffer<TimeStruct> timeBuffer; 6011060SN/A 6021060SN/A /** The fetch stage's instruction queue. */ 6031060SN/A TimeBuffer<FetchStruct> fetchQueue; 6041060SN/A 6051060SN/A /** The decode stage's instruction queue. */ 6061060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6071060SN/A 6081060SN/A /** The rename stage's instruction queue. */ 6091060SN/A TimeBuffer<RenameStruct> renameQueue; 6101060SN/A 6111060SN/A /** The IEW stage's instruction queue. */ 6121060SN/A TimeBuffer<IEWStruct> iewQueue; 6131060SN/A 6142348SN/A private: 6152348SN/A /** The activity recorder; used to tell if the CPU has any 6162348SN/A * activity remaining or if it can go to idle and deschedule 6172348SN/A * itself. 6182348SN/A */ 6192325SN/A ActivityRecorder activityRec; 6201060SN/A 6212348SN/A public: 6222348SN/A /** Records that there was time buffer activity this cycle. */ 6232325SN/A void activityThisCycle() { activityRec.activity(); } 6242292SN/A 6252348SN/A /** Changes a stage's status to active within the activity recorder. */ 6262325SN/A void activateStage(const StageIdx idx) 6272325SN/A { activityRec.activateStage(idx); } 6282292SN/A 6292348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6302325SN/A void deactivateStage(const StageIdx idx) 6312325SN/A { activityRec.deactivateStage(idx); } 6322292SN/A 6332292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6342292SN/A void wakeCPU(); 6352260SN/A 6365807Snate@binkert.org#if FULL_SYSTEM 6375807Snate@binkert.org virtual void wakeup(); 6385807Snate@binkert.org#endif 6395807Snate@binkert.org 6402292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6416221Snate@binkert.org ThreadID getFreeTid(); 6422292SN/A 6432292SN/A public: 6442680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6456221Snate@binkert.org ThreadContext * 6466221Snate@binkert.org tcBase(ThreadID tid) 6471681SN/A { 6482680Sktlim@umich.edu return thread[tid]->getTC(); 6492190SN/A } 6502190SN/A 6512292SN/A /** The global sequence number counter. */ 6523093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6531060SN/A 6544598Sbinkertn@umich.edu#if USE_CHECKER 6552348SN/A /** Pointer to the checker, which can dynamically verify 6562348SN/A * instruction results at run time. This can be set to NULL if it 6572348SN/A * is not being used. 6582348SN/A */ 6592316SN/A Checker<DynInstPtr> *checker; 6604598Sbinkertn@umich.edu#endif 6612316SN/A 6622292SN/A /** Pointer to the system. */ 6631060SN/A System *system; 6641060SN/A 6652843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6662843Sktlim@umich.edu Event *drainEvent; 6672843Sktlim@umich.edu 6682843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6692843Sktlim@umich.edu int drainCount; 6702316SN/A 6712348SN/A /** Pointers to all of the threads in the CPU. */ 6722292SN/A std::vector<Thread *> thread; 6732260SN/A 6742292SN/A /** Whether or not the CPU should defer its registration. */ 6751060SN/A bool deferRegistration; 6761060SN/A 6772292SN/A /** Is there a context switch pending? */ 6782292SN/A bool contextSwitch; 6791060SN/A 6802292SN/A /** Threads Scheduled to Enter CPU */ 6812292SN/A std::list<int> cpuWaitList; 6822292SN/A 6832292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6842292SN/A Tick lastRunningCycle; 6852292SN/A 6862829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6872829Sksewell@umich.edu Tick lastActivatedCycle; 6882829Sksewell@umich.edu 6892292SN/A /** Mapping for system thread id to cpu id */ 6906221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 6912292SN/A 6922292SN/A /** Available thread ids in the cpu*/ 6936221Snate@binkert.org std::vector<ThreadID> tids; 6942292SN/A 6955595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 6966974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6977520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 6985595Sgblack@eecs.umich.edu { 6996974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 7006974Stjones1@inf.ed.ac.uk data, load_idx); 7015595Sgblack@eecs.umich.edu } 7025595Sgblack@eecs.umich.edu 7035595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7046974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7057520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7065595Sgblack@eecs.umich.edu { 7076974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7086974Stjones1@inf.ed.ac.uk data, store_idx); 7095595Sgblack@eecs.umich.edu } 7105595Sgblack@eecs.umich.edu 7116974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7126974Stjones1@inf.ed.ac.uk Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 7136974Stjones1@inf.ed.ac.uk 7145595Sgblack@eecs.umich.edu Addr lockAddr; 7155595Sgblack@eecs.umich.edu 7165595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7175595Sgblack@eecs.umich.edu bool lockFlag; 7185595Sgblack@eecs.umich.edu 7192292SN/A /** Stat for total number of times the CPU is descheduled. */ 7205999Snate@binkert.org Stats::Scalar timesIdled; 7212292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7225999Snate@binkert.org Stats::Scalar idleCycles; 7238627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 7248627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 7258627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 7262292SN/A /** Stat for the number of committed instructions per thread. */ 7275999Snate@binkert.org Stats::Vector committedInsts; 7282292SN/A /** Stat for the total number of committed instructions. */ 7295999Snate@binkert.org Stats::Scalar totalCommittedInsts; 7302292SN/A /** Stat for the CPI per thread. */ 7312292SN/A Stats::Formula cpi; 7322292SN/A /** Stat for the total CPI. */ 7332292SN/A Stats::Formula totalCpi; 7342292SN/A /** Stat for the IPC per thread. */ 7352292SN/A Stats::Formula ipc; 7362292SN/A /** Stat for the total IPC. */ 7372292SN/A Stats::Formula totalIpc; 7387897Shestness@cs.utexas.edu 7397897Shestness@cs.utexas.edu //number of integer register file accesses 7407897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 7417897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 7427897Shestness@cs.utexas.edu //number of float register file accesses 7437897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 7447897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 7457897Shestness@cs.utexas.edu //number of misc 7467897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 7477897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 7481060SN/A}; 7491060SN/A 7502325SN/A#endif // __CPU_O3_CPU_HH__ 751