cpu.hh revision 7897
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302756Sksewell@umich.edu * Korey Sewell 317897Shestness@cs.utexas.edu * Rick Strong 321689SN/A */ 331689SN/A 342325SN/A#ifndef __CPU_O3_CPU_HH__ 352325SN/A#define __CPU_O3_CPU_HH__ 361060SN/A 371060SN/A#include <iostream> 381060SN/A#include <list> 392292SN/A#include <queue> 402292SN/A#include <set> 411681SN/A#include <vector> 421060SN/A 432980Sgblack@eecs.umich.edu#include "arch/types.hh" 441060SN/A#include "base/statistics.hh" 457813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 461858SN/A#include "config/full_system.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 484598Sbinkertn@umich.edu#include "config/use_checker.hh" 492325SN/A#include "cpu/activity.hh" 501717SN/A#include "cpu/base.hh" 512683Sktlim@umich.edu#include "cpu/simple_thread.hh" 521717SN/A#include "cpu/o3/comm.hh" 531717SN/A#include "cpu/o3/cpu_policy.hh" 542292SN/A#include "cpu/o3/scoreboard.hh" 552292SN/A#include "cpu/o3/thread_state.hh" 562817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 571060SN/A#include "sim/process.hh" 581060SN/A 595529Snate@binkert.org#include "params/DerivO3CPU.hh" 605529Snate@binkert.org 612316SN/Atemplate <class> 622316SN/Aclass Checker; 632680Sktlim@umich.educlass ThreadContext; 642817Sksewell@umich.edutemplate <class> 652817Sksewell@umich.educlass O3ThreadContext; 662843Sktlim@umich.edu 672843Sktlim@umich.educlass Checkpoint; 682669Sktlim@umich.educlass MemObject; 691060SN/Aclass Process; 701060SN/A 715529Snate@binkert.orgclass BaseCPUParams; 725529Snate@binkert.org 732733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 741060SN/A{ 751060SN/A //Stuff that's pretty ISA independent will go here. 761060SN/A public: 775529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 782292SN/A 792292SN/A void regStats(); 801060SN/A}; 811060SN/A 822348SN/A/** 832348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 842348SN/A * within it, as well as all of the time buffers between stages. The 852348SN/A * tick() function for the CPU is defined here. 862348SN/A */ 871060SN/Atemplate <class Impl> 882733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 891060SN/A{ 901060SN/A public: 912325SN/A // Typedefs from the Impl here. 921060SN/A typedef typename Impl::CPUPol CPUPolicy; 931061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 944329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 951060SN/A 965595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 972292SN/A typedef O3ThreadState<Impl> Thread; 982292SN/A 992292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1002292SN/A 1012817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1022829Sksewell@umich.edu 1031060SN/A public: 1041060SN/A enum Status { 1051060SN/A Running, 1061060SN/A Idle, 1071060SN/A Halted, 1082307SN/A Blocked, 1092307SN/A SwitchedOut 1101060SN/A }; 1111060SN/A 1126022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1136022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1143781Sgblack@eecs.umich.edu 1152292SN/A /** Overall CPU status. */ 1161060SN/A Status _status; 1171060SN/A 1182829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1192829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1202829Sksewell@umich.edu 1211060SN/A private: 1221060SN/A class TickEvent : public Event 1231060SN/A { 1241060SN/A private: 1252292SN/A /** Pointer to the CPU. */ 1261755SN/A FullO3CPU<Impl> *cpu; 1271060SN/A 1281060SN/A public: 1292292SN/A /** Constructs a tick event. */ 1301755SN/A TickEvent(FullO3CPU<Impl> *c); 1312292SN/A 1322292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1331060SN/A void process(); 1342292SN/A /** Returns the description of the tick event. */ 1355336Shines@cs.fsu.edu const char *description() const; 1361060SN/A }; 1371060SN/A 1382292SN/A /** The tick event used for scheduling CPU ticks. */ 1391060SN/A TickEvent tickEvent; 1401060SN/A 1412292SN/A /** Schedule tick event, regardless of its current state. */ 1421060SN/A void scheduleTickEvent(int delay) 1431060SN/A { 1441060SN/A if (tickEvent.squashed()) 1457823Ssteve.reinhardt@amd.com reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 1461060SN/A else if (!tickEvent.scheduled()) 1477823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 1481060SN/A } 1491060SN/A 1502292SN/A /** Unschedule tick event, regardless of its current state. */ 1511060SN/A void unscheduleTickEvent() 1521060SN/A { 1531060SN/A if (tickEvent.scheduled()) 1541060SN/A tickEvent.squash(); 1551060SN/A } 1561060SN/A 1572829Sksewell@umich.edu class ActivateThreadEvent : public Event 1582829Sksewell@umich.edu { 1592829Sksewell@umich.edu private: 1602829Sksewell@umich.edu /** Number of Thread to Activate */ 1616221Snate@binkert.org ThreadID tid; 1622829Sksewell@umich.edu 1632829Sksewell@umich.edu /** Pointer to the CPU. */ 1642829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1652829Sksewell@umich.edu 1662829Sksewell@umich.edu public: 1672829Sksewell@umich.edu /** Constructs the event. */ 1682829Sksewell@umich.edu ActivateThreadEvent(); 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu /** Initialize Event */ 1712829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1722829Sksewell@umich.edu 1732829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1742829Sksewell@umich.edu void process(); 1752829Sksewell@umich.edu 1762829Sksewell@umich.edu /** Returns the description of the event. */ 1775336Shines@cs.fsu.edu const char *description() const; 1782829Sksewell@umich.edu }; 1792829Sksewell@umich.edu 1802829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1816221Snate@binkert.org void 1826221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 1832829Sksewell@umich.edu { 1842829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1852829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1865606Snate@binkert.org reschedule(activateThreadEvent[tid], 1877823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 1882829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1895606Snate@binkert.org schedule(activateThreadEvent[tid], 1907823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 1912829Sksewell@umich.edu } 1922829Sksewell@umich.edu 1932829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1946221Snate@binkert.org void 1956221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 1962829Sksewell@umich.edu { 1972829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1982829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1992829Sksewell@umich.edu } 2002829Sksewell@umich.edu 2012829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2022829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2032829Sksewell@umich.edu 2042875Sksewell@umich.edu class DeallocateContextEvent : public Event 2052875Sksewell@umich.edu { 2062875Sksewell@umich.edu private: 2073221Sktlim@umich.edu /** Number of Thread to deactivate */ 2086221Snate@binkert.org ThreadID tid; 2092875Sksewell@umich.edu 2103221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2113221Sktlim@umich.edu bool remove; 2123221Sktlim@umich.edu 2132875Sksewell@umich.edu /** Pointer to the CPU. */ 2142875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2152875Sksewell@umich.edu 2162875Sksewell@umich.edu public: 2172875Sksewell@umich.edu /** Constructs the event. */ 2182875Sksewell@umich.edu DeallocateContextEvent(); 2192875Sksewell@umich.edu 2202875Sksewell@umich.edu /** Initialize Event */ 2212875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2222875Sksewell@umich.edu 2232875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2242875Sksewell@umich.edu void process(); 2252875Sksewell@umich.edu 2263221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2273221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2283221Sktlim@umich.edu 2292875Sksewell@umich.edu /** Returns the description of the event. */ 2305336Shines@cs.fsu.edu const char *description() const; 2312875Sksewell@umich.edu }; 2322875Sksewell@umich.edu 2332875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2346221Snate@binkert.org void 2356221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 2362875Sksewell@umich.edu { 2372875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2382875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2395606Snate@binkert.org reschedule(deallocateContextEvent[tid], 2407823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2412875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2425606Snate@binkert.org schedule(deallocateContextEvent[tid], 2437823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2442875Sksewell@umich.edu } 2452875Sksewell@umich.edu 2462875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2476221Snate@binkert.org void 2486221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 2492875Sksewell@umich.edu { 2502875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2512875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2522875Sksewell@umich.edu } 2532875Sksewell@umich.edu 2542875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2552875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2562875Sksewell@umich.edu 2571060SN/A public: 2582292SN/A /** Constructs a CPU with the given parameters. */ 2595595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2602292SN/A /** Destructor. */ 2611755SN/A ~FullO3CPU(); 2621060SN/A 2632292SN/A /** Registers statistics. */ 2645595Sgblack@eecs.umich.edu void regStats(); 2651684SN/A 2665358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2675358Sgblack@eecs.umich.edu { 2685358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2695358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2705358Sgblack@eecs.umich.edu } 2715358Sgblack@eecs.umich.edu 2725358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2735358Sgblack@eecs.umich.edu { 2745358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2755358Sgblack@eecs.umich.edu } 2765358Sgblack@eecs.umich.edu 2775358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2785358Sgblack@eecs.umich.edu { 2795358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2805358Sgblack@eecs.umich.edu } 2815358Sgblack@eecs.umich.edu 2822871Sktlim@umich.edu /** Returns a specific port. */ 2832871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2842871Sktlim@umich.edu 2852292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2862292SN/A * activity to see if the CPU should deschedule itself. 2872292SN/A */ 2881684SN/A void tick(); 2891684SN/A 2902292SN/A /** Initialize the CPU */ 2911060SN/A void init(); 2921060SN/A 2932834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2942834Sksewell@umich.edu int numActiveThreads() 2952834Sksewell@umich.edu { return activeThreads.size(); } 2962834Sksewell@umich.edu 2972829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2986221Snate@binkert.org void activateThread(ThreadID tid); 2992875Sksewell@umich.edu 3002875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3016221Snate@binkert.org void deactivateThread(ThreadID tid); 3022829Sksewell@umich.edu 3032292SN/A /** Setup CPU to insert a thread's context */ 3046221Snate@binkert.org void insertThread(ThreadID tid); 3051060SN/A 3062292SN/A /** Remove all of a thread's context from CPU */ 3076221Snate@binkert.org void removeThread(ThreadID tid); 3082292SN/A 3092292SN/A /** Count the Total Instructions Committed in the CPU. */ 3106221Snate@binkert.org virtual Counter totalInstructions() const; 3112292SN/A 3122292SN/A /** Add Thread to Active Threads List. */ 3136221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3142292SN/A 3152292SN/A /** Remove Thread from Active Threads List */ 3166221Snate@binkert.org void suspendContext(ThreadID tid); 3172292SN/A 3182292SN/A /** Remove Thread from Active Threads List && 3193221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3202292SN/A */ 3216221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 3222292SN/A 3232292SN/A /** Remove Thread from Active Threads List && 3242292SN/A * Remove Thread Context from CPU. 3252292SN/A */ 3266221Snate@binkert.org void haltContext(ThreadID tid); 3272292SN/A 3282292SN/A /** Activate a Thread When CPU Resources are Available. */ 3296221Snate@binkert.org void activateWhenReady(ThreadID tid); 3302292SN/A 3312292SN/A /** Add or Remove a Thread Context in the CPU. */ 3322292SN/A void doContextSwitch(); 3332292SN/A 3342292SN/A /** Update The Order In Which We Process Threads. */ 3352292SN/A void updateThreadPriority(); 3362292SN/A 3372864Sktlim@umich.edu /** Serialize state. */ 3382864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3392864Sktlim@umich.edu 3402864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3412864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3422864Sktlim@umich.edu 3432864Sktlim@umich.edu public: 3445595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3455595Sgblack@eecs.umich.edu /** Executes a syscall. 3465595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3472292SN/A */ 3486221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 3495595Sgblack@eecs.umich.edu#endif 3502292SN/A 3512843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3522843Sktlim@umich.edu * order to stop all memory accesses. */ 3532905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3542843Sktlim@umich.edu 3552843Sktlim@umich.edu /** Resumes execution after a drain. */ 3562843Sktlim@umich.edu virtual void resume(); 3572292SN/A 3582348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3592843Sktlim@umich.edu void signalDrained(); 3602843Sktlim@umich.edu 3612843Sktlim@umich.edu /** Switches out this CPU. */ 3622843Sktlim@umich.edu virtual void switchOut(); 3632316SN/A 3642348SN/A /** Takes over from another CPU. */ 3652843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3661060SN/A 3671060SN/A /** Get the current instruction sequence number, and increment it. */ 3682316SN/A InstSeqNum getAndIncrementInstSeq() 3692316SN/A { return globalSeqNum++; } 3701060SN/A 3715595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3727684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 3735595Sgblack@eecs.umich.edu 3741858SN/A#if FULL_SYSTEM 3755702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3766221Snate@binkert.org Fault hwrei(ThreadID tid); 3775702Ssaidi@eecs.umich.edu 3786221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3795702Ssaidi@eecs.umich.edu 3805595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3815595Sgblack@eecs.umich.edu Fault getInterrupts(); 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 3845595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3875595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3885595Sgblack@eecs.umich.edu 3894192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3904192Sktlim@umich.edu * reflect change in memory connections. */ 3914192Sktlim@umich.edu void updateMemPorts(); 3924192Sktlim@umich.edu 3931060SN/A /** Check if this address is a valid instruction address. */ 3941060SN/A bool validInstAddr(Addr addr) { return true; } 3951060SN/A 3961060SN/A /** Check if this address is a valid data address. */ 3971060SN/A bool validDataAddr(Addr addr) { return true; } 3981060SN/A#endif 3991060SN/A 4002348SN/A /** Register accessors. Index refers to the physical register index. */ 4015595Sgblack@eecs.umich.edu 4025595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4036221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4045595Sgblack@eecs.umich.edu 4055595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4065595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4075595Sgblack@eecs.umich.edu */ 4086221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4095595Sgblack@eecs.umich.edu 4105595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4116221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4126221Snate@binkert.org ThreadID tid); 4135595Sgblack@eecs.umich.edu 4145595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4155595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4165595Sgblack@eecs.umich.edu */ 4175595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4186221Snate@binkert.org ThreadID tid); 4195595Sgblack@eecs.umich.edu 4201060SN/A uint64_t readIntReg(int reg_idx); 4211060SN/A 4223781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4231060SN/A 4243781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4252455SN/A 4261060SN/A void setIntReg(int reg_idx, uint64_t val); 4271060SN/A 4283781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4291060SN/A 4303781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4312455SN/A 4326221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4331060SN/A 4346314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4352292SN/A 4366221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4372292SN/A 4382348SN/A /** Architectural register accessors. Looks up in the commit 4392348SN/A * rename table to obtain the true physical index of the 4402348SN/A * architected register first, then accesses that physical 4412348SN/A * register. 4422348SN/A */ 4436221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4442292SN/A 4456314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4462292SN/A 4476221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4482292SN/A 4497720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 4507720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4517720Sgblack@eecs.umich.edu 4527720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 4537720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 4547720Sgblack@eecs.umich.edu 4552348SN/A /** Reads the commit PC of a specific thread. */ 4567720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 4572292SN/A 4584636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4597720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4604636Sgblack@eecs.umich.edu 4612348SN/A /** Reads the next PC of a specific thread. */ 4627720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4632756Sksewell@umich.edu 4645595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4655595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4665595Sgblack@eecs.umich.edu * state through the TC. 4675595Sgblack@eecs.umich.edu */ 4686221Snate@binkert.org void squashFromTC(ThreadID tid); 4695595Sgblack@eecs.umich.edu 4701060SN/A /** Function to add instruction onto the head of the list of the 4711060SN/A * instructions. Used when new instructions are fetched. 4721060SN/A */ 4732292SN/A ListIt addInst(DynInstPtr &inst); 4741060SN/A 4751060SN/A /** Function to tell the CPU that an instruction has completed. */ 4766221Snate@binkert.org void instDone(ThreadID tid); 4771060SN/A 4782292SN/A /** Add Instructions to the CPU Remove List*/ 4792292SN/A void addToRemoveList(DynInstPtr &inst); 4801060SN/A 4812325SN/A /** Remove an instruction from the front end of the list. There's 4822325SN/A * no restriction on location of the instruction. 4831060SN/A */ 4841061SN/A void removeFrontInst(DynInstPtr &inst); 4851060SN/A 4862935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4872935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4886221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 4891060SN/A 4901062SN/A /** Remove all instructions younger than the given sequence number. */ 4916221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 4922292SN/A 4932348SN/A /** Removes the instruction pointed to by the iterator. */ 4946221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 4952292SN/A 4962348SN/A /** Cleans up all instructions on the remove list. */ 4972292SN/A void cleanUpRemovedInsts(); 4981062SN/A 4992348SN/A /** Debug function to print all instructions on the list. */ 5001060SN/A void dumpInsts(); 5011060SN/A 5021060SN/A public: 5035737Scws3k@cs.virginia.edu#ifndef NDEBUG 5045737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5055737Scws3k@cs.virginia.edu int instcount; 5065737Scws3k@cs.virginia.edu#endif 5075737Scws3k@cs.virginia.edu 5081060SN/A /** List of all the instructions in flight. */ 5092292SN/A std::list<DynInstPtr> instList; 5101060SN/A 5112292SN/A /** List of all the instructions that will be removed at the end of this 5122292SN/A * cycle. 5132292SN/A */ 5142292SN/A std::queue<ListIt> removeList; 5152292SN/A 5162325SN/A#ifdef DEBUG 5172348SN/A /** Debug structure to keep track of the sequence numbers still in 5182348SN/A * flight. 5192348SN/A */ 5202292SN/A std::set<InstSeqNum> snList; 5212325SN/A#endif 5222292SN/A 5232325SN/A /** Records if instructions need to be removed this cycle due to 5242325SN/A * being retired or squashed. 5252292SN/A */ 5262292SN/A bool removeInstsThisCycle; 5272292SN/A 5281060SN/A protected: 5291060SN/A /** The fetch stage. */ 5301060SN/A typename CPUPolicy::Fetch fetch; 5311060SN/A 5321060SN/A /** The decode stage. */ 5331060SN/A typename CPUPolicy::Decode decode; 5341060SN/A 5351060SN/A /** The dispatch stage. */ 5361060SN/A typename CPUPolicy::Rename rename; 5371060SN/A 5381060SN/A /** The issue/execute/writeback stages. */ 5391060SN/A typename CPUPolicy::IEW iew; 5401060SN/A 5411060SN/A /** The commit stage. */ 5421060SN/A typename CPUPolicy::Commit commit; 5431060SN/A 5441060SN/A /** The register file. */ 5451060SN/A typename CPUPolicy::RegFile regFile; 5461060SN/A 5471060SN/A /** The free list. */ 5481060SN/A typename CPUPolicy::FreeList freeList; 5491060SN/A 5501060SN/A /** The rename map. */ 5512292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5522292SN/A 5532292SN/A /** The commit rename map. */ 5542292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5551060SN/A 5561060SN/A /** The re-order buffer. */ 5571060SN/A typename CPUPolicy::ROB rob; 5581060SN/A 5592292SN/A /** Active Threads List */ 5606221Snate@binkert.org std::list<ThreadID> activeThreads; 5612292SN/A 5622292SN/A /** Integer Register Scoreboard */ 5632292SN/A Scoreboard scoreboard; 5642292SN/A 5656313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 5666313Sgblack@eecs.umich.edu 5671060SN/A public: 5682292SN/A /** Enum to give each stage a specific index, so when calling 5692292SN/A * activateStage() or deactivateStage(), they can specify which stage 5702292SN/A * is being activated/deactivated. 5712292SN/A */ 5722292SN/A enum StageIdx { 5732292SN/A FetchIdx, 5742292SN/A DecodeIdx, 5752292SN/A RenameIdx, 5762292SN/A IEWIdx, 5772292SN/A CommitIdx, 5782292SN/A NumStages }; 5792292SN/A 5801060SN/A /** Typedefs from the Impl to get the structs that each of the 5811060SN/A * time buffers should use. 5821060SN/A */ 5831061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5841060SN/A 5851061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5861060SN/A 5871061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5881060SN/A 5891061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5901060SN/A 5911061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5921060SN/A 5931060SN/A /** The main time buffer to do backwards communication. */ 5941060SN/A TimeBuffer<TimeStruct> timeBuffer; 5951060SN/A 5961060SN/A /** The fetch stage's instruction queue. */ 5971060SN/A TimeBuffer<FetchStruct> fetchQueue; 5981060SN/A 5991060SN/A /** The decode stage's instruction queue. */ 6001060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6011060SN/A 6021060SN/A /** The rename stage's instruction queue. */ 6031060SN/A TimeBuffer<RenameStruct> renameQueue; 6041060SN/A 6051060SN/A /** The IEW stage's instruction queue. */ 6061060SN/A TimeBuffer<IEWStruct> iewQueue; 6071060SN/A 6082348SN/A private: 6092348SN/A /** The activity recorder; used to tell if the CPU has any 6102348SN/A * activity remaining or if it can go to idle and deschedule 6112348SN/A * itself. 6122348SN/A */ 6132325SN/A ActivityRecorder activityRec; 6141060SN/A 6152348SN/A public: 6162348SN/A /** Records that there was time buffer activity this cycle. */ 6172325SN/A void activityThisCycle() { activityRec.activity(); } 6182292SN/A 6192348SN/A /** Changes a stage's status to active within the activity recorder. */ 6202325SN/A void activateStage(const StageIdx idx) 6212325SN/A { activityRec.activateStage(idx); } 6222292SN/A 6232348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6242325SN/A void deactivateStage(const StageIdx idx) 6252325SN/A { activityRec.deactivateStage(idx); } 6262292SN/A 6272292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6282292SN/A void wakeCPU(); 6292260SN/A 6305807Snate@binkert.org#if FULL_SYSTEM 6315807Snate@binkert.org virtual void wakeup(); 6325807Snate@binkert.org#endif 6335807Snate@binkert.org 6342292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6356221Snate@binkert.org ThreadID getFreeTid(); 6362292SN/A 6372292SN/A public: 6382680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6396221Snate@binkert.org ThreadContext * 6406221Snate@binkert.org tcBase(ThreadID tid) 6411681SN/A { 6422680Sktlim@umich.edu return thread[tid]->getTC(); 6432190SN/A } 6442190SN/A 6452292SN/A /** The global sequence number counter. */ 6463093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6471060SN/A 6484598Sbinkertn@umich.edu#if USE_CHECKER 6492348SN/A /** Pointer to the checker, which can dynamically verify 6502348SN/A * instruction results at run time. This can be set to NULL if it 6512348SN/A * is not being used. 6522348SN/A */ 6532316SN/A Checker<DynInstPtr> *checker; 6544598Sbinkertn@umich.edu#endif 6552316SN/A 6561858SN/A#if FULL_SYSTEM 6572292SN/A /** Pointer to the system. */ 6581060SN/A System *system; 6592292SN/A#endif 6601060SN/A 6612843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6622843Sktlim@umich.edu Event *drainEvent; 6632843Sktlim@umich.edu 6642843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6652843Sktlim@umich.edu int drainCount; 6662316SN/A 6672348SN/A /** Pointers to all of the threads in the CPU. */ 6682292SN/A std::vector<Thread *> thread; 6692260SN/A 6702292SN/A /** Whether or not the CPU should defer its registration. */ 6711060SN/A bool deferRegistration; 6721060SN/A 6732292SN/A /** Is there a context switch pending? */ 6742292SN/A bool contextSwitch; 6751060SN/A 6762292SN/A /** Threads Scheduled to Enter CPU */ 6772292SN/A std::list<int> cpuWaitList; 6782292SN/A 6792292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6802292SN/A Tick lastRunningCycle; 6812292SN/A 6822829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6832829Sksewell@umich.edu Tick lastActivatedCycle; 6842829Sksewell@umich.edu 6852292SN/A /** Mapping for system thread id to cpu id */ 6866221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 6872292SN/A 6882292SN/A /** Available thread ids in the cpu*/ 6896221Snate@binkert.org std::vector<ThreadID> tids; 6902292SN/A 6915595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 6926974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6937520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 6945595Sgblack@eecs.umich.edu { 6956974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 6966974Stjones1@inf.ed.ac.uk data, load_idx); 6975595Sgblack@eecs.umich.edu } 6985595Sgblack@eecs.umich.edu 6995595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7006974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7017520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7025595Sgblack@eecs.umich.edu { 7036974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7046974Stjones1@inf.ed.ac.uk data, store_idx); 7055595Sgblack@eecs.umich.edu } 7065595Sgblack@eecs.umich.edu 7076974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7086974Stjones1@inf.ed.ac.uk Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 7096974Stjones1@inf.ed.ac.uk 7105595Sgblack@eecs.umich.edu Addr lockAddr; 7115595Sgblack@eecs.umich.edu 7125595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7135595Sgblack@eecs.umich.edu bool lockFlag; 7145595Sgblack@eecs.umich.edu 7152292SN/A /** Stat for total number of times the CPU is descheduled. */ 7165999Snate@binkert.org Stats::Scalar timesIdled; 7172292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7185999Snate@binkert.org Stats::Scalar idleCycles; 7192292SN/A /** Stat for the number of committed instructions per thread. */ 7205999Snate@binkert.org Stats::Vector committedInsts; 7212292SN/A /** Stat for the total number of committed instructions. */ 7225999Snate@binkert.org Stats::Scalar totalCommittedInsts; 7232292SN/A /** Stat for the CPI per thread. */ 7242292SN/A Stats::Formula cpi; 7252292SN/A /** Stat for the total CPI. */ 7262292SN/A Stats::Formula totalCpi; 7272292SN/A /** Stat for the IPC per thread. */ 7282292SN/A Stats::Formula ipc; 7292292SN/A /** Stat for the total IPC. */ 7302292SN/A Stats::Formula totalIpc; 7317897Shestness@cs.utexas.edu 7327897Shestness@cs.utexas.edu //number of integer register file accesses 7337897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 7347897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 7357897Shestness@cs.utexas.edu //number of float register file accesses 7367897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 7377897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 7387897Shestness@cs.utexas.edu //number of misc 7397897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 7407897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 7411060SN/A}; 7421060SN/A 7432325SN/A#endif // __CPU_O3_CPU_HH__ 744