cpu.hh revision 6314
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 565529Snate@binkert.org#include "params/DerivO3CPU.hh" 575529Snate@binkert.org 582316SN/Atemplate <class> 592316SN/Aclass Checker; 602680Sktlim@umich.educlass ThreadContext; 612817Sksewell@umich.edutemplate <class> 622817Sksewell@umich.educlass O3ThreadContext; 632843Sktlim@umich.edu 642843Sktlim@umich.educlass Checkpoint; 652669Sktlim@umich.educlass MemObject; 661060SN/Aclass Process; 671060SN/A 685529Snate@binkert.orgclass BaseCPUParams; 695529Snate@binkert.org 702733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 711060SN/A{ 721060SN/A //Stuff that's pretty ISA independent will go here. 731060SN/A public: 745529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 752292SN/A 762292SN/A void regStats(); 771060SN/A}; 781060SN/A 792348SN/A/** 802348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 812348SN/A * within it, as well as all of the time buffers between stages. The 822348SN/A * tick() function for the CPU is defined here. 832348SN/A */ 841060SN/Atemplate <class Impl> 852733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 861060SN/A{ 871060SN/A public: 882325SN/A // Typedefs from the Impl here. 891060SN/A typedef typename Impl::CPUPol CPUPolicy; 901061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 914329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 921060SN/A 935595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 942292SN/A typedef O3ThreadState<Impl> Thread; 952292SN/A 962292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972292SN/A 982817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 992829Sksewell@umich.edu 1001060SN/A public: 1011060SN/A enum Status { 1021060SN/A Running, 1031060SN/A Idle, 1041060SN/A Halted, 1052307SN/A Blocked, 1062307SN/A SwitchedOut 1071060SN/A }; 1081060SN/A 1096022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1106022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1113781Sgblack@eecs.umich.edu 1122292SN/A /** Overall CPU status. */ 1131060SN/A Status _status; 1141060SN/A 1152829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1162829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1172829Sksewell@umich.edu 1181060SN/A private: 1191060SN/A class TickEvent : public Event 1201060SN/A { 1211060SN/A private: 1222292SN/A /** Pointer to the CPU. */ 1231755SN/A FullO3CPU<Impl> *cpu; 1241060SN/A 1251060SN/A public: 1262292SN/A /** Constructs a tick event. */ 1271755SN/A TickEvent(FullO3CPU<Impl> *c); 1282292SN/A 1292292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1301060SN/A void process(); 1312292SN/A /** Returns the description of the tick event. */ 1325336Shines@cs.fsu.edu const char *description() const; 1331060SN/A }; 1341060SN/A 1352292SN/A /** The tick event used for scheduling CPU ticks. */ 1361060SN/A TickEvent tickEvent; 1371060SN/A 1382292SN/A /** Schedule tick event, regardless of its current state. */ 1391060SN/A void scheduleTickEvent(int delay) 1401060SN/A { 1411060SN/A if (tickEvent.squashed()) 1425606Snate@binkert.org reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 1431060SN/A else if (!tickEvent.scheduled()) 1445606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(delay))); 1451060SN/A } 1461060SN/A 1472292SN/A /** Unschedule tick event, regardless of its current state. */ 1481060SN/A void unscheduleTickEvent() 1491060SN/A { 1501060SN/A if (tickEvent.scheduled()) 1511060SN/A tickEvent.squash(); 1521060SN/A } 1531060SN/A 1542829Sksewell@umich.edu class ActivateThreadEvent : public Event 1552829Sksewell@umich.edu { 1562829Sksewell@umich.edu private: 1572829Sksewell@umich.edu /** Number of Thread to Activate */ 1586221Snate@binkert.org ThreadID tid; 1592829Sksewell@umich.edu 1602829Sksewell@umich.edu /** Pointer to the CPU. */ 1612829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1622829Sksewell@umich.edu 1632829Sksewell@umich.edu public: 1642829Sksewell@umich.edu /** Constructs the event. */ 1652829Sksewell@umich.edu ActivateThreadEvent(); 1662829Sksewell@umich.edu 1672829Sksewell@umich.edu /** Initialize Event */ 1682829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1712829Sksewell@umich.edu void process(); 1722829Sksewell@umich.edu 1732829Sksewell@umich.edu /** Returns the description of the event. */ 1745336Shines@cs.fsu.edu const char *description() const; 1752829Sksewell@umich.edu }; 1762829Sksewell@umich.edu 1772829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1786221Snate@binkert.org void 1796221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 1802829Sksewell@umich.edu { 1812829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1822829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1835606Snate@binkert.org reschedule(activateThreadEvent[tid], 1845606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1852829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1865606Snate@binkert.org schedule(activateThreadEvent[tid], 1875606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1882829Sksewell@umich.edu } 1892829Sksewell@umich.edu 1902829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1916221Snate@binkert.org void 1926221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 1932829Sksewell@umich.edu { 1942829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1952829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1962829Sksewell@umich.edu } 1972829Sksewell@umich.edu 1982829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 1992829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2002829Sksewell@umich.edu 2012875Sksewell@umich.edu class DeallocateContextEvent : public Event 2022875Sksewell@umich.edu { 2032875Sksewell@umich.edu private: 2043221Sktlim@umich.edu /** Number of Thread to deactivate */ 2056221Snate@binkert.org ThreadID tid; 2062875Sksewell@umich.edu 2073221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2083221Sktlim@umich.edu bool remove; 2093221Sktlim@umich.edu 2102875Sksewell@umich.edu /** Pointer to the CPU. */ 2112875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2122875Sksewell@umich.edu 2132875Sksewell@umich.edu public: 2142875Sksewell@umich.edu /** Constructs the event. */ 2152875Sksewell@umich.edu DeallocateContextEvent(); 2162875Sksewell@umich.edu 2172875Sksewell@umich.edu /** Initialize Event */ 2182875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2192875Sksewell@umich.edu 2202875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2212875Sksewell@umich.edu void process(); 2222875Sksewell@umich.edu 2233221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2243221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2253221Sktlim@umich.edu 2262875Sksewell@umich.edu /** Returns the description of the event. */ 2275336Shines@cs.fsu.edu const char *description() const; 2282875Sksewell@umich.edu }; 2292875Sksewell@umich.edu 2302875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2316221Snate@binkert.org void 2326221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 2332875Sksewell@umich.edu { 2342875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2352875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2365606Snate@binkert.org reschedule(deallocateContextEvent[tid], 2375606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2382875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2395606Snate@binkert.org schedule(deallocateContextEvent[tid], 2405606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2412875Sksewell@umich.edu } 2422875Sksewell@umich.edu 2432875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2446221Snate@binkert.org void 2456221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 2462875Sksewell@umich.edu { 2472875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2482875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2492875Sksewell@umich.edu } 2502875Sksewell@umich.edu 2512875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2522875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2532875Sksewell@umich.edu 2541060SN/A public: 2552292SN/A /** Constructs a CPU with the given parameters. */ 2565595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2572292SN/A /** Destructor. */ 2581755SN/A ~FullO3CPU(); 2591060SN/A 2602292SN/A /** Registers statistics. */ 2615595Sgblack@eecs.umich.edu void regStats(); 2621684SN/A 2635358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2645358Sgblack@eecs.umich.edu { 2655358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2665358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2675358Sgblack@eecs.umich.edu } 2685358Sgblack@eecs.umich.edu 2695358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2705358Sgblack@eecs.umich.edu { 2715358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2725358Sgblack@eecs.umich.edu } 2735358Sgblack@eecs.umich.edu 2745358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2755358Sgblack@eecs.umich.edu { 2765358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2775358Sgblack@eecs.umich.edu } 2785358Sgblack@eecs.umich.edu 2792871Sktlim@umich.edu /** Returns a specific port. */ 2802871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2812871Sktlim@umich.edu 2822292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2832292SN/A * activity to see if the CPU should deschedule itself. 2842292SN/A */ 2851684SN/A void tick(); 2861684SN/A 2872292SN/A /** Initialize the CPU */ 2881060SN/A void init(); 2891060SN/A 2902834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2912834Sksewell@umich.edu int numActiveThreads() 2922834Sksewell@umich.edu { return activeThreads.size(); } 2932834Sksewell@umich.edu 2942829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2956221Snate@binkert.org void activateThread(ThreadID tid); 2962875Sksewell@umich.edu 2972875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2986221Snate@binkert.org void deactivateThread(ThreadID tid); 2992829Sksewell@umich.edu 3002292SN/A /** Setup CPU to insert a thread's context */ 3016221Snate@binkert.org void insertThread(ThreadID tid); 3021060SN/A 3032292SN/A /** Remove all of a thread's context from CPU */ 3046221Snate@binkert.org void removeThread(ThreadID tid); 3052292SN/A 3062292SN/A /** Count the Total Instructions Committed in the CPU. */ 3076221Snate@binkert.org virtual Counter totalInstructions() const; 3082292SN/A 3092292SN/A /** Add Thread to Active Threads List. */ 3106221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3112292SN/A 3122292SN/A /** Remove Thread from Active Threads List */ 3136221Snate@binkert.org void suspendContext(ThreadID tid); 3142292SN/A 3152292SN/A /** Remove Thread from Active Threads List && 3163221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3172292SN/A */ 3186221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 3192292SN/A 3202292SN/A /** Remove Thread from Active Threads List && 3212292SN/A * Remove Thread Context from CPU. 3222292SN/A */ 3236221Snate@binkert.org void haltContext(ThreadID tid); 3242292SN/A 3252292SN/A /** Activate a Thread When CPU Resources are Available. */ 3266221Snate@binkert.org void activateWhenReady(ThreadID tid); 3272292SN/A 3282292SN/A /** Add or Remove a Thread Context in the CPU. */ 3292292SN/A void doContextSwitch(); 3302292SN/A 3312292SN/A /** Update The Order In Which We Process Threads. */ 3322292SN/A void updateThreadPriority(); 3332292SN/A 3342864Sktlim@umich.edu /** Serialize state. */ 3352864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3362864Sktlim@umich.edu 3372864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3382864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3392864Sktlim@umich.edu 3402864Sktlim@umich.edu public: 3415595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3425595Sgblack@eecs.umich.edu /** Executes a syscall. 3435595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3442292SN/A */ 3456221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 3465595Sgblack@eecs.umich.edu#endif 3472292SN/A 3482843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3492843Sktlim@umich.edu * order to stop all memory accesses. */ 3502905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3512843Sktlim@umich.edu 3522843Sktlim@umich.edu /** Resumes execution after a drain. */ 3532843Sktlim@umich.edu virtual void resume(); 3542292SN/A 3552348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3562843Sktlim@umich.edu void signalDrained(); 3572843Sktlim@umich.edu 3582843Sktlim@umich.edu /** Switches out this CPU. */ 3592843Sktlim@umich.edu virtual void switchOut(); 3602316SN/A 3612348SN/A /** Takes over from another CPU. */ 3622843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3631060SN/A 3641060SN/A /** Get the current instruction sequence number, and increment it. */ 3652316SN/A InstSeqNum getAndIncrementInstSeq() 3662316SN/A { return globalSeqNum++; } 3671060SN/A 3685595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3696221Snate@binkert.org void trap(Fault fault, ThreadID tid); 3705595Sgblack@eecs.umich.edu 3711858SN/A#if FULL_SYSTEM 3725702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3736221Snate@binkert.org Fault hwrei(ThreadID tid); 3745702Ssaidi@eecs.umich.edu 3756221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3765702Ssaidi@eecs.umich.edu 3775595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3785595Sgblack@eecs.umich.edu Fault getInterrupts(); 3795595Sgblack@eecs.umich.edu 3805595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 3815595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3845595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3855595Sgblack@eecs.umich.edu 3864192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3874192Sktlim@umich.edu * reflect change in memory connections. */ 3884192Sktlim@umich.edu void updateMemPorts(); 3894192Sktlim@umich.edu 3901060SN/A /** Check if this address is a valid instruction address. */ 3911060SN/A bool validInstAddr(Addr addr) { return true; } 3921060SN/A 3931060SN/A /** Check if this address is a valid data address. */ 3941060SN/A bool validDataAddr(Addr addr) { return true; } 3951060SN/A 3961060SN/A /** Get instruction asid. */ 3976221Snate@binkert.org int getInstAsid(ThreadID tid) 3986313Sgblack@eecs.umich.edu { return isa[tid].instAsid(); } 3991060SN/A 4001060SN/A /** Get data asid. */ 4016221Snate@binkert.org int getDataAsid(ThreadID tid) 4026313Sgblack@eecs.umich.edu { return isa[tid].dataAsid(); } 4031060SN/A#else 4042292SN/A /** Get instruction asid. */ 4056221Snate@binkert.org int getInstAsid(ThreadID tid) 4062683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4071060SN/A 4082292SN/A /** Get data asid. */ 4096221Snate@binkert.org int getDataAsid(ThreadID tid) 4102683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4111060SN/A 4121060SN/A#endif 4131060SN/A 4142348SN/A /** Register accessors. Index refers to the physical register index. */ 4155595Sgblack@eecs.umich.edu 4165595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4176221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4185595Sgblack@eecs.umich.edu 4195595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4205595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4215595Sgblack@eecs.umich.edu */ 4226221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4235595Sgblack@eecs.umich.edu 4245595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4256221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4266221Snate@binkert.org ThreadID tid); 4275595Sgblack@eecs.umich.edu 4285595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4295595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4305595Sgblack@eecs.umich.edu */ 4315595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4326221Snate@binkert.org ThreadID tid); 4335595Sgblack@eecs.umich.edu 4341060SN/A uint64_t readIntReg(int reg_idx); 4351060SN/A 4363781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4371060SN/A 4383781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4392455SN/A 4401060SN/A void setIntReg(int reg_idx, uint64_t val); 4411060SN/A 4423781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4431060SN/A 4443781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4452455SN/A 4466221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4471060SN/A 4486314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4492292SN/A 4506221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4512292SN/A 4522348SN/A /** Architectural register accessors. Looks up in the commit 4532348SN/A * rename table to obtain the true physical index of the 4542348SN/A * architected register first, then accesses that physical 4552348SN/A * register. 4562348SN/A */ 4576221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4582292SN/A 4596314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4602292SN/A 4616221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4622292SN/A 4632348SN/A /** Reads the commit PC of a specific thread. */ 4646221Snate@binkert.org Addr readPC(ThreadID tid); 4652292SN/A 4662348SN/A /** Sets the commit PC of a specific thread. */ 4676221Snate@binkert.org void setPC(Addr new_PC, ThreadID tid); 4682292SN/A 4694636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4706221Snate@binkert.org Addr readMicroPC(ThreadID tid); 4714636Sgblack@eecs.umich.edu 4724636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 4736221Snate@binkert.org void setMicroPC(Addr new_microPC, ThreadID tid); 4744636Sgblack@eecs.umich.edu 4752348SN/A /** Reads the next PC of a specific thread. */ 4766221Snate@binkert.org Addr readNextPC(ThreadID tid); 4772292SN/A 4782348SN/A /** Sets the next PC of a specific thread. */ 4796221Snate@binkert.org void setNextPC(Addr val, ThreadID tid); 4801060SN/A 4812756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4826221Snate@binkert.org Addr readNextNPC(ThreadID tid); 4832756Sksewell@umich.edu 4842756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4856221Snate@binkert.org void setNextNPC(Addr val, ThreadID tid); 4864636Sgblack@eecs.umich.edu 4874636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 4886221Snate@binkert.org Addr readNextMicroPC(ThreadID tid); 4894636Sgblack@eecs.umich.edu 4904636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 4916221Snate@binkert.org void setNextMicroPC(Addr val, ThreadID tid); 4922756Sksewell@umich.edu 4935595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4945595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4955595Sgblack@eecs.umich.edu * state through the TC. 4965595Sgblack@eecs.umich.edu */ 4976221Snate@binkert.org void squashFromTC(ThreadID tid); 4985595Sgblack@eecs.umich.edu 4991060SN/A /** Function to add instruction onto the head of the list of the 5001060SN/A * instructions. Used when new instructions are fetched. 5011060SN/A */ 5022292SN/A ListIt addInst(DynInstPtr &inst); 5031060SN/A 5041060SN/A /** Function to tell the CPU that an instruction has completed. */ 5056221Snate@binkert.org void instDone(ThreadID tid); 5061060SN/A 5072292SN/A /** Add Instructions to the CPU Remove List*/ 5082292SN/A void addToRemoveList(DynInstPtr &inst); 5091060SN/A 5102325SN/A /** Remove an instruction from the front end of the list. There's 5112325SN/A * no restriction on location of the instruction. 5121060SN/A */ 5131061SN/A void removeFrontInst(DynInstPtr &inst); 5141060SN/A 5152935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5162935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5176221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5181060SN/A 5191062SN/A /** Remove all instructions younger than the given sequence number. */ 5206221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5212292SN/A 5222348SN/A /** Removes the instruction pointed to by the iterator. */ 5236221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5242292SN/A 5252348SN/A /** Cleans up all instructions on the remove list. */ 5262292SN/A void cleanUpRemovedInsts(); 5271062SN/A 5282348SN/A /** Debug function to print all instructions on the list. */ 5291060SN/A void dumpInsts(); 5301060SN/A 5311060SN/A public: 5325737Scws3k@cs.virginia.edu#ifndef NDEBUG 5335737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5345737Scws3k@cs.virginia.edu int instcount; 5355737Scws3k@cs.virginia.edu#endif 5365737Scws3k@cs.virginia.edu 5371060SN/A /** List of all the instructions in flight. */ 5382292SN/A std::list<DynInstPtr> instList; 5391060SN/A 5402292SN/A /** List of all the instructions that will be removed at the end of this 5412292SN/A * cycle. 5422292SN/A */ 5432292SN/A std::queue<ListIt> removeList; 5442292SN/A 5452325SN/A#ifdef DEBUG 5462348SN/A /** Debug structure to keep track of the sequence numbers still in 5472348SN/A * flight. 5482348SN/A */ 5492292SN/A std::set<InstSeqNum> snList; 5502325SN/A#endif 5512292SN/A 5522325SN/A /** Records if instructions need to be removed this cycle due to 5532325SN/A * being retired or squashed. 5542292SN/A */ 5552292SN/A bool removeInstsThisCycle; 5562292SN/A 5571060SN/A protected: 5581060SN/A /** The fetch stage. */ 5591060SN/A typename CPUPolicy::Fetch fetch; 5601060SN/A 5611060SN/A /** The decode stage. */ 5621060SN/A typename CPUPolicy::Decode decode; 5631060SN/A 5641060SN/A /** The dispatch stage. */ 5651060SN/A typename CPUPolicy::Rename rename; 5661060SN/A 5671060SN/A /** The issue/execute/writeback stages. */ 5681060SN/A typename CPUPolicy::IEW iew; 5691060SN/A 5701060SN/A /** The commit stage. */ 5711060SN/A typename CPUPolicy::Commit commit; 5721060SN/A 5731060SN/A /** The register file. */ 5741060SN/A typename CPUPolicy::RegFile regFile; 5751060SN/A 5761060SN/A /** The free list. */ 5771060SN/A typename CPUPolicy::FreeList freeList; 5781060SN/A 5791060SN/A /** The rename map. */ 5802292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5812292SN/A 5822292SN/A /** The commit rename map. */ 5832292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5841060SN/A 5851060SN/A /** The re-order buffer. */ 5861060SN/A typename CPUPolicy::ROB rob; 5871060SN/A 5882292SN/A /** Active Threads List */ 5896221Snate@binkert.org std::list<ThreadID> activeThreads; 5902292SN/A 5912292SN/A /** Integer Register Scoreboard */ 5922292SN/A Scoreboard scoreboard; 5932292SN/A 5946313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 5956313Sgblack@eecs.umich.edu 5961060SN/A public: 5972292SN/A /** Enum to give each stage a specific index, so when calling 5982292SN/A * activateStage() or deactivateStage(), they can specify which stage 5992292SN/A * is being activated/deactivated. 6002292SN/A */ 6012292SN/A enum StageIdx { 6022292SN/A FetchIdx, 6032292SN/A DecodeIdx, 6042292SN/A RenameIdx, 6052292SN/A IEWIdx, 6062292SN/A CommitIdx, 6072292SN/A NumStages }; 6082292SN/A 6091060SN/A /** Typedefs from the Impl to get the structs that each of the 6101060SN/A * time buffers should use. 6111060SN/A */ 6121061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6131060SN/A 6141061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6151060SN/A 6161061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6171060SN/A 6181061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6191060SN/A 6201061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6211060SN/A 6221060SN/A /** The main time buffer to do backwards communication. */ 6231060SN/A TimeBuffer<TimeStruct> timeBuffer; 6241060SN/A 6251060SN/A /** The fetch stage's instruction queue. */ 6261060SN/A TimeBuffer<FetchStruct> fetchQueue; 6271060SN/A 6281060SN/A /** The decode stage's instruction queue. */ 6291060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6301060SN/A 6311060SN/A /** The rename stage's instruction queue. */ 6321060SN/A TimeBuffer<RenameStruct> renameQueue; 6331060SN/A 6341060SN/A /** The IEW stage's instruction queue. */ 6351060SN/A TimeBuffer<IEWStruct> iewQueue; 6361060SN/A 6372348SN/A private: 6382348SN/A /** The activity recorder; used to tell if the CPU has any 6392348SN/A * activity remaining or if it can go to idle and deschedule 6402348SN/A * itself. 6412348SN/A */ 6422325SN/A ActivityRecorder activityRec; 6431060SN/A 6442348SN/A public: 6452348SN/A /** Records that there was time buffer activity this cycle. */ 6462325SN/A void activityThisCycle() { activityRec.activity(); } 6472292SN/A 6482348SN/A /** Changes a stage's status to active within the activity recorder. */ 6492325SN/A void activateStage(const StageIdx idx) 6502325SN/A { activityRec.activateStage(idx); } 6512292SN/A 6522348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6532325SN/A void deactivateStage(const StageIdx idx) 6542325SN/A { activityRec.deactivateStage(idx); } 6552292SN/A 6562292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6572292SN/A void wakeCPU(); 6582260SN/A 6595807Snate@binkert.org#if FULL_SYSTEM 6605807Snate@binkert.org virtual void wakeup(); 6615807Snate@binkert.org#endif 6625807Snate@binkert.org 6632292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6646221Snate@binkert.org ThreadID getFreeTid(); 6652292SN/A 6662292SN/A public: 6672680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6686221Snate@binkert.org ThreadContext * 6696221Snate@binkert.org tcBase(ThreadID tid) 6701681SN/A { 6712680Sktlim@umich.edu return thread[tid]->getTC(); 6722190SN/A } 6732190SN/A 6742292SN/A /** The global sequence number counter. */ 6753093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6761060SN/A 6774598Sbinkertn@umich.edu#if USE_CHECKER 6782348SN/A /** Pointer to the checker, which can dynamically verify 6792348SN/A * instruction results at run time. This can be set to NULL if it 6802348SN/A * is not being used. 6812348SN/A */ 6822316SN/A Checker<DynInstPtr> *checker; 6834598Sbinkertn@umich.edu#endif 6842316SN/A 6851858SN/A#if FULL_SYSTEM 6862292SN/A /** Pointer to the system. */ 6871060SN/A System *system; 6881060SN/A 6892292SN/A /** Pointer to physical memory. */ 6901060SN/A PhysicalMemory *physmem; 6912292SN/A#endif 6921060SN/A 6932843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6942843Sktlim@umich.edu Event *drainEvent; 6952843Sktlim@umich.edu 6962843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6972843Sktlim@umich.edu int drainCount; 6982316SN/A 6992348SN/A /** Pointers to all of the threads in the CPU. */ 7002292SN/A std::vector<Thread *> thread; 7012260SN/A 7022292SN/A /** Whether or not the CPU should defer its registration. */ 7031060SN/A bool deferRegistration; 7041060SN/A 7052292SN/A /** Is there a context switch pending? */ 7062292SN/A bool contextSwitch; 7071060SN/A 7082292SN/A /** Threads Scheduled to Enter CPU */ 7092292SN/A std::list<int> cpuWaitList; 7102292SN/A 7112292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7122292SN/A Tick lastRunningCycle; 7132292SN/A 7142829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7152829Sksewell@umich.edu Tick lastActivatedCycle; 7162829Sksewell@umich.edu 7172292SN/A /** Mapping for system thread id to cpu id */ 7186221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7192292SN/A 7202292SN/A /** Available thread ids in the cpu*/ 7216221Snate@binkert.org std::vector<ThreadID> tids; 7222292SN/A 7235595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7245595Sgblack@eecs.umich.edu template <class T> 7255595Sgblack@eecs.umich.edu Fault read(RequestPtr &req, T &data, int load_idx) 7265595Sgblack@eecs.umich.edu { 7275595Sgblack@eecs.umich.edu return this->iew.ldstQueue.read(req, data, load_idx); 7285595Sgblack@eecs.umich.edu } 7295595Sgblack@eecs.umich.edu 7305595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7315595Sgblack@eecs.umich.edu template <class T> 7325595Sgblack@eecs.umich.edu Fault write(RequestPtr &req, T &data, int store_idx) 7335595Sgblack@eecs.umich.edu { 7345595Sgblack@eecs.umich.edu return this->iew.ldstQueue.write(req, data, store_idx); 7355595Sgblack@eecs.umich.edu } 7365595Sgblack@eecs.umich.edu 7375595Sgblack@eecs.umich.edu Addr lockAddr; 7385595Sgblack@eecs.umich.edu 7395595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7405595Sgblack@eecs.umich.edu bool lockFlag; 7415595Sgblack@eecs.umich.edu 7422292SN/A /** Stat for total number of times the CPU is descheduled. */ 7435999Snate@binkert.org Stats::Scalar timesIdled; 7442292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7455999Snate@binkert.org Stats::Scalar idleCycles; 7462292SN/A /** Stat for the number of committed instructions per thread. */ 7475999Snate@binkert.org Stats::Vector committedInsts; 7482292SN/A /** Stat for the total number of committed instructions. */ 7495999Snate@binkert.org Stats::Scalar totalCommittedInsts; 7502292SN/A /** Stat for the CPI per thread. */ 7512292SN/A Stats::Formula cpi; 7522292SN/A /** Stat for the total CPI. */ 7532292SN/A Stats::Formula totalCpi; 7542292SN/A /** Stat for the IPC per thread. */ 7552292SN/A Stats::Formula ipc; 7562292SN/A /** Stat for the total IPC. */ 7572292SN/A Stats::Formula totalIpc; 7581060SN/A}; 7591060SN/A 7602325SN/A#endif // __CPU_O3_CPU_HH__ 761