cpu.hh revision 5595
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 565529Snate@binkert.org#include "params/DerivO3CPU.hh" 575529Snate@binkert.org 582316SN/Atemplate <class> 592316SN/Aclass Checker; 602680Sktlim@umich.educlass ThreadContext; 612817Sksewell@umich.edutemplate <class> 622817Sksewell@umich.educlass O3ThreadContext; 632843Sktlim@umich.edu 642843Sktlim@umich.educlass Checkpoint; 652669Sktlim@umich.educlass MemObject; 661060SN/Aclass Process; 671060SN/A 685529Snate@binkert.orgclass BaseCPUParams; 695529Snate@binkert.org 702733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 711060SN/A{ 721060SN/A //Stuff that's pretty ISA independent will go here. 731060SN/A public: 745529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 752292SN/A 762292SN/A void regStats(); 772632Sstever@eecs.umich.edu 782817Sksewell@umich.edu /** Sets this CPU's ID. */ 792817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 802817Sksewell@umich.edu 812817Sksewell@umich.edu /** Reads this CPU's ID. */ 822669Sktlim@umich.edu int readCpuId() { return cpu_id; } 831681SN/A 841685SN/A protected: 851681SN/A int cpu_id; 861060SN/A}; 871060SN/A 882348SN/A/** 892348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 902348SN/A * within it, as well as all of the time buffers between stages. The 912348SN/A * tick() function for the CPU is defined here. 922348SN/A */ 931060SN/Atemplate <class Impl> 942733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 951060SN/A{ 961060SN/A public: 972325SN/A // Typedefs from the Impl here. 981060SN/A typedef typename Impl::CPUPol CPUPolicy; 991061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1004329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1011060SN/A 1025595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1032292SN/A typedef O3ThreadState<Impl> Thread; 1042292SN/A 1052292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1062292SN/A 1072817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1082829Sksewell@umich.edu 1091060SN/A public: 1101060SN/A enum Status { 1111060SN/A Running, 1121060SN/A Idle, 1131060SN/A Halted, 1142307SN/A Blocked, 1152307SN/A SwitchedOut 1161060SN/A }; 1171060SN/A 1183781Sgblack@eecs.umich.edu TheISA::ITB * itb; 1193781Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1203781Sgblack@eecs.umich.edu 1212292SN/A /** Overall CPU status. */ 1221060SN/A Status _status; 1231060SN/A 1242829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1252829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1262829Sksewell@umich.edu 1271060SN/A private: 1281060SN/A class TickEvent : public Event 1291060SN/A { 1301060SN/A private: 1312292SN/A /** Pointer to the CPU. */ 1321755SN/A FullO3CPU<Impl> *cpu; 1331060SN/A 1341060SN/A public: 1352292SN/A /** Constructs a tick event. */ 1361755SN/A TickEvent(FullO3CPU<Impl> *c); 1372292SN/A 1382292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1391060SN/A void process(); 1402292SN/A /** Returns the description of the tick event. */ 1415336Shines@cs.fsu.edu const char *description() const; 1421060SN/A }; 1431060SN/A 1442292SN/A /** The tick event used for scheduling CPU ticks. */ 1451060SN/A TickEvent tickEvent; 1461060SN/A 1472292SN/A /** Schedule tick event, regardless of its current state. */ 1481060SN/A void scheduleTickEvent(int delay) 1491060SN/A { 1501060SN/A if (tickEvent.squashed()) 1515100Ssaidi@eecs.umich.edu tickEvent.reschedule(nextCycle(curTick + ticks(delay))); 1521060SN/A else if (!tickEvent.scheduled()) 1535100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(delay))); 1541060SN/A } 1551060SN/A 1562292SN/A /** Unschedule tick event, regardless of its current state. */ 1571060SN/A void unscheduleTickEvent() 1581060SN/A { 1591060SN/A if (tickEvent.scheduled()) 1601060SN/A tickEvent.squash(); 1611060SN/A } 1621060SN/A 1632829Sksewell@umich.edu class ActivateThreadEvent : public Event 1642829Sksewell@umich.edu { 1652829Sksewell@umich.edu private: 1662829Sksewell@umich.edu /** Number of Thread to Activate */ 1672829Sksewell@umich.edu int tid; 1682829Sksewell@umich.edu 1692829Sksewell@umich.edu /** Pointer to the CPU. */ 1702829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1712829Sksewell@umich.edu 1722829Sksewell@umich.edu public: 1732829Sksewell@umich.edu /** Constructs the event. */ 1742829Sksewell@umich.edu ActivateThreadEvent(); 1752829Sksewell@umich.edu 1762829Sksewell@umich.edu /** Initialize Event */ 1772829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1782829Sksewell@umich.edu 1792829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1802829Sksewell@umich.edu void process(); 1812829Sksewell@umich.edu 1822829Sksewell@umich.edu /** Returns the description of the event. */ 1835336Shines@cs.fsu.edu const char *description() const; 1842829Sksewell@umich.edu }; 1852829Sksewell@umich.edu 1862829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1872829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1882829Sksewell@umich.edu { 1892829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1902829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1914030Sktlim@umich.edu activateThreadEvent[tid]. 1925100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 1932829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1944030Sktlim@umich.edu activateThreadEvent[tid]. 1955100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 1962829Sksewell@umich.edu } 1972829Sksewell@umich.edu 1982829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1992829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 2002829Sksewell@umich.edu { 2012829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2022829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2032829Sksewell@umich.edu } 2042829Sksewell@umich.edu 2055595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 2065595Sgblack@eecs.umich.edu TheISA::IntReg getSyscallArg(int i, int tid); 2075595Sgblack@eecs.umich.edu 2085595Sgblack@eecs.umich.edu /** Used to shift args for indirect syscall. */ 2095595Sgblack@eecs.umich.edu void setSyscallArg(int i, TheISA::IntReg val, int tid); 2105595Sgblack@eecs.umich.edu#endif 2115595Sgblack@eecs.umich.edu 2122829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2132829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2142829Sksewell@umich.edu 2152875Sksewell@umich.edu class DeallocateContextEvent : public Event 2162875Sksewell@umich.edu { 2172875Sksewell@umich.edu private: 2183221Sktlim@umich.edu /** Number of Thread to deactivate */ 2192875Sksewell@umich.edu int tid; 2202875Sksewell@umich.edu 2213221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2223221Sktlim@umich.edu bool remove; 2233221Sktlim@umich.edu 2242875Sksewell@umich.edu /** Pointer to the CPU. */ 2252875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2262875Sksewell@umich.edu 2272875Sksewell@umich.edu public: 2282875Sksewell@umich.edu /** Constructs the event. */ 2292875Sksewell@umich.edu DeallocateContextEvent(); 2302875Sksewell@umich.edu 2312875Sksewell@umich.edu /** Initialize Event */ 2322875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2332875Sksewell@umich.edu 2342875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2352875Sksewell@umich.edu void process(); 2362875Sksewell@umich.edu 2373221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2383221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2393221Sktlim@umich.edu 2402875Sksewell@umich.edu /** Returns the description of the event. */ 2415336Shines@cs.fsu.edu const char *description() const; 2422875Sksewell@umich.edu }; 2432875Sksewell@umich.edu 2442875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2453221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2462875Sksewell@umich.edu { 2472875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2482875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2494030Sktlim@umich.edu deallocateContextEvent[tid]. 2505100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 2512875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2524030Sktlim@umich.edu deallocateContextEvent[tid]. 2535100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 2542875Sksewell@umich.edu } 2552875Sksewell@umich.edu 2562875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2572875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2582875Sksewell@umich.edu { 2592875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2602875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2612875Sksewell@umich.edu } 2622875Sksewell@umich.edu 2632875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2642875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2652875Sksewell@umich.edu 2661060SN/A public: 2672292SN/A /** Constructs a CPU with the given parameters. */ 2685595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2692292SN/A /** Destructor. */ 2701755SN/A ~FullO3CPU(); 2711060SN/A 2722292SN/A /** Registers statistics. */ 2735595Sgblack@eecs.umich.edu void regStats(); 2741684SN/A 2755358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2765358Sgblack@eecs.umich.edu { 2775358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2785358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2795358Sgblack@eecs.umich.edu } 2805358Sgblack@eecs.umich.edu 2815358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2825358Sgblack@eecs.umich.edu { 2835358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2845358Sgblack@eecs.umich.edu } 2855358Sgblack@eecs.umich.edu 2865358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2875358Sgblack@eecs.umich.edu { 2885358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2895358Sgblack@eecs.umich.edu } 2905358Sgblack@eecs.umich.edu 2914988Sgblack@eecs.umich.edu /** Translates instruction requestion. */ 2924988Sgblack@eecs.umich.edu Fault translateInstReq(RequestPtr &req, Thread *thread) 2934988Sgblack@eecs.umich.edu { 2944988Sgblack@eecs.umich.edu return this->itb->translate(req, thread->getTC()); 2954988Sgblack@eecs.umich.edu } 2964988Sgblack@eecs.umich.edu 2974988Sgblack@eecs.umich.edu /** Translates data read request. */ 2984988Sgblack@eecs.umich.edu Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2994988Sgblack@eecs.umich.edu { 3004988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), false); 3014988Sgblack@eecs.umich.edu } 3024988Sgblack@eecs.umich.edu 3034988Sgblack@eecs.umich.edu /** Translates data write request. */ 3044988Sgblack@eecs.umich.edu Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 3054988Sgblack@eecs.umich.edu { 3064988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), true); 3074988Sgblack@eecs.umich.edu } 3084988Sgblack@eecs.umich.edu 3092871Sktlim@umich.edu /** Returns a specific port. */ 3102871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 3112871Sktlim@umich.edu 3122292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3132292SN/A * activity to see if the CPU should deschedule itself. 3142292SN/A */ 3151684SN/A void tick(); 3161684SN/A 3172292SN/A /** Initialize the CPU */ 3181060SN/A void init(); 3191060SN/A 3202834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3212834Sksewell@umich.edu int numActiveThreads() 3222834Sksewell@umich.edu { return activeThreads.size(); } 3232834Sksewell@umich.edu 3242829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3252875Sksewell@umich.edu void activateThread(unsigned tid); 3262875Sksewell@umich.edu 3272875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3282875Sksewell@umich.edu void deactivateThread(unsigned tid); 3292829Sksewell@umich.edu 3302292SN/A /** Setup CPU to insert a thread's context */ 3312292SN/A void insertThread(unsigned tid); 3321060SN/A 3332292SN/A /** Remove all of a thread's context from CPU */ 3342292SN/A void removeThread(unsigned tid); 3352292SN/A 3362292SN/A /** Count the Total Instructions Committed in the CPU. */ 3372292SN/A virtual Counter totalInstructions() const 3382292SN/A { 3392292SN/A Counter total(0); 3402292SN/A 3412292SN/A for (int i=0; i < thread.size(); i++) 3422292SN/A total += thread[i]->numInst; 3432292SN/A 3442292SN/A return total; 3452292SN/A } 3462292SN/A 3472292SN/A /** Add Thread to Active Threads List. */ 3482292SN/A void activateContext(int tid, int delay); 3492292SN/A 3502292SN/A /** Remove Thread from Active Threads List */ 3512292SN/A void suspendContext(int tid); 3522292SN/A 3532292SN/A /** Remove Thread from Active Threads List && 3543221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3552292SN/A */ 3563221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3572292SN/A 3582292SN/A /** Remove Thread from Active Threads List && 3592292SN/A * Remove Thread Context from CPU. 3602292SN/A */ 3612292SN/A void haltContext(int tid); 3622292SN/A 3632292SN/A /** Activate a Thread When CPU Resources are Available. */ 3642292SN/A void activateWhenReady(int tid); 3652292SN/A 3662292SN/A /** Add or Remove a Thread Context in the CPU. */ 3672292SN/A void doContextSwitch(); 3682292SN/A 3692292SN/A /** Update The Order In Which We Process Threads. */ 3702292SN/A void updateThreadPriority(); 3712292SN/A 3722864Sktlim@umich.edu /** Serialize state. */ 3732864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3742864Sktlim@umich.edu 3752864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3762864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3772864Sktlim@umich.edu 3782864Sktlim@umich.edu public: 3795595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3805595Sgblack@eecs.umich.edu /** Executes a syscall. 3815595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3822292SN/A */ 3835595Sgblack@eecs.umich.edu void syscall(int64_t callnum, int tid); 3845595Sgblack@eecs.umich.edu 3855595Sgblack@eecs.umich.edu /** Sets the return value of a syscall. */ 3865595Sgblack@eecs.umich.edu void setSyscallReturn(SyscallReturn return_value, int tid); 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu#endif 3892292SN/A 3902843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3912843Sktlim@umich.edu * order to stop all memory accesses. */ 3922905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3932843Sktlim@umich.edu 3942843Sktlim@umich.edu /** Resumes execution after a drain. */ 3952843Sktlim@umich.edu virtual void resume(); 3962292SN/A 3972348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3982843Sktlim@umich.edu void signalDrained(); 3992843Sktlim@umich.edu 4002843Sktlim@umich.edu /** Switches out this CPU. */ 4012843Sktlim@umich.edu virtual void switchOut(); 4022316SN/A 4032348SN/A /** Takes over from another CPU. */ 4042843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 4051060SN/A 4061060SN/A /** Get the current instruction sequence number, and increment it. */ 4072316SN/A InstSeqNum getAndIncrementInstSeq() 4082316SN/A { return globalSeqNum++; } 4091060SN/A 4105595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 4115595Sgblack@eecs.umich.edu void trap(Fault fault, unsigned tid); 4125595Sgblack@eecs.umich.edu 4131858SN/A#if FULL_SYSTEM 4145595Sgblack@eecs.umich.edu /** Posts an interrupt. */ 4155595Sgblack@eecs.umich.edu void post_interrupt(int int_num, int index); 4165595Sgblack@eecs.umich.edu 4175595Sgblack@eecs.umich.edu /** HW return from error interrupt. */ 4185595Sgblack@eecs.umich.edu Fault hwrei(unsigned tid); 4195595Sgblack@eecs.umich.edu 4205595Sgblack@eecs.umich.edu bool simPalCheck(int palFunc, unsigned tid); 4215595Sgblack@eecs.umich.edu 4225595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 4235595Sgblack@eecs.umich.edu Fault getInterrupts(); 4245595Sgblack@eecs.umich.edu 4255595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 4265595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 4275595Sgblack@eecs.umich.edu 4285595Sgblack@eecs.umich.edu /** Halts the CPU. */ 4295595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 4305595Sgblack@eecs.umich.edu 4314192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 4324192Sktlim@umich.edu * reflect change in memory connections. */ 4334192Sktlim@umich.edu void updateMemPorts(); 4344192Sktlim@umich.edu 4351060SN/A /** Check if this address is a valid instruction address. */ 4361060SN/A bool validInstAddr(Addr addr) { return true; } 4371060SN/A 4381060SN/A /** Check if this address is a valid data address. */ 4391060SN/A bool validDataAddr(Addr addr) { return true; } 4401060SN/A 4411060SN/A /** Get instruction asid. */ 4422292SN/A int getInstAsid(unsigned tid) 4432292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 4441060SN/A 4451060SN/A /** Get data asid. */ 4462292SN/A int getDataAsid(unsigned tid) 4472292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 4481060SN/A#else 4492292SN/A /** Get instruction asid. */ 4502292SN/A int getInstAsid(unsigned tid) 4512683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4521060SN/A 4532292SN/A /** Get data asid. */ 4542292SN/A int getDataAsid(unsigned tid) 4552683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4561060SN/A 4571060SN/A#endif 4581060SN/A 4592348SN/A /** Register accessors. Index refers to the physical register index. */ 4605595Sgblack@eecs.umich.edu 4615595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4625595Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); 4635595Sgblack@eecs.umich.edu 4645595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4655595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4665595Sgblack@eecs.umich.edu */ 4675595Sgblack@eecs.umich.edu TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); 4685595Sgblack@eecs.umich.edu 4695595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4705595Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); 4715595Sgblack@eecs.umich.edu 4725595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4735595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4745595Sgblack@eecs.umich.edu */ 4755595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4765595Sgblack@eecs.umich.edu unsigned tid); 4775595Sgblack@eecs.umich.edu 4781060SN/A uint64_t readIntReg(int reg_idx); 4791060SN/A 4803781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4811060SN/A 4823781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 4831060SN/A 4843781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4852455SN/A 4863781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 4871060SN/A 4881060SN/A void setIntReg(int reg_idx, uint64_t val); 4891060SN/A 4903781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4911060SN/A 4923781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4931060SN/A 4943781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4952455SN/A 4963781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4971060SN/A 4982292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4991060SN/A 5002292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 5011060SN/A 5022292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 5032292SN/A 5042292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 5052292SN/A 5062348SN/A /** Architectural register accessors. Looks up in the commit 5072348SN/A * rename table to obtain the true physical index of the 5082348SN/A * architected register first, then accesses that physical 5092348SN/A * register. 5102348SN/A */ 5112292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 5122292SN/A 5132292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 5142292SN/A 5152292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 5162292SN/A 5172292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 5182292SN/A 5192348SN/A /** Reads the commit PC of a specific thread. */ 5204636Sgblack@eecs.umich.edu Addr readPC(unsigned tid); 5212292SN/A 5222348SN/A /** Sets the commit PC of a specific thread. */ 5232348SN/A void setPC(Addr new_PC, unsigned tid); 5242292SN/A 5254636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5264636Sgblack@eecs.umich.edu Addr readMicroPC(unsigned tid); 5274636Sgblack@eecs.umich.edu 5284636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 5294636Sgblack@eecs.umich.edu void setMicroPC(Addr new_microPC, unsigned tid); 5304636Sgblack@eecs.umich.edu 5312348SN/A /** Reads the next PC of a specific thread. */ 5324636Sgblack@eecs.umich.edu Addr readNextPC(unsigned tid); 5332292SN/A 5342348SN/A /** Sets the next PC of a specific thread. */ 5354636Sgblack@eecs.umich.edu void setNextPC(Addr val, unsigned tid); 5361060SN/A 5372756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 5384636Sgblack@eecs.umich.edu Addr readNextNPC(unsigned tid); 5392756Sksewell@umich.edu 5402756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 5414636Sgblack@eecs.umich.edu void setNextNPC(Addr val, unsigned tid); 5424636Sgblack@eecs.umich.edu 5434636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 5444636Sgblack@eecs.umich.edu Addr readNextMicroPC(unsigned tid); 5454636Sgblack@eecs.umich.edu 5464636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 5474636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val, unsigned tid); 5482756Sksewell@umich.edu 5495595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5505595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5515595Sgblack@eecs.umich.edu * state through the TC. 5525595Sgblack@eecs.umich.edu */ 5535595Sgblack@eecs.umich.edu void squashFromTC(unsigned tid); 5545595Sgblack@eecs.umich.edu 5551060SN/A /** Function to add instruction onto the head of the list of the 5561060SN/A * instructions. Used when new instructions are fetched. 5571060SN/A */ 5582292SN/A ListIt addInst(DynInstPtr &inst); 5591060SN/A 5601060SN/A /** Function to tell the CPU that an instruction has completed. */ 5612292SN/A void instDone(unsigned tid); 5621060SN/A 5632292SN/A /** Add Instructions to the CPU Remove List*/ 5642292SN/A void addToRemoveList(DynInstPtr &inst); 5651060SN/A 5662325SN/A /** Remove an instruction from the front end of the list. There's 5672325SN/A * no restriction on location of the instruction. 5681060SN/A */ 5691061SN/A void removeFrontInst(DynInstPtr &inst); 5701060SN/A 5712935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5722935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5734632Sgblack@eecs.umich.edu void removeInstsNotInROB(unsigned tid); 5741060SN/A 5751062SN/A /** Remove all instructions younger than the given sequence number. */ 5762292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 5772292SN/A 5782348SN/A /** Removes the instruction pointed to by the iterator. */ 5792292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 5802292SN/A 5812348SN/A /** Cleans up all instructions on the remove list. */ 5822292SN/A void cleanUpRemovedInsts(); 5831062SN/A 5842348SN/A /** Debug function to print all instructions on the list. */ 5851060SN/A void dumpInsts(); 5861060SN/A 5871060SN/A public: 5881060SN/A /** List of all the instructions in flight. */ 5892292SN/A std::list<DynInstPtr> instList; 5901060SN/A 5912292SN/A /** List of all the instructions that will be removed at the end of this 5922292SN/A * cycle. 5932292SN/A */ 5942292SN/A std::queue<ListIt> removeList; 5952292SN/A 5962325SN/A#ifdef DEBUG 5972348SN/A /** Debug structure to keep track of the sequence numbers still in 5982348SN/A * flight. 5992348SN/A */ 6002292SN/A std::set<InstSeqNum> snList; 6012325SN/A#endif 6022292SN/A 6032325SN/A /** Records if instructions need to be removed this cycle due to 6042325SN/A * being retired or squashed. 6052292SN/A */ 6062292SN/A bool removeInstsThisCycle; 6072292SN/A 6081060SN/A protected: 6091060SN/A /** The fetch stage. */ 6101060SN/A typename CPUPolicy::Fetch fetch; 6111060SN/A 6121060SN/A /** The decode stage. */ 6131060SN/A typename CPUPolicy::Decode decode; 6141060SN/A 6151060SN/A /** The dispatch stage. */ 6161060SN/A typename CPUPolicy::Rename rename; 6171060SN/A 6181060SN/A /** The issue/execute/writeback stages. */ 6191060SN/A typename CPUPolicy::IEW iew; 6201060SN/A 6211060SN/A /** The commit stage. */ 6221060SN/A typename CPUPolicy::Commit commit; 6231060SN/A 6241060SN/A /** The register file. */ 6251060SN/A typename CPUPolicy::RegFile regFile; 6261060SN/A 6271060SN/A /** The free list. */ 6281060SN/A typename CPUPolicy::FreeList freeList; 6291060SN/A 6301060SN/A /** The rename map. */ 6312292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6322292SN/A 6332292SN/A /** The commit rename map. */ 6342292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6351060SN/A 6361060SN/A /** The re-order buffer. */ 6371060SN/A typename CPUPolicy::ROB rob; 6381060SN/A 6392292SN/A /** Active Threads List */ 6402292SN/A std::list<unsigned> activeThreads; 6412292SN/A 6422292SN/A /** Integer Register Scoreboard */ 6432292SN/A Scoreboard scoreboard; 6442292SN/A 6451060SN/A public: 6462292SN/A /** Enum to give each stage a specific index, so when calling 6472292SN/A * activateStage() or deactivateStage(), they can specify which stage 6482292SN/A * is being activated/deactivated. 6492292SN/A */ 6502292SN/A enum StageIdx { 6512292SN/A FetchIdx, 6522292SN/A DecodeIdx, 6532292SN/A RenameIdx, 6542292SN/A IEWIdx, 6552292SN/A CommitIdx, 6562292SN/A NumStages }; 6572292SN/A 6581060SN/A /** Typedefs from the Impl to get the structs that each of the 6591060SN/A * time buffers should use. 6601060SN/A */ 6611061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6621060SN/A 6631061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6641060SN/A 6651061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6661060SN/A 6671061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6681060SN/A 6691061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6701060SN/A 6711060SN/A /** The main time buffer to do backwards communication. */ 6721060SN/A TimeBuffer<TimeStruct> timeBuffer; 6731060SN/A 6741060SN/A /** The fetch stage's instruction queue. */ 6751060SN/A TimeBuffer<FetchStruct> fetchQueue; 6761060SN/A 6771060SN/A /** The decode stage's instruction queue. */ 6781060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6791060SN/A 6801060SN/A /** The rename stage's instruction queue. */ 6811060SN/A TimeBuffer<RenameStruct> renameQueue; 6821060SN/A 6831060SN/A /** The IEW stage's instruction queue. */ 6841060SN/A TimeBuffer<IEWStruct> iewQueue; 6851060SN/A 6862348SN/A private: 6872348SN/A /** The activity recorder; used to tell if the CPU has any 6882348SN/A * activity remaining or if it can go to idle and deschedule 6892348SN/A * itself. 6902348SN/A */ 6912325SN/A ActivityRecorder activityRec; 6921060SN/A 6932348SN/A public: 6942348SN/A /** Records that there was time buffer activity this cycle. */ 6952325SN/A void activityThisCycle() { activityRec.activity(); } 6962292SN/A 6972348SN/A /** Changes a stage's status to active within the activity recorder. */ 6982325SN/A void activateStage(const StageIdx idx) 6992325SN/A { activityRec.activateStage(idx); } 7002292SN/A 7012348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 7022325SN/A void deactivateStage(const StageIdx idx) 7032325SN/A { activityRec.deactivateStage(idx); } 7042292SN/A 7052292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7062292SN/A void wakeCPU(); 7072260SN/A 7082292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7092292SN/A int getFreeTid(); 7102292SN/A 7112292SN/A public: 7122680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7132680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 7141681SN/A { 7152680Sktlim@umich.edu return thread[tid]->getTC(); 7162190SN/A } 7172190SN/A 7182292SN/A /** The global sequence number counter. */ 7193093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7201060SN/A 7214598Sbinkertn@umich.edu#if USE_CHECKER 7222348SN/A /** Pointer to the checker, which can dynamically verify 7232348SN/A * instruction results at run time. This can be set to NULL if it 7242348SN/A * is not being used. 7252348SN/A */ 7262316SN/A Checker<DynInstPtr> *checker; 7274598Sbinkertn@umich.edu#endif 7282316SN/A 7291858SN/A#if FULL_SYSTEM 7302292SN/A /** Pointer to the system. */ 7311060SN/A System *system; 7321060SN/A 7332292SN/A /** Pointer to physical memory. */ 7341060SN/A PhysicalMemory *physmem; 7352292SN/A#endif 7361060SN/A 7372843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 7382843Sktlim@umich.edu Event *drainEvent; 7392843Sktlim@umich.edu 7402843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 7412843Sktlim@umich.edu int drainCount; 7422316SN/A 7432348SN/A /** Pointers to all of the threads in the CPU. */ 7442292SN/A std::vector<Thread *> thread; 7452260SN/A 7462292SN/A /** Whether or not the CPU should defer its registration. */ 7471060SN/A bool deferRegistration; 7481060SN/A 7492292SN/A /** Is there a context switch pending? */ 7502292SN/A bool contextSwitch; 7511060SN/A 7522292SN/A /** Threads Scheduled to Enter CPU */ 7532292SN/A std::list<int> cpuWaitList; 7542292SN/A 7552292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7562292SN/A Tick lastRunningCycle; 7572292SN/A 7582829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7592829Sksewell@umich.edu Tick lastActivatedCycle; 7602829Sksewell@umich.edu 7612292SN/A /** Number of Threads CPU can process */ 7622292SN/A unsigned numThreads; 7632292SN/A 7642292SN/A /** Mapping for system thread id to cpu id */ 7652292SN/A std::map<unsigned,unsigned> threadMap; 7662292SN/A 7672292SN/A /** Available thread ids in the cpu*/ 7682292SN/A std::vector<unsigned> tids; 7692292SN/A 7705595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7715595Sgblack@eecs.umich.edu template <class T> 7725595Sgblack@eecs.umich.edu Fault read(RequestPtr &req, T &data, int load_idx) 7735595Sgblack@eecs.umich.edu { 7745595Sgblack@eecs.umich.edu return this->iew.ldstQueue.read(req, data, load_idx); 7755595Sgblack@eecs.umich.edu } 7765595Sgblack@eecs.umich.edu 7775595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7785595Sgblack@eecs.umich.edu template <class T> 7795595Sgblack@eecs.umich.edu Fault write(RequestPtr &req, T &data, int store_idx) 7805595Sgblack@eecs.umich.edu { 7815595Sgblack@eecs.umich.edu return this->iew.ldstQueue.write(req, data, store_idx); 7825595Sgblack@eecs.umich.edu } 7835595Sgblack@eecs.umich.edu 7845595Sgblack@eecs.umich.edu Addr lockAddr; 7855595Sgblack@eecs.umich.edu 7865595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7875595Sgblack@eecs.umich.edu bool lockFlag; 7885595Sgblack@eecs.umich.edu 7892292SN/A /** Stat for total number of times the CPU is descheduled. */ 7902292SN/A Stats::Scalar<> timesIdled; 7912292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7922292SN/A Stats::Scalar<> idleCycles; 7932292SN/A /** Stat for the number of committed instructions per thread. */ 7942292SN/A Stats::Vector<> committedInsts; 7952292SN/A /** Stat for the total number of committed instructions. */ 7962292SN/A Stats::Scalar<> totalCommittedInsts; 7972292SN/A /** Stat for the CPI per thread. */ 7982292SN/A Stats::Formula cpi; 7992292SN/A /** Stat for the total CPI. */ 8002292SN/A Stats::Formula totalCpi; 8012292SN/A /** Stat for the IPC per thread. */ 8022292SN/A Stats::Formula ipc; 8032292SN/A /** Stat for the total IPC. */ 8042292SN/A Stats::Formula totalIpc; 8051060SN/A}; 8061060SN/A 8072325SN/A#endif // __CPU_O3_CPU_HH__ 808